CN116915052A - Synchronous buck DCDC architecture capable of automatically preventing abrupt change of duty ratio during low buck ratio operation - Google Patents
Synchronous buck DCDC architecture capable of automatically preventing abrupt change of duty ratio during low buck ratio operation Download PDFInfo
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- CN116915052A CN116915052A CN202310452291.7A CN202310452291A CN116915052A CN 116915052 A CN116915052 A CN 116915052A CN 202310452291 A CN202310452291 A CN 202310452291A CN 116915052 A CN116915052 A CN 116915052A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a synchronous buck DCDC framework capable of automatically preventing abrupt change of duty ratio when working at low buck ratio, which comprises an error amplifier, a voltage comparator, a PWM (pulse width modulation) generating circuit, a PWM signal control module, a low-side switching tube control module, a high-side switching tube and a low-side switching tube, wherein the error amplifier compares an input voltage reference signal Vref with a voltage feedback signal FB to output an error comparison result, and the voltage comparator compares the input error comparison result with a switching tube current detection signal to output a voltage comparison result. The synchronous buck DCDC framework capable of automatically preventing abrupt change of the duty ratio when the low buck ratio works is used for overcoming larger fluctuation of the VOUT voltage caused by abrupt change of the duty ratio when VIN and VOUT voltages on the current equipment are close, and can enable the output voltage VOUT to keep lower ripple under the condition of arbitrary input VIN.
Description
Technical Field
The invention belongs to the technical field of synchronous buck DCDC architecture which can automatically prevent duty ratio from suddenly changing during low buck ratio operation.
Background
Synchronous buck DCDC in a fixed frequency, peak current control mode has wide application in the industry, for example, from 24V,48V voltage bus buck to 3.3V/5V to power other low voltage modules.
Fig. 3 shows waveforms of the synchronous buck DCDC in the fixed frequency peak current control mode when operating at a low buck ratio (VIN, VOUT voltage is close), where clk_pwm is the falling edge synchronous clock, SW is the switching node, ic is the inductor peak current control signal, and IL is the inductor current. As shown, the switch is turned on in synchronization with the falling edge of clock clk_pwm and turned off when the inductor current reaches IL. When VIN, VOUT voltage is very close and inductor current rises very slowly, it may happen that inductor current has not yet reached control current Ic when the falling edge of the second synchronous clock clk2 arrives, and the switch will remain open until IL reaches Ic. If the inductor current IL reaches the control current Ic immediately after the falling edge of clk2, the switching tube will be turned off, the inductor current IL will fall at VOUT/L, and the switching tube will not be turned on again until the falling edge of the third synchronizing clock clk3, and the inductor current IL rises again. As can be seen from fig. 3, when VIN and VOUT approach to a certain level, frequency hopping occurs, the duty cycle is suddenly changed, resulting in a large fluctuation in the output VOUT voltage.
Therefore, the above problems are further improved.
Disclosure of Invention
The invention mainly aims to provide a synchronous buck DCDC framework capable of automatically preventing abrupt change of duty ratio when working at low buck ratio, which is used for overcoming larger fluctuation of VOUT voltage caused by abrupt change of duty ratio when VIN and VOUT voltages on the current equipment are close, and can enable output voltage VOUT to keep lower ripple under the condition of arbitrary input VIN.
In order to achieve the above purpose, the invention provides a synchronous buck DCDC architecture capable of automatically preventing abrupt change of duty ratio when working with low buck ratio, comprising an error amplifier, a voltage comparator, a PWM generating circuit, a PWM signal control module, a low side switching tube control module, a high side switching tube and a low side switching tube, wherein:
the error amplifier compares an input voltage reference signal Vref with a voltage feedback signal FB to output an error comparison result;
the voltage comparator compares the input error comparison result with a switching tube current detection signal (detection of an input power supply VIN) to output a voltage comparison result;
the PWM generating circuit is used for respectively inputting a voltage comparison result, a system clock and a grid control signal HG output by the PWM signal control module, and respectively outputting a PWM signal Data and a Flag signal Flag with synchronous rising edges and system clock falling edges after processing, so as to control the working states of the high-side switching tube and the low-side switching tube;
the PWM signal control module is used for respectively inputting a PWM signal Data, a Flag signal Flag and a grid control signal LG output by the low-side switching tube control module, and respectively outputting the output grid control signal HG to the grid of the high-side switching tube and one input end of the PWM generating circuit after processing, so as to be used for controlling the on and off of the high-side switching tube;
the low-side switching tube control module is used for respectively inputting a PWM signal Data and a Flag signal Flag, and outputting an output grid control signal HG to a grid of the low-side switching tube and an input end of the PWM signal control module after processing, so as to be used for controlling the on and off of the low-side switching tube;
the drain electrode of the high-side switching tube is connected with the input power supply VIN, and the source electrode of the high-side switching tube is electrically connected with the drain electrode of the low-side switching tube and is commonly connected with the output power supply OUT through an inductor.
As a further preferable embodiment of the above-described embodiment, for the PWM generation circuit:
when the current IL of the high-side switching tube exceeds the control current Ic, the voltage comparator outputs a voltage comparison result of the overcurrent signal to reset the PWM signal Data and the Flag signal Flag is generated by the gate control signal HG of the high-side switching tube when detecting the falling edge of the system clock:
when the system clock falls, if the gate control signal HG is low, the Flag signal Flag is reset, and if the gate control signal HG is high, the Flag signal Flag is set, so that the Flag signal Flag will be set when the PWM signal Data continues to be high for more than one clock period.
As a further preferable embodiment of the above-described embodiment, for the PWM signal control module:
under normal conditions, the gate control signal HG is in phase with the PWM signal Data, the rising edge is synchronous with the falling edge of the system clock, and when the Flag signal Flag is set, the output gate control signal HG is not synchronous with the falling edge of the system clock, so that the gate control signal LG of the low-side switching tube will be set only if the gate control signal LG is reset.
As a further preferable embodiment of the above-described embodiment, for the low-side switching tube control module:
under normal conditions, the gate control signal LG and the PWM signal Data are inverted, synchronously reset at the falling edge of the system clock, when the Flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock, the set time is limited by the built-in timer, and when the set time of the gate control signal LG reaches the timer timing time, the gate control signal LG is reset.
As a further preferable embodiment of the above-described embodiment, when the voltages of the input power source VIN and the output power source VOUT are close to each other:
the PWM signal Data is set when the first clock clk1 falls, the grid control signal HG is set at the same time, the high-side switching tube is conducted, the grid control signal LG is reset at the same time, and the low-side switching tube is closed;
the gate control signal HG is high level when the second clock clk2 falls, the high-side switching tube is opened for more than one clock period, the Flag signal Flag is set, then the current IL of the inductor reaches the control current Ic at the moment T1, the gate control signal HG is reset, the high-side switching tube is closed, the gate control signal LG is set, and the low-side rectifying tube is opened;
the maximum open time Max Toff of the gate control signal LG is controlled by an internal timer, the gate control signal LG is forced to reset when the open time reaches Max Toff, the low side rectifier is turned off while the gate control signal HG is set, and the high side switch is turned on until the current IL of the inductor reaches the control current Ic.
As a further preferable technical solution of the above technical solution, a resistor RT and a resistor RB are connected in series between the output power source VOUT and the ground, and a tap signal between the resistor RT and the resistor RB is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier.
Drawings
Fig. 1 is a circuit configuration diagram of a synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes when the low buck ratio of the present invention is operated.
Fig. 2 is a timing control diagram of signals when VIN and VOUT of the synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes during low buck ratio operation of the present invention are close.
Fig. 3 is a waveform diagram of a conventional synchronous buck DCDC in a fixed frequency peak current control mode operating at a low buck ratio.
The reference numerals include: 01. an error amplifier; 02. a voltage comparator; 03. a PWM generating circuit; 04. a PWM signal control module; 05. a low side switching tube control module; 06. a high side switching tube; 07. a low side switching tube; 08 inductance; 09. a resistor RT;10 resistance RB.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
In a preferred embodiment of the invention, the person skilled in the art will note that the resistors and the like to which the invention relates can be regarded as prior art.
Preferred embodiments.
The invention discloses a synchronous buck DCDC framework capable of automatically preventing abrupt change of duty ratio when working at low buck ratio, which comprises an error amplifier 01, a voltage comparator 02, a PWM generating circuit 03, a PWM signal control module 04, a low-side switching tube control module 05, a high-side switching tube 06 and a low-side switching tube 07, wherein:
the error amplifier 01 compares an input voltage reference signal Vref with a voltage feedback signal FB to output an error comparison result;
the voltage comparator 02 compares the input error comparison result with a switching tube current detection signal (detection of the input power source VIN) to output a voltage comparison result;
the PWM generation circuit 03 inputs the voltage comparison result, the system clock and the gate control signal HG output by the PWM signal control module, and outputs the PWM signal Data and the Flag signal Flag with the rising edge synchronized with the falling edge of the system clock after processing, so as to control the working states of the high-side switching tube 06 and the low-side switching tube 07;
the PWM signal control module 04 inputs a PWM signal Data, a Flag signal Flag, and a gate control signal LG output by the low-side switching tube control module 05, and outputs an output gate control signal HG to a gate of the high-side switching tube 06 and an input end of the PWM generating circuit 03 after processing, so as to control on and off of the high-side switching tube 06;
the low-side switching tube control module 05 inputs a PWM signal Data and a Flag signal Flag, and outputs an output gate control signal HG to a gate of the low-side switching tube 07 and an input end of the PWM signal control module 04 after processing, so as to control the on and off of the low-side switching tube 07;
the drain electrode of the high-side switching tube 06 is connected with an input power source VIN, and the source electrode of the high-side switching tube 07 is electrically connected with the drain electrode of the low-side switching tube 07 and is commonly connected with an output power source OUT through an inductor 08.
Specifically, for the PWM generation circuit 03:
when the current IL of the high-side switching tube 06 exceeds the control current Ic, the voltage comparator 02 outputs a voltage comparison result of the overcurrent signal to reset the PWM signal Data and the Flag signal Flag is generated by the gate control signal HG of the high-side switching tube when detecting the falling edge of the system clock:
when the system clock falls, if the gate control signal HG is low, the Flag signal Flag is reset, and if the gate control signal HG is high, the Flag signal Flag is set, so that the Flag signal Flag will be set when the PWM signal Data continues to be high for more than one clock period.
More specifically, for PWM signal control module 04:
under normal conditions, the gate control signal HG is in phase with the PWM signal Data, the rising edge is synchronous with the falling edge of the system clock, and when the Flag signal Flag is set, the output gate control signal HG is not synchronous with the falling edge of the system clock, so that the gate control signal LG of the low-side switching tube 07 will be set only if the gate control signal LG is reset.
Further, for the low side switching tube control module 05:
under normal conditions, the gate control signal LG and the PWM signal Data are inverted, synchronously reset at the falling edge of the system clock, when the Flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock, the set time is limited by the built-in timer, and when the set time of the gate control signal LG reaches the timer timing time, the gate control signal LG is reset.
Further, when the voltages of the input power source VIN and the output power source VOUT are close to each other:
the PWM signal Data is set when the first clock clk1 falls, the grid control signal HG is set at the same time, the high-side switching tube is conducted, the grid control signal LG is reset at the same time, and the low-side switching tube is closed;
the gate control signal HG is high level when the second clock clk2 falls, the high-side switching tube is opened for more than one clock period, the Flag signal Flag is set, then the current IL of the inductor reaches the control current Ic at the moment T1, the gate control signal HG is reset, the high-side switching tube is closed, the gate control signal LG is set, and the low-side rectifying tube is opened;
the maximum open time Max Toff of the gate control signal LG is controlled by an internal timer, the gate control signal LG is forced to reset when the open time reaches Max Toff, the low side rectifier is turned off while the gate control signal HG is set, and the high side switch is turned on until the current IL of the inductor reaches the control current Ic.
Preferably, a resistor RT (09) and a resistor RB (10) are connected in series between the output power source VOUT and ground, and a tap signal between the resistor RT (09) and the resistor RB (10) is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier.
Preferably, the invention is applied to all occasions requiring synchronous voltage reduction DCDC of VIN and VOUT voltages approaching and adopting a fixed-frequency and peak-current control mode.
Preferably, as shown in fig. 1:
the 01 component is an error amplifier, the positive end input is connected with the voltage reference signal Vref, the negative end is connected with the output voltage feedback signal FB, and the error comparison result is output.
The component 02 is a voltage comparator, the negative input end of the voltage comparator is connected with the output error comparison result of the component 01, and the positive input end of the voltage comparator is connected with the switching tube current detection signal.
The 03 component is a PWM generating circuit, the input is connected with the output of the 02 component voltage comparator and the system clock, and the other input is connected with the grid control signal 'HG' of the 06 component. The PWM signal "Data" and the Flag signal "Flag" whose rising edges are synchronized with the falling edges of the system clock are outputted for controlling the operations of the 06-component high-side switching transistor and the 07-component rectifying transistor. When 06 part high side switch tube current IL exceeds control current Ic 02 part outputs overcurrent signal, resets "Data" signal. The Flag signal "Flag" is generated by the gate control signal "HG" of the 06 component at the time of detecting the falling edge of the system clock: if the HG signal is low when the system clock falls, the Flag signal is reset; the Flag signal "Flag" is set if the "HG" signal is high when the system clock falls. That is, if the PWM signal "Data" continues to be high for more than one clock period, the Flag bit "Flag" will be set.
The 04 component HS latch is a latch of a PWM signal. The input signals of the 04 parts are the output "Data" and "Flag" signals of the 03 parts, and the output "LG" signal of the 05 part. The output signal of the component 04 is an HG signal, and is connected to the grid electrode of the high-side switching tube of the component 06 and used for controlling the on and off of the high-side switching tube of the component 06. Under normal conditions, the "HG" signal is in phase with the PWM signal "Data", and the rising edge is synchronized with the falling edge of the system clock. When Flag signal "Flag" is set, output gate control signal "HG" is not synchronized by the falling edge of the system clock, at which time the "HG" signal will be set as long as 07 components gate control signal "LG" is reset.
The 05 component LS control is a low-side rectifying tube control module, input signals are output 'Date' and 'Flag' signals of the 03 component, output signals are 'LG', and the input signals are connected to the grid electrode of the 07 component low-side rectifying tube (namely, a low-side switching tube). In the normal mode, the LG signal is inverted from the PWM signal Data and is synchronously reset at the falling edge of the system clock. When the Flag signal 'Flag' is set, the output gate control signal 'LG' is not synchronized by the falling edge of the system clock, the set time is limited by the built-in timer, and when the set time of the 'LG' signal reaches the timer timing time, the 'LG' signal is reset.
The 06 component is a high side switching tube. The source terminal is connected to the drain terminal of the low side rectifier of the 07 component, and to the external 08 component inductance. The drain terminal is connected with the power supply VIN. The gate terminal 04 outputs "HG" which is turned on when the "HG" signal is high and turned off when the "HG" signal is low.
The 07 component is a low-side switching tube, and the drain end is connected with the source end of the 06 component high-side switching tube and is connected with an external 08 component inductor. The source terminal is grounded. The output "LG" of the gate-on 05 component is turned on when the "LG" signal is high and turned off when the "LG" signal is low.
Component 08 is an inductor with one end connected to the source of component 06 and the drain of component 07 and the other end connected to output "VOUT".
09,10 the component is a resistor RT, RB, two resistors in series between VOUT and ground, and a resistor intermediate tap signal FB is a voltage feedback signal, input to the negative side input of the component 01.
As shown in fig. 2, the timing diagram of the voltage of VIN and VOUT is close. The first clock clk1 is set at the falling edge of Data, HG is set at the same time, 06 component high-side switching tube is conducted, LG is reset at the same time, and 07 component rectifying tube is closed. The second clock clk2 falling edge "HG" is high and the 06-component high-side switch is turned on for more than one clock cycle and "Flag" is set. Then, at time T1, inductor current IL reaches control current Ic, the "HG" signal is reset, the 06-component high-side switching transistor is turned off, the "LG" signal is set, and the 07-component low-side rectifying transistor is turned on. The maximum open time Max Toff of "LG" is controlled by an internal timer, and when the open time reaches Max Toff, "LG" is forced to reset, the low-side rectifier is turned off, while the "HG" signal is set, and the high-side switching tube is turned on until the inductor current IL reaches the control current Ic.
It should be noted that technical features such as resistors related to the present application should be regarded as the prior art, and specific structures, working principles, control modes and spatial arrangement related to the technical features may be selected conventionally in the art, and should not be regarded as the invention point of the present application, which is not further specifically described in detail.
Modifications of the embodiments described above, or equivalents of some of the features may be made by those skilled in the art, and any modifications, equivalents, improvements or etc. within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. The synchronous buck DCDC framework is characterized by comprising an error amplifier, a voltage comparator, a PWM generating circuit, a PWM signal control module, a low-side switching tube control module, a high-side switching tube and a low-side switching tube, wherein the error amplifier, the voltage comparator, the PWM generating circuit, the PWM signal control module, the low-side switching tube control module, the high-side switching tube and the low-side switching tube are arranged in the framework, and the synchronous buck DCDC framework is characterized in that the duty ratio is automatically prevented from suddenly changing when the low buck ratio works:
the error amplifier compares an input voltage reference signal Vref with a voltage feedback signal FB to output an error comparison result;
the voltage comparator compares the input error comparison result with a switching tube current detection signal to output a voltage comparison result;
the PWM generating circuit is used for respectively inputting a voltage comparison result, a system clock and a grid control signal HG output by the PWM signal control module, and respectively outputting a PWM signal Data and a Flag signal Flag with synchronous rising edges and system clock falling edges after processing, so as to control the working states of the high-side switching tube and the low-side switching tube;
the PWM signal control module is used for respectively inputting a PWM signal Data, a Flag signal Flag and a grid control signal LG output by the low-side switching tube control module, and respectively outputting the output grid control signal HG to the grid of the high-side switching tube and one input end of the PWM generating circuit after processing, so as to be used for controlling the on and off of the high-side switching tube;
the low-side switching tube control module is used for respectively inputting a PWM signal Data and a Flag signal Flag, and outputting an output grid control signal HG to a grid of the low-side switching tube and an input end of the PWM signal control module after processing, so as to be used for controlling the on and off of the low-side switching tube;
the drain electrode of the high-side switching tube is connected with the input power supply VIN, and the source electrode of the high-side switching tube is electrically connected with the drain electrode of the low-side switching tube and is commonly connected with the output power supply OUT through an inductor.
2. The synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes during low buck ratio operation of claim 1, wherein for the PWM generation circuit:
when the current IL of the high-side switching tube exceeds the control current Ic, the voltage comparator outputs a voltage comparison result of the overcurrent signal to reset the PWM signal Data and the Flag signal Flag is generated by the gate control signal HG of the high-side switching tube when detecting the falling edge of the system clock:
when the system clock falls, if the gate control signal HG is low, the Flag signal Flag is reset, and if the gate control signal HG is high, the Flag signal Flag is set, so that the Flag signal Flag will be set when the PWM signal Data continues to be high for more than one clock period.
3. The synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes during low buck ratio operation of claim 2, wherein for the PWM signal control module:
under normal conditions, the gate control signal HG is in phase with the PWM signal Data, the rising edge is synchronous with the falling edge of the system clock, and when the Flag signal Flag is set, the output gate control signal HG is not synchronous with the falling edge of the system clock, so that the gate control signal LG of the low-side switching tube will be set only if the gate control signal LG is reset.
4. A synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes during low buck operation according to claim 3, wherein for the low side switching tube control module:
under normal conditions, the gate control signal LG and the PWM signal Data are inverted, synchronously reset at the falling edge of the system clock, when the Flag signal Flag is set, the output gate control signal LG is not synchronized by the falling edge of the system clock, the set time is limited by the built-in timer, and when the set time of the gate control signal LG reaches the timer timing time, the gate control signal LG is reset.
5. The synchronous buck DCDC architecture of claim 4, wherein the voltage of the input power source VIN and the output power source VOUT are close to each other when the low buck ratio is in operation to automatically prevent abrupt duty cycle transitions:
the PWM signal Data is set when the first clock clk1 falls, the grid control signal HG is set at the same time, the high-side switching tube is conducted, the grid control signal LG is reset at the same time, and the low-side switching tube is closed;
the gate control signal HG is high level when the second clock clk2 falls, the high-side switching tube is opened for more than one clock period, the Flag signal Flag is set, then the current IL of the inductor reaches the control current Ic at the moment T1, the gate control signal HG is reset, the high-side switching tube is closed, the gate control signal LG is set, and the low-side rectifying tube is opened;
the maximum open time Max Toff of the gate control signal LG is controlled by an internal timer, the gate control signal LG is forced to reset when the open time reaches Max Toff, the low side rectifier is turned off while the gate control signal HG is set, and the high side switch is turned on until the current IL of the inductor reaches the control current Ic.
6. The synchronous buck DCDC architecture for automatically preventing abrupt duty cycle changes during low buck operation according to claim 1, wherein a resistor RT and a resistor RB are connected in series between the output power source VOUT and ground, and a tap signal between the resistor RT and the resistor RB is a voltage feedback signal FB and is connected to the negative input terminal of the error amplifier.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310452291.7A CN116915052A (en) | 2023-04-21 | 2023-04-21 | Synchronous buck DCDC architecture capable of automatically preventing abrupt change of duty ratio during low buck ratio operation |
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|---|---|---|---|
| CN202310452291.7A CN116915052A (en) | 2023-04-21 | 2023-04-21 | Synchronous buck DCDC architecture capable of automatically preventing abrupt change of duty ratio during low buck ratio operation |
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- 2023-04-21 CN CN202310452291.7A patent/CN116915052A/en active Pending
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