CN116908536A - Self-adjustment-based equal-precision frequency measurement system and method - Google Patents

Abstract

The application relates to the technical field of frequency measurement systems and methods, and discloses a self-adjusting equal-precision frequency measurement system and method, comprising the following steps: CPLD and MCU; the CPLD comprises a PLL phase-locked loop module, and the PLL phase-locked loop module generates a required clock comprising a reference clock and a multi-level filtering clock; the parallel port communication module simulates Flash read-write time sequence, simplifies data read-write interaction between the MCU side and the CPLD, and ensures timeliness of data interaction; and the pulse filtering module performs filtering operation according to the set filtering grade, so that pulse signal acquisition errors caused by high-frequency interference are avoided. The application adopts two design methods of double-edge acquisition self-adjustment and acquisition window self-adjustment, improves the response time of frequency measurement while ensuring the frequency measurement precision, and can improve the frequency measurement response time by one time as fast as the traditional frequency measurement mode, thereby meeting the higher control requirement of the industrial field on rotating speed equipment and improving the dynamic control performance.

Description

A frequency measurement system and method based on self-adjustment and equal precision

Technical field

The invention relates to the field of frequency measurement systems and methods, and in particular to a frequency measurement system and method based on self-adjustment and other precision.

Background technique

With the development of modern industry, occasions such as speed regulation and control of motors or other rotating mechanical structures require not only high measurement accuracy and wide measurement range of rotational speed and frequency, but also fast response time. However, the existing speed frequency measurement solution cannot cover all control requirements, and it is difficult to achieve a good balance between frequency measurement accuracy and response time. There are two main existing speed frequency measurement solutions. The first frequency measurement method mainly collects the count value N of the pulse signal to be measured within a set time, and calculates the pulse frequency to be measured through the count value N and the set time T. F, but the pulse count value N to be measured can only exist in integers, and has an error of ±1. Therefore, this frequency measurement scheme can achieve higher frequency measurement accuracy by measuring frequency in the high frequency band, while the frequency measurement error in the low frequency band is larger. The frequency measurement response time is limited by the set time T, which is the minimum response time. It is necessary to balance the contradiction between the frequency measurement response time and the frequency measurement accuracy according to the actual frequency measurement requirements. The second period measurement method mainly collects the count value N of the reference pulse within M periods of the pulse to be measured, and calculates the period length of the pulse to be measured through the reference pulse period M and the reference pulse count value N, thereby obtaining the pulse frequency F to be measured. , since the reference pulse count value N of the M period length of the pulse to be measured is collected, so in the high frequency band, due to the short high frequency single cycle time, the frequency measurement accuracy error deviation of the fixed M period length becomes larger, and at the same time, the low frequency band frequency measurement The response time is limited by the pulse pulse to be measured, and the frequency measurement response time is at least one pulse period to be measured. When the frequency to be measured is low, the data refresh may not be timely, affecting the dynamic control performance.

In order to solve the above problems, this application proposes a frequency measurement system and method based on self-adjustment and equal precision.

Contents of the invention

(1) Purpose of invention

In order to solve the technical problems existing in the background technology, the present invention proposes a frequency measurement system and method based on self-adjustment and equal accuracy. The present invention adopts two design methods of double-edge acquisition self-adjustment and acquisition window self-adjustment, while ensuring frequency measurement accuracy. At the same time, the frequency measurement response time is improved. Compared with the traditional frequency measurement method, the frequency measurement response time can be doubled at the fastest, meeting the higher control requirements for speed equipment in industrial sites and improving the dynamic control performance.

(2) Technical solutions

In order to solve the above problems, the present invention provides a frequency measurement system based on self-adjustment and equal precision, including:

CPLD and MCU;

CPLD includes a PLL phase-locked loop module, which generates the required clocks, including a reference clock and a multi-level filter clock;

Parallel port communication module, the parallel port communication module simulates the Flash read and write timing, simplifying the data read and write interaction between the MCU side and the CPLD, while ensuring the timeliness of data interaction;

Pulse filter module, the pulse filter module performs filtering operations according to the set filtering level to avoid pulse signal acquisition errors caused by high-frequency interference;

Counting acquisition module, the core part of the design scheme, automatically adjusts the acquisition of pulse edge signals and the length of the acquisition window according to the period of the pulse to be measured;

Pulse acquisition module;

MCU includes CPLD communication and data processing unit, PLC controller communication processing unit and auxiliary unit;

MCU is used for command control, data reading and writing, data processing and communication processing of CPLD; CPLD is used for receiving control operations of MCU and collection and filtering operations of external pulse signals to be measured;

Data interaction occurs between MCU and CPLD through a parallel communication interface.

Preferably, the auxiliary unit includes hardware fault reset and module real-time status display;

Hardware fault reset ensures that if the module crashes due to hardware interference or reasons, it will automatically reset and return to normal;

The real-time status display of the module facilitates users to observe the running status of the module in real time. Through the different display status of module operation, communication, error and other LEDs, the current status of the module or any faults can be confirmed.

A method based on self-adjusting equal-precision frequency measurement system, how to use the pulse filter module:

To filter out high-frequency interference signals, the pulse filter module uses a sampling frequency f higher than the pulse signal to be measured. After the pulse edge appears, it continuously collects level signals m times. When the pulse level signals for m times are consistent, , determine that the pulse signal is valid;

When the level signal duration t is less than (f*m), the pulse signal will be discarded and determined to be a high-frequency interference signal;

Pulse filtering principle: Assume the acquisition threshold m=4, the external pulse is at pulse 2, and during the entire high level duration, two consecutive samples are high level, and the third sampling level is low level, so pulse 2 will Signals considered to be interference will be filtered out.

Preferably, the pulse acquisition module is used as follows:

When the external pulse frequency is low, the window regulator uses one pulse period to be measured as the window time, and the upper edge and lower edge capturers participate in pulse edge capture at the same time. Within the window time of the upper edge capture and the window time of the lower edge capture, The reference clock pulse counter counts separately;

During the continuous input of pulses to be measured, the pulse acquisition module alternately transmits the pulse count values collected by the upper and lower edge pulse counters to the parallel port communication module, thereby increasing the refresh speed of the pulse count value to half of the pulse period to be measured at the fastest;

In the upper edge window time T ₀ =t ₂ -t ₀ , the reference pulse count value is N ₀ , in the lower edge window time T ₁ =t ₃ -t ₁ , the reference pulse count value is N ₁ , and the upper edge window time T ₂ = The reference pulse count value within the t ₄ -t ₂ window time is N ₂ , and so on, from t ₀ to t ₂ , the refresh time of N ₀ is t ₂ -t ₀ , from t ₂ to t ₃ , the refresh time of N ₁ is t ₃ -t ₂ , from t ₃ to t ₄ , the refresh time of N ₂ is t ₄ -t ₃ , therefore after the first acquisition window T ₀ , if the pulse to be measured is a pulse with a duty cycle of 50% For rectangular pulse signals, the data refresh time t = (t ₃ - t ₂ ) = (t ₄ - t ₃ ) is half of the pulse period to be measured, which is important for speed control equipment with a pulse frequency of about 50Hz. Meaning, it can ensure that a speed acquisition can be carried out in about 10ms and a closed-loop control can be completed. Compared with the traditional single-edge acquisition method, the data refresh cycle is doubled;

If the pulse duty cycle to be measured is not a rectangular pulse signal with a duty cycle of 50%, that is, (t ₃ -t ₂ ) ≠ (t ₄ -t ₃ ), the double-edge acquisition self-adjustment scheme is still applicable, and the data refresh time t is alternately equal to t _n -t _n-1 and t _n+1 -t _n (n>2), taking the power frequency of 50Hz as an example, the data refresh period t=10ms~20ms;

When the external pulse frequency is high, the window regulator will use m pulse periods to be measured as the window time. The selection of m will be dynamically self-adjusted according to the pulse frequency to be measured. At the same time, only the upper edge capturer participates in pulse edge capture, m=3, The fundamental frequency count value is N, the starting point of the window time is also the end point, that is, the upper edge signal of the pulse to be measured, and the length of the window time is an integer multiple of the period of the pulse signal to be measured, then the measurement error is ±1 of the fundamental frequency pulse signal, that is 1/25M, ensuring that the frequency measurement in the entire range is equal-precision frequency measurement. The refresh time t _n of N is 3 times the pulse period to be measured. At the same time, the value of m is automatically adjusted following the pulse signal to be measured. The selection of m is mainly based on the previous The refresh period t _n of the periodic fundamental frequency pulse count value N is selected, and within the guaranteed refresh period t _n =5ms-10ms, m*1/F≈t _n , F is the pulse frequency to be measured calculated from N, and m The value of is an integer. When the frequency of the pulse signal to be measured is high, the value of m increases. When the frequency of the pulse signal to be measured is low, the value of m decreases;

Through the above selection principle of m value, m is an integer, which ensures that the start and end of the window time are all triggered by the upper edge of the pulse to be measured, and the frequency measurement error is plus or minus one code value of the reference pulse, achieving equal-precision frequency measurement. At the same time, the refresh time t _n of the count value N is always maintained between 5ms and 10ms by adjusting m, which not only ensures accuracy but also ensures the real-time nature of data collection.

Preferably, how to use the CPLD communication and data processing unit:

The CPLD communication and data processing unit is used to read and write CPLD related registers, process the collected data from each channel, and convert the data collected by the CPLD into actual frequency values. The MCU reads and writes the CPLD through the FSMC interface, and operates the control and data registers of the CPLD;

When the external pulse frequency is low, the window regulator uses one pulse period to be measured as the window time, and the collected reference pulse count value is N, then the pulse frequency to be measured When the external pulse frequency is high, the window regulator will use m pulse periods to be measured as the window time, and the collected reference pulse count value is N, then the pulse frequency to be measured/>

The pulse frequency F to be measured calculated by the MCU will be passed to the PLC controller communication processing unit.

Preferably, the method of using the PLC controller communication processing unit is:

Receive control commands from the PLC CPU module and upload the collected frequency data of each channel to be measured to the CPU;

When the PLC CPU is powered on, it organizes configuration messages according to the user configuration information, and sends the configuration information to the MCU through the internal bus. The MCU parses the configuration information and writes the configuration to the CPLD to realize the initial configuration of the PLC to the CPLD. After the configuration is completed, the PLCCPU The data message obtains the frequency value of each channel and the actual status information of each channel, etc., and stores them locally for users to use.

Preferably, the MCU reads and writes the CPLD through the FSMC interface, and operates the control and data registers of the CPLD, including initial parameter settings, channel acquisition filter level settings, reference pulse data, and reading of pulse data to be measured.

The above technical solution of the present invention has the following beneficial technical effects:

The two design methods of double-edge acquisition self-adjustment and acquisition window self-adjustment are used to ensure the frequency measurement accuracy while improving the frequency measurement response time. Compared with the traditional frequency measurement method, the frequency measurement response time can be doubled at the fastest, meeting the requirements Industrial sites have higher control requirements for speed equipment, which improves dynamic control performance.

Description of the drawings

Figure 1 is a schematic structural diagram of a CPLD in the present invention.

Figure 2 is a schematic structural diagram of pulse filtering in the present invention.

Figure 3 is a schematic structural diagram of double-edge acquisition and self-adjustment in the present invention.

Figure 4 is a schematic structural diagram of the self-adjusting collection window in the present invention.

Figure 5 is a schematic structural diagram of the MCU in the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the specific embodiments and the accompanying drawings. It should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present invention.

As shown in Figures 1-5, the invention proposes a frequency measurement system based on self-adjustment and equal precision, including:

CPLD and MCU;

CPLD includes a PLL phase-locked loop module, which generates the required clocks, including a reference clock and a multi-level filter clock;

Parallel port communication module, the parallel port communication module simulates the Flash read and write timing, simplifying the data read and write interaction between the MCU side and the CPLD, while ensuring the timeliness of data interaction;

Pulse filter module, the pulse filter module performs filtering operations according to the set filtering level to avoid pulse signal acquisition errors caused by high-frequency interference;

Counting acquisition module, the core part of the design scheme, automatically adjusts the acquisition of pulse edge signals and the length of the acquisition window according to the period of the pulse to be measured;

Pulse acquisition module; the pulse acquisition module adopts the scheme design of acquisition window self-adjustment + double-edge acquisition self-adjustment, which not only ensures the frequency measurement accuracy, but also improves the frequency measurement response speed. The pulse acquisition module is composed of functional modules such as edge capturer, window regulator, and reference clock pulse counter. The edge capturer includes a rising edge capturer and a falling edge capturer;

MCU includes CPLD communication and data processing unit, PLC controller communication processing unit and auxiliary unit;

MCU is used for command control, data reading and writing, data processing and communication processing of CPLD; CPLD is used for receiving control operations of MCU and collection and filtering operations of external pulse signals to be measured;

Data interaction occurs between MCU and CPLD through a parallel communication interface.

The PLL phase-locked loop module inputs a 50M external crystal oscillator clock, and outputs a 25M reference clock, other multi-level filter clocks, etc. through the internal PLL. The 25M reference clock is used as the reference pulse counting signal. At the same time, the crystal oscillator uses a temperature-compensated crystal oscillator BT0507C/D, -40℃- The accuracy can reach ±1.5ppm at 85 degrees Celsius, which can effectively ensure the accuracy and consistency of the reference clock in different temperature environments. Other filter clocks provide different levels of filter drive signals. Depending on the software configuration, they can filter out different levels of high-frequency signal interference to ensure the accuracy of pulse collection.

The parallel port communication module simulates a storage area and uses the MCU's FSMC variable static storage controller to directly operate CPLD related registers, which can simplify MCU side software programming. At the same time, the parallel port communication method makes data interaction faster.

Preferably, the auxiliary unit includes hardware fault reset and module real-time status display;

Hardware fault reset ensures that if the module crashes due to hardware interference or reasons, it will automatically reset and return to normal;

The real-time status display of the module facilitates users to observe the running status of the module in real time. Through the different display status of module operation, communication, error and other LEDs, the current status of the module or any faults can be confirmed.

A method based on self-adjusting equal-precision frequency measurement system, how to use the pulse filter module:

To filter out high-frequency interference signals, the pulse filter module uses a sampling frequency f higher than the pulse signal to be measured. After the pulse edge appears, it continuously collects level signals m times. When the pulse level signals for m times are consistent, , determine that the pulse signal is valid;

When the level signal duration t is less than (f*m), the pulse signal will be discarded and determined to be a high-frequency interference signal;

Pulse filtering principle: Assume the acquisition threshold m=4, the external pulse is at pulse 2, and during the entire high level duration, two consecutive samples are high level, and the third sampling level is low level, so pulse 2 will Signals considered to be interference will be filtered out.

In an optional embodiment, the pulse acquisition module is used as follows:

When the external pulse frequency is low, the window regulator uses one pulse period to be measured as the window time, and the upper edge and lower edge capturers participate in pulse edge capture at the same time. Within the window time of the upper edge capture and the window time of the lower edge capture, The reference clock pulse counter counts separately;

During the continuous input of pulses to be measured, the pulse acquisition module alternately transmits the pulse count values collected by the upper and lower edge pulse counters to the parallel port communication module, thereby increasing the refresh speed of the pulse count value to half of the pulse period to be measured at the fastest;

As shown in Figure 3, the reference pulse count value is N ₀ within the upper edge window time T ₀ =t ₂ -t ₀ , and the reference pulse count value is N ₁ within the lower edge window time T ₁ =t ₃ -t ₁ . Window time T ₂ =t ₄ -t ₂ The reference pulse count value within the window time is N ₂ , and so on, from t ₀ to t ₂ , the refresh time of N ₀ is t ₂ -t ₀ , from t ₂ to t ₃ , The refresh time of N ₁ is t ₃ -t _2. From t ₃ to t ₄ , the refresh time of N ₂ is t ₄ -t _3. Therefore, after the first acquisition window T ₀ , if the pulse to be measured is duty For a rectangular pulse signal with a ratio of 50%, the data refresh time t = (t ₃ - t ₂ ) = (t ₄ - t ₃ ) is half of the pulse period to be measured. This is for a pulse frequency to be measured around the power frequency of 50Hz. The speed control equipment is of great significance, as it can ensure that a speed collection can be carried out in about 10ms and a closed-loop control can be completed. Compared with the traditional single-edge collection method, the data refresh cycle is doubled;

If the pulse duty cycle to be measured is not a rectangular pulse signal with a duty cycle of 50%, that is, (t ₃ -t ₂ ) ≠ (t ₄ -t ₃ ), the double-edge acquisition self-adjustment scheme is still applicable, and the data refresh time t is alternately equal to t _n -t _n-1 and t _n+1 -t _n (n>2), taking the power frequency of 50Hz as an example, the data refresh period t=10ms~20ms;

When the external pulse frequency is high, the window regulator will use m pulse periods to be measured as the window time. The selection of m will be dynamically self-adjusted according to the pulse frequency to be measured. At the same time, only the upper edge capturer participates in pulse edge capture, as shown in Figure 4 , m=3, the fundamental frequency count value is N, the starting point of the window time is also the end point, that is, the upper edge signal of the pulse to be measured, the length of the window time is an integer multiple of the period of the pulse signal to be measured, then the measurement error is the fundamental frequency pulse signal ±1, that is, 1/25M, to ensure that the frequency measurement in the entire range is the same precision frequency measurement. The refresh time _t of N is 3 times the pulse period to be measured. At the same time, the value of m is automatically adjusted following the pulse signal to be measured. The selection is mainly based on the refresh period t _n of the base frequency pulse count value N of the previous period. Within the guaranteed refresh period t _n =5ms-10ms, m*1/F≈t _n , F is the pulse frequency to be measured and is calculated by N It is concluded that, and the value of m is an integer, when the frequency of the pulse signal to be measured is high, the value of m increases, and when the frequency of the pulse signal to be measured is low, the value of m decreases;

Through the above selection principle of m value, m is an integer, which ensures that the start and end of the window time are all triggered by the upper edge of the pulse to be measured, and the frequency measurement error is plus or minus one code value of the reference pulse, achieving equal-precision frequency measurement. At the same time, the refresh time t _n of the count value N is always maintained between 5ms and 10ms by adjusting m, which not only ensures accuracy but also ensures the real-time nature of data collection.

In an optional embodiment, the CPLD communication and data processing unit is used as follows:

The CPLD communication and data processing unit is used to read and write CPLD related registers, process the collected data from each channel, and convert the data collected by the CPLD into actual frequency values. The MCU reads and writes the CPLD through the FSMC interface, and operates the control and data registers of the CPLD;

When the external pulse frequency is low, the window regulator uses one pulse period to be measured as the window time, and the collected reference pulse count value is N, then the pulse frequency to be measured When the external pulse frequency is high, the window regulator will use m pulse periods to be measured as the window time, and the collected reference pulse count value is N, then the pulse frequency to be measured/>

The pulse frequency F to be measured calculated by the MCU will be passed to the PLC controller communication processing unit.

Preferably, the method of using the PLC controller communication processing unit is:

Receive control commands from the PLC CPU module and upload the collected frequency data of each channel to be measured to the CPU;

When the PLC CPU is powered on, it organizes configuration messages according to the user configuration information, and sends the configuration information to the MCU through the internal bus. The MCU parses the configuration information and writes the configuration to the CPLD to realize the initial configuration of the PLC to the CPLD. After the configuration is completed, the PLCCPU The data message obtains the frequency value of each channel and the actual status information of each channel, etc., and stores them locally for users to use.

In an optional embodiment, the MCU reads and writes the CPLD through the FSMC interface, and operates the control and data registers of the CPLD, including initial parameter settings, channel acquisition filter level settings, reference pulse data, and reading of pulse data to be measured.

It should be understood that the above-described specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention shall be included in the protection scope of the present invention. Furthermore, it is intended that the appended claims of the present invention cover all changes and modifications that fall within the scope and boundaries of the appended claims, or equivalents of such scopes and boundaries.

Claims (7)

1. A self-adjusting equal precision frequency measurement system, comprising:

CPLD and MCU;

the CPLD comprises a PLL phase-locked loop module, and the PLL phase-locked loop module generates a required clock comprising a reference clock and a multi-level filtering clock;

the parallel port communication module simulates Flash read-write time sequence, simplifies data read-write interaction between the MCU side and the CPLD, and ensures timeliness of data interaction;

the pulse filtering module performs filtering operation according to the set filtering grade;

the counting and collecting module is a core part of the design scheme and is used for automatically adjusting the collecting of pulse edge signals and the length of a collecting window according to the period of the pulse to be detected;

a pulse acquisition module;

the MCU comprises a CPLD communication and data processing unit, a PLC controller communication processing unit and an auxiliary unit;

the MCU is used for command control, data reading and writing, data processing and communication processing of the CPLD; the CPLD is used for receiving control operation of the MCU and acquisition filtering operation of external pulse signals to be detected;

and the MCU and the CPLD perform data interaction through a parallel communication interface.

2. The self-adjusting equal-precision frequency measurement system according to claim 1, wherein the auxiliary unit comprises hardware fault reset and module real-time status display;

the hardware fault reset ensures that the module automatically resets and returns to normal due to the dead halt state caused by hardware interference or reasons;

the real-time state display of the module is convenient for a user to observe the running state of the module in real time, and confirms the current state of the module or what fault occurs through different display states of LEDs such as module running, communication, errors and the like.

3. The method based on the self-adjusting equal-precision frequency measurement system according to claim 1 or 2, wherein the pulse filtering module is used in the following way:

the method comprises the steps that a high-frequency interference signal is filtered, a pulse filtering module continuously collects m-time level signals after pulse jump edges occur by being higher than the sampling frequency f of a pulse signal to be detected, and the pulse signal is judged to be effective when the pulse level signals of the m-time continuous pulse level signals are consistent;

when the duration t of the level signal is less than (f x m), the pulse signal is discarded and is determined as a high-frequency interference signal;

pulse filtering principle: let m=4, the external pulse is at pulse 2, continuously sampled 2 times high for the entire high duration, and the 3 rd sampled level is low, so pulse 2 will be considered as the jammer signal will be filtered out.

4. A method based on a self-adjusting equal precision frequency measurement system as claimed in claim 3, wherein the pulse acquisition module is used as follows:

when the external pulse frequency is lower, the window regulator takes a pulse period to be detected as window time, the upper edge and the lower edge capturer simultaneously participate in pulse edge capturing, and the reference clock pulse counter respectively and independently counts in the window time captured by the upper edge and the window time captured by the lower edge;

in the continuous input process of the pulse to be detected, the pulse acquisition module alternately transmits the pulse count value acquired by the upper and lower edge pulse counter to the parallel port communication module, so that the refresh speed of the pulse count value is increased to half of the period of the pulse to be detected;

window time T at upper edge ₀ ＝t ₂ -t ₀ The internal reference pulse count value is N ₀ Lower edge window time T ₁ ＝t ₃ -t ₁ The internal reference pulse count value is N ₁ Upper edge window time T ₂ ＝t ₄ -t ₂ The reference pulse count value in the window time is N ₂ Analogize from t ₀ To t ₂ ，N ₀ Is t ₂ -t ₀ From t ₂ To t ₃ ，N ₁ Is t ₃ -t ₂ From t ₃ To t ₄ ，N ₂ Is t ₄ -t ₃ Thereby from the first acquisition window T ₀ Then, if the pulse to be tested is a rectangular pulse signal with a duty ratio of 50%, the data refresh time t= (t) ₃ -t ₂ )＝(t ₄ -t ₃ ) The pulse frequency to be measured is half of the pulse period to be measured, so that the pulse frequency to be measured has important significance for speed regulation equipment with the pulse frequency of about 50Hz, the speed can be collected once within about 10ms, the closed loop control once is completed, and compared with the traditional single-edge collection mode, the data refreshing period is doubled;

if the duty cycle of the pulse to be measured is not 50% of that of a rectangular pulse signal, i.e. (t ₃ -t ₂ )≠(t ₄ -t ₃ ) The double-edge acquisition self-adjustment scheme is still applicable, and the data refreshing time t is alternately equal to t _n -t _n-1 And t _n+1 -t _n (n > 2), taking power frequency 50Hz as an example, the data refreshing periodt＝10ms～20ms；

When the external pulse frequency is high, the window regulator takes M pulse periods to be measured as window time, the selection of M is dynamically self-regulated according to the pulse frequency to be measured, meanwhile, only the upper edge capturer participates in pulse edge capture, m=3, the fundamental frequency count value is N, the starting point of the window time is also an end point, namely an upper edge signal of the pulse to be measured, the window time length is an integer multiple of the pulse signal period to be measured, the measurement error is +/-1, namely 1/25M, the whole range frequency measurement is ensured to be equal-precision frequency measurement, and the refreshing time t of N is ensured _n The pulse period to be measured is 3 times, and the value of m is automatically adjusted along with the pulse signal to be measured, and the selection of m is mainly based on the refresh period t of the pulse count value N of the fundamental frequency of the previous period _n Selecting, ensuring a refresh period t _n In the range of =5 ms-10ms, m.times.1/F.apprxeq.t _n F is the pulse frequency to be measured and is calculated by N, the value of m is an integer, when the pulse frequency to be measured is high, the value of m is increased, and when the pulse frequency to be measured is low, the value of m is decreased;

through the selection principle of the m value, m is an integer, the starting and ending of the window time are ensured to take the upper edge of the pulse to be detected as a trigger signal, the frequency measurement error is the positive and negative code value of the reference pulse, the equal-precision frequency measurement is realized, and the refresh time t of the count value N is also ensured _n The m is regulated to be always kept between 5ms and 10ms, so that the accuracy is ensured, and the real-time performance of data acquisition is also ensured.

5. The method based on the self-adjusting equal-precision frequency measurement system as claimed in claim 4, wherein the CPLD communication and data processing unit uses the method:

the CPLD communication and data processing unit is used for reading and writing CPLD related registers, processing collected data of each channel, converting the data collected by the CPLD into actual frequency values, and the MCU reads and writes the CPLD through the FSMC interface to operate the registers such as control, data and the like of the CPLD;

when the external pulse frequency is lower, the window regulator takes a pulse period to be detected as the window time, and the acquired reference pulse count value is N, so that the pulse frequency to be detectedWhen the external pulse frequency is higher, the window regulator takes m pulse periods to be detected as window time, the acquired reference pulse count value is N, and the pulse frequency to be detected is +.>

And the pulse frequency F to be detected calculated by the MCU is transmitted to a communication processing unit of the PLC.

6. The method based on the self-adjusting equal-precision frequency measurement system according to claim 1, wherein the using method of the communication processing unit of the PLC is as follows:

receiving a control command of the PLC CPU module, and uploading collected frequency data to be tested of each channel to the CPU;

the PLC CPU is electrified to organize configuration messages according to user configuration information, the configuration information is issued to the MCU through the internal bus, the MCU analyzes the configuration information, the configuration is written into the CPLD, the initial configuration of the CPLD by the PLC is realized, after the configuration is completed, the PLC CPU obtains frequency values of all channels, actual state information of all channels and the like through the data messages, and the frequency values, the actual state information and the like of all channels are stored locally for users to use.

7. The method based on the self-adjusting equal-precision frequency measuring system according to claim 6, wherein the MCU reads and writes the CPLD through the FSMC interface, and operates registers such as control and data of the CPLD, including initial parameter setting, channel acquisition filtering level setting, reference pulse data and pulse data to be measured reading.