CN116776058A - Matrix transpose method - Google Patents

Abstract

The application relates to a matrix transposition method, which comprises the following steps: and circularly executing data read-write operation on the target matrix until the data in the target matrix are read out, and obtaining a transposed matrix of the target matrix. The data read-write operation comprises the following steps: sequentially controlling a plurality of shift registers in a chip to read preset quantity of data from a target matrix according to a clock sequence; the preset number is the same as the number of the plurality of shift registers, and stored data in each shift register moves one bit to high in each clock in the reading process; and under the condition that each shift register finishes one data reading, controlling the most significant stored data of each shift register to be written into the transpose matrix. By adopting the method, the calculation speed of matrix transposition of the chip can be improved, and the running speed of computer equipment carried by the chip is further improved.

Description

Matrix transpose method

Technical field

The present application relates to the field of information processing technology, and in particular to a matrix transposition method.

Background technique

Usually, when an artificial intelligence chip runs a neural network model, it needs to matrix the processed data and then perform operations on the matrix. Among them, the most basic operation in matrix operations includes the transpose of the matrix.

In related technology, when transposing a matrix, it is usually necessary to read the matrix data according to the address sequence, then address, and then convert the address to output the matrix transposed data, and repeat the above process to realize the transposition operation of the matrix.

However, the above method has low matrix transposition efficiency, which affects the calculation speed of the artificial intelligence chip, resulting in low computing efficiency of the artificial intelligence chip.

Contents of the invention

Based on this, it is necessary to address the above technical problems and provide a matrix transposition method that can increase the computing speed of the artificial intelligence chip and thereby improve the computing efficiency of the artificial intelligence chip.

In the first aspect, this application provides a matrix transposition method, which method includes:

Perform data read and write operations on the target matrix cyclically until the data in the target matrix is read, and the transpose matrix of the target matrix is obtained; the data read and write operations include:

According to the clock sequence, multiple shift registers in the chip are sequentially controlled to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and each clock is read during the reading process. The stored data in the shift register is moved to the high bit by one bit;

When each shift register has completed one data read, the highest-order stored data of each shift register is controlled to be written into the transposed matrix.

In one embodiment, multiple shift registers are sequentially controlled to read data from the target matrix according to clock sequence, including:

Get the reading order of multiple shift registers;

According to the clock sequence and the reading sequence of multiple shift registers, obtain the read address of each shift register in the target matrix;

According to the read address of each shift register in the target matrix, each shift register is controlled to read data from the target matrix.

In one embodiment, obtaining the reading sequence of multiple shift registers includes:

The lengths of multiple shift registers are determined according to the bandwidth of the memory cells in the chip; the lengths of each shift register are different;

Determine the order of the multiple shift registers in descending order of the length of each shift register.

In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence; wherein, the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth. .

In one embodiment, according to the clock sequence and the reading sequence of multiple shift registers, obtaining the read address of each shift register in the target matrix includes:

According to the clock sequence and the reading sequence of multiple shift registers, obtain the shift register corresponding to each clock; perform data reading of one shift register at each clock;

The address of the first row of data in the target matrix is used as the read address of the shift register corresponding to the first clock, and the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain each The read address of the shift register corresponding to clocks.

In one embodiment, controlling each shift register to read data from the target matrix according to the read address of each shift register in the target matrix includes:

For any shift register, determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix;

Control the shift register to read the target data.

In one embodiment, controlling the writing of the highest-order stored data of each shift register into the transposed matrix includes:

Obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposition vector;

Controls the writing of the transposed vector into the transposed matrix.

In one embodiment, controlling the writing of the transposed vector into the transposed matrix includes:

Get the writing address of the transposed vector in the transposed matrix;

According to the write address, the transposed vector is written into the transposed matrix.

In one embodiment, obtaining the writing address of the transposed vector in the transposed matrix includes:

Obtain the number of times each shift register has completed a data read during the cyclic execution of data read and write operations on the target matrix;

Determine the column address of the transposed vector in the transposed matrix according to the degree;

Use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

In one embodiment, the matrix transposition method further includes:

Determine the offset address transition step size of each clock according to the size of the target matrix and the bandwidth of the memory unit in the chip;

During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the clock's bias address jump step, and when the bias address jump is completed, the clock's bias address transition is The base address jumps by one address.

In a second aspect, this application also provides a matrix transposition device. The device includes: an acquisition module. The acquisition module includes a reading unit and a writing unit, wherein:

The acquisition module is used to perform data reading and writing operations on the target matrix cyclically until the data in the target matrix is read, and the transposed matrix of the target matrix is obtained;

The reading unit is used to sequentially control multiple shift registers in the chip to read a preset number of data from the target matrix in clock sequence; the preset number is the same as the number of multiple shift registers, and during the reading process The stored data in each shift register is shifted to the high bit by one bit at each clock;

The writing unit is used to control the highest bit stored data of each shift register to be written into the transposed matrix when each shift register has completed one data read.

In a third aspect, this application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, it implements any of the embodiments of the first aspect. Method steps.

In a fourth aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, any one of the embodiments of the first aspect is implemented. The steps in the method.

In a fifth aspect, the present application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method in any one of the embodiments of the first aspect.

The above matrix transposition method performs cyclic data reading and writing operations on the target matrix until the data in the target matrix is read, and the transposed matrix of the target matrix is obtained. Among them, the data read and write operations include: sequentially controlling multiple shift registers in the chip to read a preset number of data from the target matrix in accordance with the clock sequence; the preset number is the same as the number of multiple shift registers, and when reading During the fetching process, the stored data in each shift register moves one bit to the high bit at each clock; when each shift register completes a data read, control the writing of the highest bit stored data in each shift register. in the transposed matrix. Since this application controls the shift register to read a preset amount of data from the target matrix at each clock, it also controls the stored data in each shift register to move one bit to the high bit, and also controls each shift register. When all registers have completed one data read, the highest-order stored data of each shift register is controlled to be written into the transposition matrix. It is equivalent to the process of using shift registers to perform matrix transposition. Each shift register is reading, shifting and writing at the same time. This pipeline read and write mode avoids the idle state of each shift register. At the same time, it fits the characteristics of the chip's pipeline operation and saves time in matrix transposition operations. Moreover, in the matrix transposition method provided by this application, the number of data read by the shift register from the target matrix is the same as the number of multiple shift registers. Then, when each shift register completes one data read , the bandwidth of the corresponding shift register reading data under each clock is consistent with the bandwidth of the highest bit stored data output by each shift register under the clock. This data reading and writing method with consistent input and output bandwidth is convenient for the chip During the writing process of the transposed matrix, address jumps are performed regularly, thereby improving the writing efficiency of the matrix transposed matrix. In addition, usually, chips are installed and run in computer equipment, so it can be understood that when performing matrix transposition processing in the chip through the matrix transposition method provided by the embodiment of the present application, the transposition of these matrices is improved. Efficiency is equivalent to increasing the running speed of the chip, which is also equivalent to increasing the running speed of the computer equipment equipped with the chip.

Description of drawings

Figure 1 is an application environment diagram of the matrix transposition method in one embodiment;

Figure 2 is a schematic flow chart of a matrix transposition method in one embodiment;

Figure 3 is a schematic flowchart of the data reading steps in one embodiment;

Figure 4 is a schematic flow chart of the data reading steps in another embodiment;

Figure 5 is a schematic flowchart of the data reading steps in another embodiment;

Figure 6 is a schematic flow chart of the data reading steps in another embodiment;

Figure 7 is a schematic flowchart of the data writing steps in one embodiment;

Figure 8 is a schematic flowchart of the data writing steps in another embodiment;

Figure 9 is a schematic flow chart of the data writing steps in another embodiment;

Figure 10 is a schematic flow chart of address hopping in another embodiment;

Figure 11 is a schematic flowchart of a target matrix in an embodiment;

Figure 12 is a schematic flow chart of data reading and writing operations in one embodiment;

Figure 13 is a schematic flow chart of address hopping in another embodiment;

Figure 14 is a structural block diagram of a matrix transposition device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.

The matrix operation method provided by the embodiment of the present application can be applied on the chip. The chip can be an artificial intelligence chip such as a voice processing chip, a video processing chip, an image processing chip, etc. Its internal structure diagram can be shown in Figure 1. The chip includes a processor, memory, input/output interface (Input/Output, referred to as I/O) and communication interface. Among them, the processor, memory and input/output interface are connected through the system bus, and the communication interface is connected to the system bus through the input/output interface. Among them, the chip's processor is used to provide computing and control capabilities. The chip's memory includes non-volatile storage media and shift memory. The non-volatile storage medium stores operating systems, computer programs and databases. The shift memory provides an environment for the execution of operating systems and computer programs in non-volatile storage media. The chip's database is used to store thread stack processing data. The chip's input/output interface is used to exchange information between the processor and external devices. The communication interface of the chip is used to communicate with external terminals through network connections. The computer program, when executed by the processor, implements a matrix processing method. Those skilled in the art can understand that the structure shown in Figure 1 is only a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the chip on which the solution of the present application is applied. The specific chip may include more than The figures show more or fewer parts, or certain parts combined, or with different arrangements of parts.

With the rapid development of artificial intelligence technology, artificial intelligence chips are widely used in many fields. Due to the powerful data computing capabilities of artificial intelligence chips, the computing tasks performed by artificial intelligence chips are becoming more and more complex. When the artificial intelligence chip runs the neural network model, it needs to matrix the processed data and then perform operations on the matrix. Among them, the most basic operation in matrix operations includes the transpose of the matrix.

In artificial intelligence chips, the addressing mode of continuous module addresses is usually used, and a shift register is used to implement matrix transposition. In the related technology, a blocking matrix transposition method is used to control the shift register according to the bit width, perform data reading operations in the address sequence at the current clock, perform data output at the next clock conversion address of the current clock, and repeat the above cycle. process to achieve matrix transposition.

Taking the bandwidth of the shift register to read data as 8 bits and the size of matrix A as 8×16 as an example, the blocking matrix transposition method is explained: first, the shift register is controlled to read the 8-bit data of matrix A row by row. ; Then address the transposed matrix B (16×8) corresponding to matrix A, and write the read data into the transposed matrix B column by column until the read data is written; then control the shift The register reads the 8-bit data of the next row of matrix A, and repeats the above process until all the data of matrix A is written into the transposed matrix B, completing the transposition operation of matrix A.

However, in the above-mentioned blocking matrix transposition method, the reading and writing of the shift register cannot be performed at the same time. That is, the process of reading data and outputting data of the shift register need to be performed within two clocks, which is not compatible with the internal pipeline of the chip. Operating mode. Furthermore, when outputting data, the blocking matrix transposition method requires multiple addresses for the data output in columns. Such a cumbersome addressing process will cause the matrix transposition time to be too long.

Based on this, this application provides a non-blocking matrix transposition method. By setting the length of each shift register and the data reading and writing method, each shift register pipeline in the chip reads and outputs data, quickly realizing the matrix. Transpose, giving full play to the computing efficiency of the chip, thereby saving the power consumption of the chip. Next, the matrix transposition method is explained through an embodiment.

In one embodiment, as shown in Figure 2, a matrix transposition method is provided. This method is explained by taking the method applied to the chip in Figure 1 as an example, and includes the following steps:

Perform data reading and writing operations on the target matrix cyclically until the data in the target matrix is read, and obtain the transpose matrix of the target matrix.

Among them, the chip in the embodiment of the present application can be applied in multiple scenarios according to actual needs, such as voice processing, video processing, image processing, etc. Then, depending on the application scenario, the chip in the embodiment of the present application may be a voice processing chip, a video processing chip, an image processing chip, etc. Correspondingly, if the chip is a voice processing chip, the target matrix is a voice information matrix obtained based on voice information; if the chip is a video processing chip, the target matrix is a voice information matrix obtained based on video information; if the chip is an image processing chip, Then the target matrix is the image information matrix obtained based on the image information. The embodiments of this application do not limit the type of chip.

It should be noted that when the chip in the embodiment of the present application performs matrix transposition, it is different from the computer's random addressing method. Instead, it uses continuous module addresses to directly read the data in the matrix. By placing the data of adjacent address units in different memories, such as shift registers, and combining the parallel working mode of each shift register, the matrix transposition is performed.

In the case of obtaining the target matrix, perform a transpose operation on the target matrix, read and write data to the data in the target matrix at the same time, and read the data of the target matrix cyclically in combination with the chip's continuous module addressing method. Write. In this way, when the data in the target matrix is read, the transposed matrix of the target matrix is obtained.

Among them, data reading and writing operations include:

S201, in accordance with the clock sequence, sequentially control multiple shift registers in the chip to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and each clock during the reading process The stored data in each shift register is moved to the high bit by one bit.

In the embodiment of the present application, multiple shift registers in the chip are used as a group to perform the transpose operation of the target matrix, and one shift register is allowed to read data from the target matrix at each clock. According to the clock sequence, one of the multiple shift registers in the chip is sequentially controlled to read data from the target matrix, and the read data is stored in the lowest bit of the corresponding shift register.

Among them, the number of data read by different shift registers from the target matrix is the same, which is the number of multiple shift registers in the group. For example, the eight shift registers in the chip perform the matrix transpose operation of the target matrix. Then, the corresponding shift register reads 8 matrix elements from the target matrix at each clock.

At the same time, during the process of the shift register reading data, while the shift register under the current clock is reading data, if there are other shift registers that have read data before the current clock, that is, including stored data, then Controls the stored data in other shift registers to move one bit to the high bit.

Still taking the eight shift registers in the chip to perform the matrix transpose operation of the target matrix as an example, if none of the eight shift registers reads the data of the target matrix, the corresponding shift register reads data, the other seven shift registers do not store data, so there will be no data movement to high bits; if all eight shift registers have read the data of the target matrix, then the shift register corresponding to the current clock reads When fetching data, the other seven shift registers all include stored data, so under the current clock, the stored data in each shift register also moves one bit to the high bit.

Taking eight shift registers as a group, the process of reading data by the shift register is explained: under the first clock, the first register reads the eight-bit data of the target matrix and stores the read data into the first register Low bit; the second clock, the second register reads and stores the eight-bit data of the target matrix, and stores the read data to the low bit of the second register, while the stored data of the first register moves one bit to the high bit; the third clock, the third shift register reads the eight-bit data of the target matrix and stores the read data to the low bit of the third register. At the same time, the stored data of the first register continues to move to the high bit by one bit (the first register moves cumulatively to the high bit). two bits), the stored data in the second register moves to the high bit by one bit; at the fourth clock, the fourth shift register reads the eight-bit data of the target matrix and stores the read data to the low bit of the fourth register. The stored data in one register continues to move one bit to the high bit (the first register moves three bits to the high bit cumulatively), and the stored data in the second register continues to move one bit to the high bit (the second register moves three bits to the high bit cumulatively); By analogy, at the eighth clock, the eighth register reads the eight-bit data of the target matrix. The stored data in the first register moves cumulatively to the high bit by seven bits. The stored data in the second register moves cumulatively by six bits to the high bit. The third register The stored data in the register moves cumulatively by five bits to the high bit, the stored data in the fourth register moves cumulatively by four bits to the high bit, the stored data in the fifth register moves cumulatively by three bits towards the high bit, and the stored data in the sixth register moves cumulatively towards the high bit. Moving two bits, the stored data in the seventh register moves cumulatively to the high bit by one bit.

S202, when each shift register has completed one data read, control the highest bit stored data of each shift register to be written into the transposed matrix.

When each shift register completes a data read, that is, each shift register stores the data of the target matrix, and during the reading process, the stored data in each shift register is equal to each clock. When moving one bit to the high bit, the data stored in each shift register is moved to the highest bit. At this time, the highest-order stored data of each shift register is output and written into the transposition matrix.

In the embodiment of the present application, data reading and writing operations are performed cyclically on the target matrix until the data in the target matrix is read, and the transposed matrix of the target matrix is obtained. Among them, the data read and write operations include: sequentially controlling multiple shift registers in the chip to read a preset number of data from the target matrix in accordance with the clock sequence; the preset number is the same as the number of multiple shift registers, and when reading During the fetching process, the stored data in each shift register moves one bit to the high bit at each clock; when each shift register completes a data read, control the writing of the highest bit stored data in each shift register. in the transposed matrix. Since the embodiment of the present application controls the shift register to read a preset amount of data from the target matrix at each clock, it also controls the stored data in each shift register to move one bit to the high bit, and also controls the stored data in each shift register to move to the high bit. When all shift registers have completed one data read, the highest bit stored data of each shift register is controlled to be written into the transposed matrix. It is equivalent to the process of using shift registers to perform matrix transposition. Each shift register is reading, shifting and writing at the same time. This pipeline read and write mode avoids the idle state of each shift register. At the same time, it fits the characteristics of the chip's pipeline operation and saves time in matrix transposition operations. Moreover, in the matrix transposition method provided by the embodiment of the present application, the number of data read by the shift register from the target matrix is the same as the number of multiple shift registers. Then, each shift register completes one data read. In this case, the bandwidth of the corresponding shift register reading data under each clock is consistent with the bandwidth of the highest bit stored data output by each shift register under that clock. This data reading and writing method with consistent input and output bandwidth, This facilitates the chip to perform regular address transitions during the process of writing the transposed matrix, thereby improving the writing efficiency of the matrix transposed matrix. Normally, taking the voice processing chip, video processing chip, and image processing chip listed above as examples, the chips in any scenario are mounted and run on computer equipment, so it can be understood that the chips provided by the embodiments of this application When the matrix transposition method transposes any matrix of the voice information matrix, speech information matrix or image information matrix in the chip, improving the transposition efficiency of these matrices is equivalent to increasing the running speed of the chip, which is also equivalent to Improves the running speed of the computer equipment equipped with the chip.

When the chip performs the matrix transpose operation, it is necessary to read the data of the target matrix and write the data of the transposed matrix at the same time, thereby increasing the speed of the matrix transpose operation. Based on this, the following describes the data reading steps of the target matrix through an embodiment.

In one embodiment, as shown in Figure 3, multiple shift registers are sequentially controlled to read data from the target matrix according to clock sequence, including:

S301, obtain the reading order of multiple shift registers.

Combine multiple shift registers in the chip and sort the multiple shift registers according to the rule that one clock corresponds to one shift register for data reading to obtain the reading order of multiple shift registers in the chip.

S302: Obtain the reading address of each shift register in the target matrix according to the clock sequence and the reading sequence of the multiple shift registers.

Among them, the read address is the basis for each shift register to perform data reading. Each read address corresponds to a set of data. The shift register reads and stores the data corresponding to the read address according to the read address.

In the embodiment of the present application, according to the clock sequence and the reading sequence of multiple shift registers, different shift registers are controlled to read data in different rows of the target matrix, and one shift register is allowed to obtain the read address at each clock. to perform data reading tasks. When determining the shift register that performs data reading at each clock, determine the read address of the shift register in the target matrix at each clock based on the data of the target matrix that needs to be read at each clock.

S303: Control each shift register to read data from the target matrix according to the read address of each shift register in the target matrix.

After obtaining the read address of each shift register in the target matrix, control each shift register to read data from the target matrix according to the corresponding read address, and store the read data in a first-in, first-out manner. The lower bits of the shift register.

In the embodiment of this application, under each clock, the shift register is controlled to read data from the target matrix according to the read address, which is equivalent to giving full play to the addressing mode of the chip's continuous module address in the process of reading data. This feature enables the shift register to continuously read data and supports the chip pipeline operation mode.

In the process of data reading, multiple shift registers in the chip are involved. In the embodiment of the present application, one shift register is allowed to perform data reading under each clock, which means that multiple shift registers need to be sorted to determine the shift register that performs data reading under different clocks. Based on this, the steps for obtaining the reading order of multiple shift registers will be described below through an embodiment.

In one embodiment, as shown in Figure 4, obtaining the reading sequence of multiple shift registers includes:

S401: Determine the lengths of multiple shift registers according to the bandwidth of the memory unit in the chip; the lengths of each shift register are different. Among them, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence; the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

According to the bandwidth of the memory unit in the chip and the same principle of read and write bandwidth, set the number of multiple shift registers and determine the lengths of the multiple shift registers.

Setting the bandwidth of the memory unit in the chip to be the same as the number of multiple shift registers can ensure that under the same clock, multiple shift registers write data to the memory unit consistent with the bandwidth of the memory unit.

Multiple shift registers of different lengths are determined according to the bandwidth of the memory unit in the chip, and the minimum length is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth. It can be ensured that when multiple shift registers include stored data, each The shift register stores data in the highest bit, corresponding to a column of target data.

Optionally, if the bandwidth of the storage unit is 8B, eight shift registers are set, and the lengths of the shift registers vary from 9 to 16. Assume that each data is int8 data, that is, 1B. With this setting, when there is data in the highest bit of each shift register, one register reads data at each clock, that is, the bandwidth of reading data is 8B, and the highest bit data of 8 shift registers Write back at the same time, it is also 8B.

S402: Determine the order of multiple shift registers by ordering the lengths of each shift register from large to small.

Sort multiple shift registers in the chip according to the length of the shift registers from largest to smallest to obtain the reading order of multiple shift registers.

Optionally, if the bandwidth of the storage unit is 8B, eight shift registers are set, and the lengths of the shift registers vary from 9 to 16. Assume that each data is int8 data, that is, 1B. Then the order of the registers that perform data reading in sequence is: shift register with length 16, shift register with length 15, shift register with length 14, shift register with length 13, shift with length 12 Register, shift register of length 11, shift register of length 10, shift register of length 9.

In the embodiment of the present application, according to the bandwidth of the storage unit, the number of shift registers is set to be the same as the bandwidth, which is equivalent to having multiple shift registers write data to the storage unit and the storage unit during the data writing process. The bandwidth is the same. Moreover, set the minimum length of the shift register to the bandwidth plus 1, and set the maximum length of the shift register to twice the bandwidth, which is equivalent to reading the data of the target matrix in a shift register during the data reading process. At the same time, it provides a preset storage space for other shift registers to shift. Therefore, the embodiment of the present application sets the number of shift registers and the length of the shift register in a manner that ensures that the bandwidth of reading data and the bandwidth of writing data are the same during the data reading and writing process, and can fully utilize the computing efficiency of the chip. .

After obtaining the reading sequence of multiple shift registers in the chip, assign a read address to each shift register for data reading. Below, through an embodiment, the steps for obtaining the read address of each shift register are explained:

In one embodiment, as shown in Figure 5, according to the clock sequence and the reading sequence of multiple shift registers, the read address of each shift register in the target matrix is obtained, including:

S501: Obtain the shift register corresponding to each clock according to the clock sequence and the reading sequence of multiple shift registers; perform data reading of one shift register at each clock.

According to the rule that each clock performs data reading of one shift register, match the clock sequence with the reading sequence of multiple shift registers to obtain the shift register that performs data reading for each clock.

Still taking the storage unit bandwidth of 8B as an example, set up 8 different shift registers with a length ranging from 8 to 16, and the reading order of multiple shift registers is from large to small length of each shift register. Take the sequence as an example. Then, the length of the shift register corresponding to the first clock is 16, the length of the shift register corresponding to the second clock is 15, the length of the shift register corresponding to the third clock is 14, and the length of the shift register corresponding to the fourth clock The length of the shift register is 13, the length of the shift register corresponding to the fifth clock is 12, the length of the shift register corresponding to the sixth clock is 11, and the length of the shift register corresponding to the seventh clock is 10 , the length of the shift register corresponding to the eighth clock is 9, and the length of the shift register corresponding to the ninth clock is 16.

S502, use the address of the first row of data in the target matrix as the read address of the shift register corresponding to the first clock, and the address of the second row as the read address of the shift register corresponding to the second clock, and so on. Get the read address of the shift register corresponding to each clock.

Since each clock corresponds to a shift register for data reading, and the data read by different shift registers is the data of different rows of the target matrix, then the row address of the data in the target matrix is the read address of the shift register. Match the row order in the target matrix with the clock order. Correspondingly, use the row address in the target matrix as the read address of the shift register under the corresponding clock.

Optionally, at the first clock, use the first row address of the data in the target matrix as the read address of the shift register under the first clock; at the second clock, use the second row address of the data in the target matrix. As the read address of the shift register under the second clock; at the third clock, the third row address of the data in the target matrix is used as the read address of the shift register under the third clock; and so on, we get each The read address of the shift register corresponding to clocks.

In the embodiment of the present application, on the basis of determining the shift register corresponding to each clock, the read address of the shift register corresponding to each clock is determined according to the row order of the target matrix. Since the row order is continuous, the clock order is also continuous. , then the read addresses of each shift register determined in row order are also consecutive. This way of determining the read address cleverly makes use of the chip's addressing method of continuous module addresses, maximizing the chip's computing efficiency.

The shift register reads one row of data in the target matrix. However, when the read bandwidth of the shift register is smaller than the elements of one row in the target matrix, the shift register needs to read the data multiple times to obtain a complete row of data in the target matrix. . Based on this, the steps for the shift register to read the data in the target matrix according to the read address will be described below through an embodiment.

In one embodiment, as shown in Figure 6, controlling each shift register to read data from the target matrix according to the read address of each shift register in the target matrix includes:

S601. For any shift register, determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix.

It should be noted that the data bandwidth corresponding to a read address is consistent with the read bandwidth of the shift register, which means that a read address corresponds to multiple data in one row of the target matrix. For example, if the read bandwidth is 8B and one data in the target matrix is 1B, then the data corresponding to a read address is 8 consecutive data in a row in the target matrix.

For any shift register, according to the read address of the shift register in the target matrix, a set of data in the target matrix corresponding to the read address is determined as the target data read by the shift register.

S602, control the shift register to read target data.

When the target data read by the shift register is determined, the read address in the target matrix is used as the read address of the target data, and the shift register is controlled to read the target data from the target matrix according to the read address of the target matrix.

In the embodiment of the present application, the target data corresponding to the shift register is determined according to the read address of the shift register in the target matrix, and the shift register is controlled to read the target data from the target matrix according to the read address. The design logic is clear, and Easy to implement.

When the chip performs the matrix transpose operation, it is necessary to write data to the transposed matrix while reading data from the target matrix. The foregoing embodiment describes the data reading steps of the target matrix. Based on this, the following describes the data writing steps of the transposed matrix through an embodiment.

In one embodiment, as shown in Figure 7, controlling the writing of the highest-order stored data of each shift register into the transpose matrix includes:

S701: Obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposition vector.

When each shift register has completed one data read, the highest bit of each shift register stores the data of the target matrix, and the highest bit of data of each shift register respectively corresponds to the data of the same column of the target matrix, The highest-order stored data of each shift register is combined in the form of rows, and the combination is used as the transposition vector of the output of each shift register of the current clock.

S702, control the transposition vector to be written into the transposition matrix.

Since the transposed vector is stored in the form of columns in the target matrix, to transpose the target matrix, the transposed vector needs to be written into the transposed matrix in the form of rows.

In the embodiment of the present application, on the basis of obtaining the highest-order stored data of each shift register, the highest-order stored data of each shift register is combined to generate a transposition vector, and the transposed vector is controlled to be stored in the form of rows in the transposed vector. In the matrix, the transpose operation of the target matrix is implemented.

Similar to the data reading process of the target matrix, the read address needs to be obtained. In the data writing process of the transposed matrix, the data writing of the transposed matrix also needs to be based on the writing address. Based on this, the data writing steps of the transposed matrix will be described below through an embodiment.

In one embodiment, as shown in Figure 8, controlling the transposition vector to be written into the transposition matrix includes:

S801, obtain the writing address of the transposed vector in the transposed matrix.

Among them, the write address is the basis for writing the data stored in the highest bit of each shift register into the transpose matrix. Each write address corresponds to multiple consecutive data in one row in the transpose matrix. Optionally, determine the writing address of the transposed vector in the transposed matrix according to the position of the transposed vector in the transposed matrix.

S802: Control the transposition vector to be written into the transposition matrix according to the writing address.

Control multiple shift registers to write the transposition vector into the transposition matrix according to the writing address.

In the embodiment of the present application, according to the position of the transposed vector in the transposed matrix, the writing address of the transposed vector in the transposed matrix is obtained, and according to the written address, the highest bit stored data in each shift register is written. Enter the transpose matrix to realize the transposition of the target matrix.

Below, through an embodiment, an achievable way of "obtaining the writing address of the transposed vector in the transposed matrix" in the previous embodiment is explained. As shown in Figure 9, obtaining the transposed vector in the transposed matrix Write addresses in the matrix, including:

S901: Obtain the number of times each shift register currently completes one data read during the cyclic execution of data read and write operations on the target matrix.

During the cyclic execution of data read and write operations on the target matrix, monitor the number of times each shift register has completed a data read, determine the row position of the transposed vector in the transposed matrix based on the number of times, and store the transposed vector in the transposed matrix. The row address in the transposed matrix is used as the writing address of the transposed vector in the transposed matrix.

S902: Determine the row address of the transposed vector in the transposed matrix according to the number of times.

For example, the current shift register has completed one data read, and the transposed vector is the first column data of the target matrix, then the first row address in the transposed matrix is the row address of the transposed vector in the transposed matrix.

S903: Use the row address of the transposed vector in the transposed matrix as the writing address of the transposed vector in the transposed matrix.

In the embodiment of the present application, the row address of the transposed vector in the transposed matrix is determined based on the number of times the shift register completes one data read, and then the writing address of the transposed vector in the transposed matrix is determined. Since the chip , both the target matrix and the transposed matrix are stored in rows. Therefore, the writing address confirmation method provided by this application only requires one addressing to write the transposed vector into the transposed matrix. Improved the computing efficiency of the chip.

During the matrix transposition process, the data read and write operations are based on the read address and write address, read the data of the target matrix, and write the data of the target matrix into the transposed matrix based on the transposed write address. middle. In the embodiment of the present application, the read address and write address obtained by the chip adopt the method of base address plus offset address, and perform transpose operation on the target matrix through regular address jumps. Based on this, the address generation method in the matrix transposition method is explained below through an embodiment.

In one embodiment, as shown in Figure 10, the matrix transposition method further includes:

S1001. Determine the offset address transition step size of each clock according to the size of the target matrix and the bandwidth of the memory unit in the chip.

During the data reading process, the read address includes the base address and the offset address, obtain the width of the target matrix and the bandwidth of the memory unit in the chip, and use the ratio of the width of the target matrix to the bandwidth of the memory unit in the chip as each clock Read the transition step size of the partial address in the read address.

During the data writing process, the read address includes the base address and the offset address, obtain the height of the target matrix and the bandwidth of the memory unit in the chip, and use the ratio of the height of the target matrix to the bandwidth of the memory unit in the chip as each clock Read the transition step size of the partial address in the read address.

For example, when the size of the target matrix is H (height) × W (width) and the storage unit is stored in rows, if the bandwidth of the storage unit is 8B, that is, every 8B of the storage unit is a continuous address unit, then The offset address jump step size of the read address of each clock is ceil(W/8), and the offset address jump step size of the write address of each clock is ceil(H/8). Among them, ceil() represents the operation of rounding up.

S1002, during the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step of the clock, and when the bias address jump is completed, the The base address of the clock jumps one address.

During the data read operation, for any clock, according to the transition step size of the partial address in the read address, the bias address of the read address performs a bias address jump in the row direction of the target matrix, and the bias address jumps at the When completed, the base address of the read address jumps by one address.

During the data writing operation, for any clock, according to the transition step size of the offset address in the write address, the offset address of the write address performs offset address transitions in the row direction of the transposed matrix, and jumps at the offset address. When the change is completed, the base address of the write address jumps by one address.

In the embodiment of the present application, during the cyclic execution of data read and write operations on the target matrix, both the read address and the write address are continuous addresses, which facilitates each clock to implement address jumps according to the address storage rules.

In one embodiment, the target matrix shown in Figure 11 is taken as an example to illustrate the matrix transposition method. The target matrix size (W×H) shown in Figure 11 is 64×16. Each data size of the target matrix is is 1B. If the bandwidth of the storage unit is 8B, 8 shift registers are set, and the lengths of the 8 shift registers decrease in sequence from 16 to 9, as shown in Figure 12. Figure 12 is a schematic diagram of the reading and writing process of eight shift registers transposing the target matrix.

It can be seen from Figure 12 that at the first clock, the eight data in the first row of the target matrix are read from the first register and stored in the lower eight bits of the first register; at the second clock, the eight data in the first row of the target matrix are read from the second register Take the eight data in the second row of the target matrix and store them in the lower eight bits of the second register, and move the stored data in the first register one bit to the left; at the third clock, read the target from the third register The eight data in the third row of the matrix are stored in the lower eight bits of the third register, and the stored data in the first register continues to move one bit to the left (the stored data in the first register moves cumulatively by two bits), The stored data in the second register is shifted one bit to the left; and by analogy, at the eighth clock, the eight data in the eighth row in the target matrix are read from the eighth register and stored in the lower eight bits of the eighth register. And the stored data in the first register moves to the high bit cumulatively by seven bits, the stored data in the second register moves to the high bit in total by six bits, the stored data in the third register moves to the high bit in total by five bits, the stored data in the fourth register moves to the high bit in total The accumulated data of the fifth register moves to the high order by four places, the stored data of the fifth register moves to the high order of three places, the stored data of the sixth register moves to the high order of two places, and the stored data of the seventh register moves to the high order of one place. The length of the first register to the length of the eighth register decreases in sequence from 16 to 9. Then at the ninth clock, the first register reads eight of the data from the ninth column of the first row to the fifteenth column of the target matrix. data, and the stored data in all registers are moved to the highest bit, and the highest bit data of each shift register is output, that is, the eight data in the first column of the target matrix. At the tenth clock, it is read by the second register Eight data from the ninth column to the fifteenth column of the second row in the target matrix, and the stored data of all registers are moved to the highest bit, and the highest bit data of each shift register is output, which is the target matrix. Eight data in two columns. In other words, after eight clocks, the data of the target matrix can be read and written at the same time, realizing pipelined (non-blocking) data read and write operations. Moreover, the bandwidth for each data read and the bandwidth for data write are both 8B, achieving the same read and write addresses.

Corresponding to the read and write operations shown in Figure 12, this application also designs an address generation system, using the base address + offset address method to provide a basis for data reading. As shown in Figure 13, Figure 13 is a schematic diagram of the transition mode of the data writing address after the eighth clock. At the ninth clock, the highest-order stored data of each shift register is written into the transpose matrix in the form of rows. When the offset address of the written address completes the transition in the row direction of the transposed matrix, the offset address of the written address is The base address jumps by one address.

In the embodiment of the present application, the transposition operation of the target matrix is explained with reference to Figures 11 to 13. According to the above operation process, the advantages of the technical solution provided by the embodiment of the present application include the following three aspects:

(1) When the data reading bandwidth remains unchanged, when using a shift register to realize matrix transposition, pipeline reading and output conform to the nature of the chip's pipeline operation, and the matrix transposition can be realized more quickly, giving full play to The chip’s computing efficiency and effectiveness while saving power.

(2) In terms of address addressing, the input and output bandwidth of the matrix transposition method provided by the embodiment of the present application matches, and the output data addresses are connected, which facilitates the implementation of address hopping according to the address storage rules.

(3) The embodiment of the present application can quickly realize the transposition operation of the matrix, providing a basis for subsequent chips to implement other matrix operations (such as matrix multiplication).

It should be understood that although the steps in the flowcharts involved in the above-mentioned embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above embodiments may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be completed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

Based on the same inventive concept, embodiments of the present application also provide a matrix transposition device for implementing the above-mentioned matrix transposition method. The solution to the problem provided by this device is similar to the solution described in the above method. Therefore, for the specific limitations in one or more embodiments of the matrix transposition device provided below, please refer to the above description of the matrix transposition method. Limitations will not be repeated here.

In one embodiment, as shown in Figure 14, a matrix transposition device 1400 is provided, including: an acquisition module 1401. The acquisition module 1401 includes a reading unit and a writing unit, wherein:

The acquisition module 1401 is used to cyclically perform data reading and writing operations on the target matrix until the data in the target matrix is read, and obtain the transposed matrix of the target matrix;

A reading unit, configured to sequentially control multiple shift registers in the chip to read a preset number of data from the target matrix in a clock sequence; the preset number is the same as the number of the multiple shift registers. , and during the reading process, the stored data in each shift register moves to the high bit by one bit at each clock;

A writing unit is configured to control the highest bit stored data of each shift register to be written into the transposition matrix when each shift register has completed one data read.

In one embodiment, the read unit includes: a sequential read sub-unit, an address acquisition sub-unit and a data read sub-unit, wherein:

Sequential reading subunit, used to obtain the reading sequence of multiple shift registers;

The address acquisition subunit is used to obtain the read address of each shift register in the target matrix according to the clock sequence and the reading sequence of multiple shift registers;

The data reading subunit is used to control each shift register to read data from the target matrix according to the read address of each shift register in the target matrix.

In one embodiment, sequential reading of subunits is also used to determine the length of multiple shift registers based on the bandwidth of the memory unit in the chip; the lengths of each shift register are different; the length of each shift register is changed from the largest to the largest. Ordering of multiple shift registers is determined into small order.

In one embodiment, the number of shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence. Among them, the minimum length in each shift register is equal to the bandwidth plus 1, and the maximum length is equal to twice the bandwidth.

In one embodiment, the address acquisition subunit is also used to acquire the shift register corresponding to each clock according to the clock sequence and the reading sequence of multiple shift registers; perform data reading of one shift register at each clock. Take; use the address of the first row of data in the target matrix as the read address of the shift register corresponding to the first clock, and the address of the second row as the read address of the shift register corresponding to the second clock, and so on, Get the read address of the shift register corresponding to each clock.

In one embodiment, the data reading subunit is also used to determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix for any shift register; control the shift register to read the target data.

In one embodiment, the writing unit includes: a vector acquisition subunit and a vector writing subunit, where:

The vector acquisition subunit is used to obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposed vector;

The vector writing subunit is used to control the writing of transposed vectors into the transposed matrix.

In one embodiment, the vector writing subunit is also used to obtain the writing address of the transposed vector in the transposed matrix; based on the writing address, the transposed vector is controlled to be written into the transposed matrix.

In one embodiment, the vector writing subunit is also used to obtain the number of times each shift register currently completes a data read during the cyclic execution of data read and write operations on the target matrix; determine the position of the transposed vector based on the number of times. Transpose the column address in the matrix; use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

In one embodiment, the matrix transposition device 1400 also includes a determination module and a hopping module, wherein:

A determination module used to determine the offset address jump step size of each clock according to the size of the target matrix and the bandwidth of the memory unit in the chip;

The hopping module is used to perform partial address hopping in the row direction according to the bias address hopping step of the clock for any clock during the cyclic execution of data read and write operations on the target matrix, and after the partial address hopping is completed case, the base address of the clock jumps one address.

Each module in the above-mentioned matrix transposition device can be implemented in whole or in part by software, hardware and combinations thereof. Each of the above modules may be embedded in or independent of the processor of the computer device in the form of hardware, or may be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, it implements the following steps:

Perform data read and write operations on the target matrix cyclically until the data in the target matrix is read, and the transpose matrix of the target matrix is obtained; the data read and write operations include:

According to the clock sequence, multiple shift registers in the chip are sequentially controlled to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and each clock is read during the reading process. The stored data in the shift register is moved to the high bit by one bit;

When each shift register has completed one data read, the highest-order stored data of each shift register is controlled to be written into the transposed matrix.

In one embodiment, the processor also implements the following steps when executing the computer program:

Get the reading order of multiple shift registers;

According to the clock sequence and the reading sequence of multiple shift registers, obtain the read address of each shift register in the target matrix;

According to the read address of each shift register in the target matrix, each shift register is controlled to read data from the target matrix.

In one embodiment, the processor also implements the following steps when executing the computer program:

The lengths of multiple shift registers are determined according to the bandwidth of the memory cells in the chip; the lengths of each shift register are different;

Determine the order of the multiple shift registers in descending order of the length of each shift register.

In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence; wherein, the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

In one embodiment, the processor also implements the following steps when executing the computer program:

According to the clock sequence and the reading sequence of multiple shift registers, obtain the shift register corresponding to each clock; perform data reading of one shift register at each clock;

The address of the first row of data in the target matrix is used as the read address of the shift register corresponding to the first clock, and the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain each The read address of the shift register corresponding to clocks.

In one embodiment, the processor also implements the following steps when executing the computer program:

For any shift register, determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix;

Control the shift register to read the target data.

In one embodiment, the processor also implements the following steps when executing the computer program:

Obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposition vector;

Controls the writing of the transposed vector into the transposed matrix.

In one embodiment, the processor also implements the following steps when executing the computer program:

Get the writing address of the transposed vector in the transposed matrix;

According to the write address, the transposed vector is written into the transposed matrix.

In one embodiment, the processor also implements the following steps when executing the computer program:

Obtain the number of times each shift register has completed a data read during the cyclic execution of data read and write operations on the target matrix;

Determine the column address of the transposed vector in the transposed matrix according to the degree;

Use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

In one embodiment, the processor also implements the following steps when executing the computer program:

Determine the offset address transition step size of each clock according to the width of the target matrix and the size of the memory unit in the chip;

During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the clock's bias address jump step, and when the bias address jump is completed, the clock's bias address transition is The base address jumps by one address.

In one embodiment, a computer-readable storage medium is provided with a computer program stored thereon. When the computer program is executed by a processor, the following steps are implemented:

Perform data read and write operations on the target matrix cyclically until the data in the target matrix is read, and the transpose matrix of the target matrix is obtained; the data read and write operations include:

According to the clock sequence, multiple shift registers in the chip are sequentially controlled to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and each clock is read during the reading process. The stored data in the shift register is moved to the high bit by one bit;

When each shift register has completed one data read, the highest-order stored data of each shift register is controlled to be written into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Get the reading order of multiple shift registers;

According to the clock sequence and the reading sequence of multiple shift registers, obtain the read address of each shift register in the target matrix;

According to the read address of each shift register in the target matrix, each shift register is controlled to read data from the target matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

The lengths of multiple shift registers are determined according to the bandwidth of the memory cells in the chip; the lengths of each shift register are different;

Determine the order of the multiple shift registers in descending order of the length of each shift register.

In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence; wherein, the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

According to the clock sequence and the reading sequence of multiple shift registers, obtain the shift register corresponding to each clock; perform data reading of one shift register at each clock;

The address of the first row of data in the target matrix is used as the read address of the shift register corresponding to the first clock, and the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain each The read address of the shift register corresponding to clocks.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

For any shift register, determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix;

Control the shift register to read the target data.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposition vector;

Controls the writing of the transposed vector into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Get the writing address of the transposed vector in the transposed matrix;

According to the write address, the transposed vector is written into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Obtain the number of times each shift register has completed a data read during the cyclic execution of data read and write operations on the target matrix;

Determine the column address of the transposed vector in the transposed matrix according to the degree;

Use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Determine the offset address transition step size of each clock according to the size of the target matrix and the bandwidth of the memory unit in the chip;

During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the clock's bias address jump step, and when the bias address jump is completed, the clock's bias address transition is The base address jumps by one address.

In one embodiment, a computer program product is provided, comprising a computer program that when executed by a processor implements the following steps:

Perform data read and write operations on the target matrix cyclically until the data in the target matrix is read, and the transpose matrix of the target matrix is obtained; the data read and write operations include:

According to the clock sequence, multiple shift registers in the chip are sequentially controlled to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and each clock is read during the reading process. The stored data in the shift register is moved to the high bit by one bit;

When each shift register has completed one data read, the highest-order stored data of each shift register is controlled to be written into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Get the reading order of multiple shift registers;

According to the clock sequence and the reading sequence of multiple shift registers, obtain the read address of each shift register in the target matrix;

According to the read address of each shift register in the target matrix, each shift register is controlled to read data from the target matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

The lengths of multiple shift registers are determined according to the bandwidth of the memory cells in the chip; the lengths of each shift register are different;

Determine the order of the multiple shift registers in descending order of the length of each shift register.

In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases in sequence; wherein, the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

According to the clock sequence and the reading sequence of multiple shift registers, obtain the shift register corresponding to each clock; perform data reading of one shift register at each clock;

The address of the first row of data in the target matrix is used as the read address of the shift register corresponding to the first clock, and the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain each The read address of the shift register corresponding to clocks.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

For any shift register, determine the target data corresponding to the shift register according to the read address of the shift register in the target matrix;

Control the shift register to read the target data.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Obtain the highest-order stored data of each shift register, and combine the highest-order stored data of each shift register to obtain the transposition vector;

Controls the writing of the transposed vector into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Get the writing address of the transposed vector in the transposed matrix;

According to the write address, the transposed vector is written into the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Obtain the number of times each shift register has completed a data read during the cyclic execution of data read and write operations on the target matrix;

Determine the column address of the transposed vector in the transposed matrix according to the degree;

Use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

In one embodiment, the computer program, when executed by the processor, also implements the following steps:

Determine the offset address transition step size of each clock according to the size of the target matrix and the bandwidth of the memory unit in the chip;

During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the clock's bias address jump step, and when the bias address jump is completed, the clock's bias address transition is The base address jumps by one address.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage. In the media, when executed, the computer program may include the processes of the above method embodiments. Any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetic variable memory (Magnetoresistive Random) Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene memory, etc. Volatile memory may include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM). The databases involved in the various embodiments provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include blockchain-based distributed databases, etc., but are not limited thereto. The processors involved in the various embodiments provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to this.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present application, and their descriptions are relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims (10)

1. A matrix transposition method, the method comprising:

circularly executing data read-write operation on a target matrix until the data in the target matrix are read out, and obtaining a transposed matrix of the target matrix; the data read-write operation comprises the following steps:

sequentially controlling a plurality of shift registers in a chip to read preset quantity of data from the target matrix according to a clock sequence; the preset number is the same as the number of the plurality of shift registers, and stored data in each shift register moves one bit to the high position under each clock in the reading process;

And under the condition that each shift register finishes one data reading, controlling the most significant stored data of each shift register to be written into the transpose matrix.

2. The method of claim 1, wherein sequentially controlling the plurality of shift registers to read data from the target matrix in clock order comprises:

acquiring the reading sequence of the plurality of shift registers;

acquiring a reading address of each shift register in the target matrix according to the clock sequence and the reading sequence of the shift registers;

and controlling each shift register to read data from the target matrix according to the read address of each shift register in the target matrix.

3. The method of claim 2, wherein the obtaining the read order of the plurality of shift registers comprises:

determining the lengths of the plurality of shift registers according to the bandwidths of the storage units in the chip; the lengths of the shift registers are different;

the order of the lengths of the shift registers from large to small is determined as the order of the plurality of shift registers.

4. A method according to claim 3, wherein the number of shift registers is the same as the bandwidth, and the length of each shift register is successively decreased; wherein the minimum length in each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

5. The method according to any one of claims 2-4, wherein said obtaining a read address of each shift register in the target matrix in the clock order and the read order of the plurality of shift registers comprises:

acquiring a shift register corresponding to each clock according to the clock sequence and the reading sequence of the shift registers; performing data reading of a shift register under each clock;

and taking the first row address of the data in the target matrix as the read address of the shift register corresponding to the first clock, taking the second row address as the read address of the shift register corresponding to the second clock, and the like to obtain the read address of the shift register corresponding to each clock.

6. The method of any one of claims 2-4, wherein controlling each shift register to read data from the target matrix according to the read address of each shift register in the target matrix comprises:

for any shift register, determining target data corresponding to the shift register according to a reading address of the shift register in the target matrix;

And controlling the shift register to read the target data.

7. The method of any of claims 1-4, wherein controlling the writing of the most significant stored data of each of the shift registers into the transpose matrix comprises:

acquiring the highest-order storage data of each shift register, and combining the highest-order storage data of each shift register to acquire a transpose vector;

and controlling the transposed vector to be written into the transposed matrix.

8. The method of claim 7, wherein the controlling the transpose vector to be written into the transpose matrix comprises:

acquiring a writing address of the transposed vector in the transposed matrix;

and controlling the transpose vector to be written into the transpose matrix according to the writing address.

9. The method of claim 8, wherein the obtaining the write address of the transpose vector in the transpose matrix comprises:

acquiring the number of times that each shift register finishes one-time data reading currently in the process of circularly executing data reading and writing operation on the target matrix;

determining a column address of the transpose vector in the transpose matrix according to the times;

And taking the column address of the transposed vector in the transposed matrix as the writing address of the transposed vector in the transposed matrix.

10. The method according to any one of claims 1-4, further comprising:

determining the offset address jump step length of each clock according to the size of the target matrix and the bandwidth of a storage unit in the chip;

and in the process of circularly executing data read-write operation on the target matrix, performing offset address hopping on any clock according to the offset address hopping step length of the clock in the row direction, and hopping the base address of the clock by one address under the condition that the offset address hopping is completed.