CN116745846A

CN116745846A - An input and output module and memory

Info

Publication number: CN116745846A
Application number: CN202180087464.9A
Authority: CN
Inventors: 潘越; 周浩阳; 布明恩
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2023-09-12
Also published as: WO2022236467A1

Abstract

An input and output module and a memory are used to reduce data writing time and improve data writing efficiency of the memory. The input-output module is coupled with the storage array, and the input-output module includes a drive circuit and a write auxiliary circuit. Among them, the driving circuit is used to generate a driving signal according to the writing signal and the data to be written, and the driving signal is used to drive the storage array to write the data to be written; the writing auxiliary circuit is coupled with the output end of the driving circuit and is used to write in the storage array. When the data to be written is input, the write auxiliary current is output; when the write current flowing through the storage array reaches the first threshold, the write auxiliary current is stopped.

Description

Input/output module and memory

Technical Field

The present application relates to the field of memory technologies, and in particular, to an input/output module and a memory.

Background

With the development of memory technology and the increasing prominence of memory wall (performance of memory performance limiting processor) problems, various new memories have attracted more and more attention, such as magnetic random access memory (magnetic random access memory, MRAM), resistive random access memory (resistive random access memory, RRAM), phase change memory (phase change memory, PCM), ferroelectric memory (ferroelectric random access memory, feRAM), and the like.

The structure of this new type of memory is generally shown in fig. 1. The memory comprises a plurality of input/output (IO) modules and a memory array, wherein the memory array comprises a plurality of memory cells, and each IO module is responsible for writing and reading data in the memory array which are correspondingly connected. Each IO block includes a Write Driver (WD) circuit for writing data in parallel and a Sense Amplifier (SA) circuit for reading data in parallel.

Specifically, when writing data, a voltage is applied to the WL, so that a switching tube in the memory cell is opened; meanwhile, the WD circuit generates a write current or a write voltage at an output terminal wd_out according to the write signal WT, selects a memory cell to which data is to be written through a Multiplexer (MUX), and applies the write current or the write voltage to the memory cell through a Bit Line (BL)/Source Line (SL), thereby writing corresponding data. It is clear that the data writing process involves charging and discharging the MUX/BL/SL nodes.

There are two types of write drive circuits: current source type and voltage source type.

The current source type write driving circuit may form a current mirror with M1 and M2 as current sources to generate a current required to write data and connected in series with M3 as shown in fig. 2. During writing, the M3 switch tube is opened, and the current generated by the writing driving circuit is applied to the corresponding BL or SL through the output end WD_OUT via the MUX, and further applied to the memory cell to be written. For the current source type write driving circuit, because the parasitic capacitance of the MUX/BL/SL and other nodes is larger, the MUX/BL/SL and other nodes need to be charged for a longer period of time at the beginning of writing, and the current I flowing through the memory cell after the charging is completed _cell Can reach a stable value and openThe active write time is started as shown in fig. 3. The longer charge time at the beginning of writing results in longer total writing time, which is detrimental to high-speed writing of the memory.

The voltage source type write driving circuit may be as shown in fig. 4, which provides the voltage required for writing data, which is typically generated by a low dropout linear regulator (low dropout regulator, LDO) and shared by the IO blocks. The write driver circuit in each IO module may be a switching tube connected to the LDO. In the writing process, the switching tube is conducted under the control of a writing signal WT, and the voltage V generated by the LDO _LDO Will be applied to the MUX by the write driver circuit, to the BL/SL via the MUX, and further to the memory cell to be written. For the voltage source type write driving circuit, when writing starts, because the nodes such as MUX/BL/SL and the like are charged and discharged at first, a large instant current is pumped into the LDO in a short time, and the voltage V output by the LDO _LDO Can drop and slowly recover to stabilize, and the voltage V on the storage unit after the charge and discharge are completed _cell The stable value is reached and the effective write time is started, as shown in fig. 5. Therefore, the writing process needs to be performed after a stable period of time. Too long settling time also results in longer total writing time, which is detrimental to high-speed writing of the memory.

In summary, the input/output module provided in the prior art is used for writing data, so that the problems of long writing time and low data writing efficiency exist.

Disclosure of Invention

The embodiment of the application provides an input/output module and a memory, which are used for reducing data writing time and improving data writing efficiency of the memory.

In a first aspect, embodiments of the present application provide an input-output module coupled to a memory array, including a driver circuit and a write assist circuit. The driving circuit is used for generating a driving signal according to the writing signal and the data to be written, and the driving signal is used for driving the storage array to write the data to be written; the write auxiliary circuit is coupled with the output end of the driving circuit and is used for outputting write auxiliary current when the storage array writes data to be written; when the write current flowing through the memory array reaches a first threshold, the write assist current stops being output.

The process of driving the memory array to write the data to be written by the driving circuit may be: the driving circuit receives a writing signal, and when the writing signal is effective, the driving circuit outputs different currents or voltages according to the value of the data to be written so as to drive different data to be written in the memory array.

With the input-output module provided in the first aspect, the write assist circuit may output the write assist current when the memory array writes data to be written, and stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold. That is, the write assist circuit can provide write assist current for the driving circuit at the initial stage of the writing stage, so as to shorten the charge and discharge time of the parasitic capacitor at the initial stage of the writing stage, so that the current or voltage actually flowing through the memory cell can reach a stable value faster, thereby reducing the data writing time and improving the data writing rate.

In one possible design, the write assist circuit includes a write assist current generating circuit and a control circuit. The write auxiliary current generation circuit is used for generating write auxiliary current; the control circuit is used for controlling the write auxiliary current generating circuit to output write auxiliary current when the memory array writes data to be written.

The control circuit may be further configured to control the write assist current generation circuit to stop outputting the write assist current when the write current flowing through the memory array reaches a first threshold.

With the above scheme, the write assist current generating circuit is configured to generate a write assist current, and the control circuit is configured to control when the write assist current generating circuit provides the write assist current to the output terminal of the driving circuit 601.

In one possible design, the control circuit includes an inverter, a delay, and a NAND gate. The inverter is used for performing inverting operation on the write signal to obtain an inverted signal; the delayer is used for carrying out delay operation on the write signal to obtain a delay signal, and the delay time of the delayer is smaller than the writing effective time of the write signal; the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generating circuit; when the enable signal is active, the write assist current generating circuit outputs a write assist current.

By adopting the scheme, the enabling signal is a short pulse triggered by the falling edge or the rising edge of the writing signal, and the pulse width of the enabling signal is determined by the delay time length of the delayer. Therefore, the enable signal is active at the initial stage of the writing stage, so that the write-assist current generating circuit is triggered to output the write-assist current at the initial stage of the writing stage, and the charge and discharge rate of the nodes such as MUX/BL/SL is accelerated.

In another possible design, the control circuit includes a comparator and an or gate. The comparator is used for comparing the voltage value of the reference voltage and the voltage value of the driving signal and outputting a comparison signal; the OR gate circuit is used for performing OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generation circuit; when the enable signal is active, the write assist current generating circuit outputs a write assist current.

With the above scheme, the enable signal is a short pulse triggered by the falling edge or rising edge of the write signal, and its pulse width is determined by the magnitude of the reference voltage. Therefore, the enable signal is active at the initial stage of the writing stage, so that the write-assist current generating circuit is triggered to output the write-assist current at the initial stage of the writing stage, and the charge and discharge rate of the nodes such as MUX/BL/SL is accelerated.

Further, the control circuit may further include a reference voltage generation module. The reference voltage generation module is coupled with the comparator and is used for outputting a reference voltage.

By adopting the scheme, the reference voltage can be generated by the reference voltage generating module and used for providing the reference voltage for the comparator in the control circuit.

In particular, the reference voltage generation module may include an analog driving circuit, an analog memory array, and a voltage output module. The analog driving circuit is used for generating a module driving signal, and the analog driving signal is used for driving the analog memory array to write analog data; the analog storage array is used for writing analog data under the driving of an analog driving signal; the voltage output module is used for outputting the stable value as the reference voltage when the output voltage of the analog driving circuit reaches the stable value.

By adopting the scheme, the stable voltage value of the driving signal when the driving circuit 601 writes data can be obtained through simulating the process of driving the storage array to write data by the driving circuit. After the stable value is reached, the effective writing time is entered, the stable value is used as a reference voltage to be output to the control circuit, the control module circuit can control the writing auxiliary current generating circuit to output the writing auxiliary current when the voltage value of the driving signal does not reach the reference voltage, and the writing auxiliary current generating circuit is controlled to stop outputting the writing auxiliary current when the voltage value of the driving signal reaches the reference voltage.

In one possible design, the write assist current generating circuit includes a first switching tube, a control electrode of which is coupled to the control circuit for turning on or off under control of the control circuit; the first electrode of the first switching tube is coupled to a voltage source, and the second electrode of the first switching tube is coupled to an output of the driving circuit.

By adopting the scheme, when the enabling signal output by the control circuit is effective, the first switching tube is conducted, and the current output by the voltage source can be output to the output end of the driving circuit through the first switching tube, so that the writing auxiliary current is provided for the driving circuit in the initial stage of the writing stage.

In one possible design, the write assist current generating circuit includes a second switching tube and a current source. The control electrode of the second switching tube is coupled with the control circuit and is used for being turned on or turned off under the control of the control circuit; the current source is coupled with the second switching tube and is used for outputting the output current to the output end of the driving circuit when the second switching tube is conducted.

By adopting the scheme, when the enabling signal output by the control circuit is effective, the second switching tube is conducted, and the output current of the current source can be output to the output end of the driving circuit, so that the writing auxiliary current is provided for the driving circuit in the initial stage of the writing stage.

In one possible design, the input-output module provided in the first aspect may further include a multiplexer. The multiplexer is coupled with the driving circuit and is used for writing the data to be written into all or part of the memory cells in the memory array according to the driving signal.

When writing data, only part of memory cells in the memory array need to write data, and other memory cells do not need to write data.

In one possible design, the input-output module provided in the first aspect may further include a sense amplifier SA. The SA is used for reading data to be read stored in the storage array.

In a second aspect, embodiments of the present application provide an input-output module coupled to a memory array, including a drive circuit and a control circuit. The driving circuit is used for generating a driving signal according to the writing signal and the data to be written, and the driving signal is used for driving the storage array to write the data to be written; the control circuit comprises an inverter, a delay device and a NAND gate circuit; the inverter is used for performing inverting operation on the write signal to obtain an inverted signal; the delayer is used for carrying out delay operation on the write-in signal to obtain a delay signal; the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.

In a third aspect, embodiments of the present application provide an input-output module coupled to a memory array, including a drive circuit and a control circuit. The driving circuit is used for generating a driving signal according to the writing signal and the data to be written, and the driving signal is used for driving the storage array to write the data to be written; the control circuit comprises a comparator and an OR gate circuit; the comparator is used for comparing the voltage value of the reference voltage and the voltage value of the driving signal and outputting a comparison signal; the OR gate circuit is used for performing OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.

The control circuit may further include a reference voltage generation circuit coupled to the comparator for outputting a reference voltage.

In a fourth aspect, an embodiment of the present application provides a memory. The memory comprises a memory array and an input-output module provided in any one of the above first to third aspects and any possible designs thereof, the input-output module being coupled to the memory array for driving the memory array to write data to be written.

In addition, it should be understood that the technical effects of the second aspect to the fourth aspect and any of the possible designs thereof may refer to the technical effects of the different designs in the first aspect, which are not described herein.

Drawings

FIG. 1 is a schematic diagram of a memory according to the prior art;

FIG. 2 is a schematic diagram of a write driver circuit according to the prior art;

FIG. 3 is a waveform diagram of a current flowing through a memory cell when writing data according to the prior art;

FIG. 4 is a schematic diagram of another write driver circuit according to the prior art;

FIG. 5 is a waveform diagram of the voltage on a memory cell when writing data according to the prior art;

fig. 6 is a schematic structural diagram of a first input/output module according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a second input/output module according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a control circuit according to an embodiment of the present application;

FIG. 9 is a waveform diagram of a write signal, an inversion signal, a delay signal and an enable signal according to an embodiment of the present application;

FIG. 10 shows a current I flowing through a memory cell according to an embodiment of the present application _cell A comparison diagram with the prior art;

FIG. 11 is a schematic diagram of another control circuit according to an embodiment of the present application;

FIG. 12 is a waveform diagram of a write signal, a drive signal, a compare signal and an enable signal according to an embodiment of the present application;

FIG. 13 is a schematic diagram showing a current V of a memory cell according to an embodiment of the present application _cell A comparison diagram with the prior art;

FIG. 14 is a schematic diagram of a write assist current generating circuit according to an embodiment of the present application;

FIG. 15 is a schematic diagram of another write assist current generating circuit according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;

FIG. 17 is a schematic diagram of another driving circuit according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of a third input/output module according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of a fourth input/output module according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of a fifth input/output module according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of a sixth input/output module according to an embodiment of the present application;

FIG. 22 is a schematic diagram of a reference voltage generating module according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a memory according to an embodiment of the present application.

Detailed Description

The application scenario of the embodiment of the present application is first described below.

The embodiment of the application can be applied to the memory shown in fig. 1. The memory shown in fig. 1 includes a plurality of IO modules and a memory array, where the memory array includes a plurality of memory cells, and each IO module is responsible for writing and reading a portion of data in the memory array. Each IO module comprises a write driving circuit and an SA, wherein the write driving circuit is used for writing data in parallel, and the SA is used for reading data in parallel.

When writing data, the data writing process involves charging and discharging the nodes such as MUX/BL/SL, and the current I flowing through the memory cell _cell And voltage V on the memory cell _cell After a period of stable time, the stable value can be reached, and the effective writing time is entered. The embodiment of the application reduces I when writing data by improving the structure of the IO module _cell And V _cell The stable time of the memory is improved.

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

In the embodiment of the present application, the plurality means two or more. In addition, in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not be construed as indicating or implying a relative importance or order. The term "coupled" in the embodiments of the present application refers to an electrical connection, and may specifically include a direct connection or an indirect connection.

An embodiment of the present application provides an input-output module, referring to fig. 6, an input-output module 600 is coupled to a memory array. The input-output module 600 includes a driving circuit 601 and a write assist circuit 602.

Specifically, the driving circuit 601 is configured to generate a driving signal according to a writing signal and data to be written, where the driving signal is configured to drive the memory array to write the data to be written; the write assist circuit 602 is coupled to an output of the driving circuit 601 for outputting a write assist current when the memory array is writing data to be written; when the write current flowing through the memory array reaches a first threshold, the write assist current stops being output.

In the embodiment of the present application, the structure of the driving circuit 601 is not different from that of the prior art writing driving circuit, and will not be described here again. The memory array may be formed of a plurality of memory cells, and as shown in fig. 6, the specific structure of the memory cells may also be described with reference to the prior art. In addition, the write current flowing through the memory array is the write current flowing through the memory cells in the memory array, as shown in fig. 6. In the following figures, the specific structure of the memory array will not be shown in detail.

The process of driving the memory array to write data to be written by the driving circuit 601 may be: the driving circuit 601 receives a write signal, and when the write signal is valid, the driving circuit 601 outputs different currents or voltages according to the value of the data to be written, so as to drive different data to be written in the memory array.

Unlike the prior art, in the embodiment of the present application, the input/output module 600 further includes a write assist circuit 602 for outputting a write assist current when the storage array writes data to be written; when the write current flowing through the memory array reaches a first threshold, the write assist current stops being output. That is, the write assist circuit 602 may provide the write assist current to the driving circuit 601 at the initial stage of the writing phase, so as to shorten the charge and discharge time of the parasitic capacitor at the initial stage of the writing phase, so that the current or voltage actually flowing through the memory cell can reach the stable value faster, thereby reducing the data writing time and improving the data writing rate.

Specifically, the write assist circuit 602 may be composed of a write assist current generation circuit and a control circuit, as shown in fig. 7. The write assist current generating circuit is used for generating a write assist current; the control circuit is used for controlling the write auxiliary current generating circuit to output write auxiliary current when the memory array writes data to be written. The control circuit is further configured to control the write assist current generation circuit to stop outputting the write assist current when the write current flowing through the memory array reaches a first threshold.

That is, the write assist current generating circuit is configured to generate a write assist current, and the control circuit is configured to control when the write assist current generating circuit supplies the write assist current to the output terminal of the driving circuit 601.

Specific configurations of the control circuit and the write assist current generating circuit are described in detail below.

1. Control circuit

The composition of the control circuit is described in detail below by way of two specific examples.

Example one

In example one, the control circuit includes an inverter, a delay (also referred to as a delay chain), and a nand gate, as shown in fig. 8. The inverter is used for performing inverting operation on the write signal to obtain an inverted signal; the delayer is used for carrying out delay operation on the write signal to obtain a delay signal, and the delay time of the delayer can be smaller than the effective writing time of the write signal; the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generating circuit; when the enable signal is active, the write assist current generating circuit outputs a write assist current.

Assuming that the write signal is active low, waveforms of the write signal, the inversion signal, the delay signal, and the enable signal may be as shown in fig. 9. As can be seen from fig. 9, the enable signal is a short pulse triggered by the falling edge of the write signal, the pulse width of which is determined by the delay time of the delay. Therefore, the enable signal is active at the initial stage of the writing stage, so that the write-assist current generating circuit is triggered to output the write-assist current at the initial stage of the writing stage, and the charge and discharge rate of the nodes such as MUX/BL/SL is accelerated.

As described above, the control circuit controls the write assist circuit generating circuit to stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold. In the first example, the control circuit controls the write assist current generating circuit to stop outputting the write assist current after the duration of outputting the write assist current by the write assist circuit generating circuit reaches the set duration. In this regard, it can be understood that: in the embodiment of the application, the duration of the write auxiliary current superposed on the memory array can be determined by a test method, and the write current flowing through the memory unit can reach the first threshold value, so that the duration obtained by the test is taken as the set duration.

Using the control circuit of fig. 9 to enable the write assist current generating circuit to output a write assist current, the current I flowing through the memory cell is compared to prior art schemes _cell A stable value can be reached in a short time, for example, through a storage listCurrent I of the cell _cell As can be seen in fig. 10.

It should be noted that the configuration of the control circuit shown in the first example is merely illustrative, and in practical applications, the control circuit may use other logic gates and/or other devices to operate the write signal, so as to obtain a short pulse triggered by a rising edge (active high level) or a falling edge (active low level) of the write signal, through which the write assist current generating circuit is enabled to output the write assist current at an early stage of the writing phase.

It should be noted that, when the i/o module 600 is applied to the memory shown in fig. 1, the control circuit may be unique to each i/o module, or may be shared by a plurality of i/o modules, which is not particularly limited in the embodiment of the present application.

Example two

In example two, the control circuit includes a comparator and an or gate circuit, as shown in fig. 11. The comparator is used for comparing the voltage value of the reference voltage and the voltage value of the driving signal and outputting a comparison signal; the OR gate circuit is used for performing OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generation circuit; when the enable signal is active, the write assist current generating circuit outputs a write assist current.

Assuming that the write signal is active low, waveforms of the write signal, the drive signal, the compare signal, and the enable signal may be as shown in fig. 12. As can be seen from fig. 12, the enable signal is a short pulse triggered by the falling edge of the write signal, the pulse width of which is determined by the magnitude of the reference voltage. Therefore, the enable signal is active at the initial stage of the writing stage, so that the write-assist current generating circuit is triggered to output the write-assist current at the initial stage of the writing stage, and the charge and discharge rate of the nodes such as MUX/BL/SL is accelerated.

As previously described, the control circuit controls the write assist circuit generation module to stop outputting the write assist current when the write current flowing through the memory array reaches a first threshold. In the second example, the control circuit controls the write assist current generating circuit to stop outputting the write assist current when the voltage value of the output signal of the driving circuit reaches the reference voltage value. In this regard, it can be understood that: in the embodiment of the application, when the voltage value of the output signal of the driving circuit is determined by a testing method, the write current flowing through the memory cell can reach the first threshold value, and then the tested voltage is used as the reference voltage.

Using the control circuit of FIG. 11 to enable the write assist current generating circuit to generate the write assist current, the voltage V of the memory cell is higher than that of the prior art _cell Can be stabilized in a short time, for example, the voltage V of the memory cell _cell As can be seen in fig. 13.

Furthermore, in example two, the control circuit may further include a reference voltage generation module coupled to the comparator for outputting the reference voltage to the comparator.

In particular, the reference voltage generation module may include an analog driving circuit, an analog memory array, and a voltage output module. The analog driving circuit is used for generating a module driving signal which is used for driving the analog storage array to write analog data; the analog storage array is used for writing analog data under the driving of an analog driving signal; the voltage output module is used for outputting the stable value as the reference voltage when the output voltage of the analog driving circuit reaches the stable value.

That is, in the embodiment of the present application, the process of driving the memory array to write data by the driving circuit 601 may be simulated, the stable voltage value of the driving signal when the driving circuit 601 writes data is obtained, and after reaching the stable value, the effective writing time is entered, for example, the stable value may be in the waveform diagram shown in fig. 3, I _cell And when the effective writing time is entered, the corresponding WD_OUT signal is valued. The stable value is used as a reference voltage to be output to a control circuit, and the control circuit can control the write auxiliary current generating circuit to output the write auxiliary current when the voltage value of the driving signal does not reach the reference voltage, and can control the write auxiliary current when the voltage value of the driving signal reaches the reference voltageThe flow generating circuit stops outputting the write assist current.

It should be noted that, the control circuit shown in the second example is merely illustrative, and in practical applications, the control circuit may use other logic gates and/or other devices to operate on the write signal, so as to obtain a short pulse triggered by a rising edge (active high level) or a falling edge (active high level) of the write signal, through which the write assist current generating circuit is enabled to output the write assist current in an early stage of the writing phase.

It should be noted that, when the i/o module 600 is applied to the memory shown in fig. 1, the control circuit in the second example may be unique to each i/o module, or may be shared by a plurality of i/o modules, or a part of the control circuit is shared by a plurality of i/o modules, and a part of the control circuit is unique to each i/o module, for example, a plurality of i/o modules share a reference voltage generating module, and a comparator and an or circuit are configured in each i/o module.

2. Write assist current generation circuit

The composition of the write assist current generating circuit is described in detail below by way of two specific examples.

Example one

In example one, the write assist current generating circuit is composed of a first switching transistor, as shown in fig. 14. The control electrode of the first switching tube is coupled with the control circuit and is used for being turned on or turned off under the control of the control circuit; a first electrode of the first switching tube is coupled to a voltage source and a second electrode of the first switching tube is coupled to an output of the driving circuit 601.

In the example of fig. 14, a first switching transistor is exemplified as a metal-oxide-semiconductor field-effect transistor (MOSFET). In practical applications, the switching transistor in the embodiment of the present application may be a gallium nitride (GaN) transistor, an insulated gate bipolar transistor (insulated gate bipolar transist, IGBT), or a bipolar junction transistor (bipolar junction transistor, BJT). The control electrode of the switching tube is an electrode for controlling the switching tube to be turned on and off, for example, the control electrode can be a grid electrode; the first electrode and the second electrode of the switching tube are two electrodes through which on current flows when the switching tube is conducted.

In the first example, when the enable signal output by the control circuit is valid, the first switching tube is turned on, and the current output by the voltage source can be output to the output end of the driving circuit 601 through the first switching tube, so that the write assist current is provided to the driving circuit 601 in the early stage of the writing phase.

Example two

In example two, the write assist current generating circuit is composed of a second switching transistor and a current source, as shown in fig. 15. The control electrode of the second switching tube is coupled with the control circuit and is used for being turned on or turned off under the control of the control circuit; the current source is coupled to the second switching tube for outputting an output current to the output of the driving circuit 601 when the second switching tube is turned on.

The current source can be realized by a switching tube with a fixed grid bias voltage, or can be realized by a current mirror.

In the second example, when the enable signal output by the control circuit is valid, the second switching tube is turned on, and the output current of the current source can be output to the output terminal of the driving circuit 601, so as to provide the write assist current for the driving circuit 601 in the early stage of the writing phase.

As described above, in the embodiment of the present application, the specific structure of the driving circuit 601 may refer to the prior art. Two specific configurations of the driving circuit 601 are listed below.

By way of example, one possible structural schematic of the drive circuit 601 may be as shown in fig. 16. The driving circuit shown in fig. 16 is a current source type driving circuit, M1 and M2 form a current mirror, and M2 is used as a current source of the driving circuit 601 to generate a current required for writing data and is connected in series with M3. When writing data, M3 is conducted when a writing signal is effective, and current in M2 can be output to WD_OUT through M3; when the data to be written is different, the currents output by wd_out are different to write different data.

By way of example, one possible structural schematic of the drive circuit 601 may be as shown in fig. 17. The driving circuit 601 shown in fig. 17 is a voltage source type driving circuit and is composed of a switching transistor M1. LDO output voltage V _LDO A voltage is provided for M1. When writing data, M1 is turned on when the write signal is active, V _LDO Output through output terminal wd_out; when the data to be written is different, the voltages of wd_out are different to write different data.

It should be noted that, in the embodiment of the present application, the specific structure of the driving circuit 601 is not limited to the structure shown in the above two examples, and other structures of the write driving circuit in the prior art are equally applicable in the embodiment of the present application.

In addition, in the embodiment of the present application, the input/output module 600 may further include a multiplexer, as shown in fig. 18. The multiplexer is coupled to the driving circuit 601 for writing the data to be written to all or part of the memory cells in the memory array according to the driving signal.

That is, when writing data, only a part of memory cells in the memory array may need to write data, while other memory cells do not need to write data, and through the multiplexer, only the memory cells that need to write data may be written with data.

In addition, in the embodiment of the present application, the input/output module 600 may further include a sense amplifier, as shown in fig. 19. The sense amplifier is used for reading data to be read stored in the memory array.

The specific structure and function of the above-mentioned multiplexer and sense amplifier may be referred to the description in the prior art, and will not be repeated here.

In summary, with the input/output module 600 provided in the embodiment of the present application, through the write assist circuit 602, an additional write assist current can be provided at the initial stage of the writing phase of the memory array, so as to shorten the charge/discharge time of the parasitic capacitor at the initial stage of the writing phase, and enable the current or voltage actually flowing through the memory cell to reach a stable value faster, thereby reducing the data writing time and improving the data writing rate.

The input/output module provided by the embodiment of the present application is described below by way of two specific examples.

As shown in fig. 20, a specific example of an IO module provided in an embodiment of the present application is shown. The IO module comprises WD circuits, write assist circuits, SA and MUX. The write auxiliary current generating circuit of the write auxiliary circuit is composed of a PMOS switch tube, and the grid electrode of the write auxiliary current generating circuit is connected with an enabling signal (WA signal) sent from the control circuit; the control circuit is shared by the write assist circuits of all IO modules, the input signal is write signal WT, and the output signal is WA. The WA signal is output from a NAND gate, one input end of the NAND gate is connected with a signal generated after the WT signal passes through an inverter, and the other input end of the NAND gate is connected with a signal generated by the WT signal passing through a delay chain. The control circuit thus functions to generate a short pulse triggered by the falling edge of the WT, the pulse width of which is determined by the delay chain.

In the example of fig. 20, the WD circuit is a voltage source, and the write assist circuit generates a write assist current and charges the MUX/BL/SL nodes at the same time when the write operation starts, so that the current draw of the WD circuit to the LDO is reduced, and the current or voltage on the memory cell can reach a stable value faster, thereby improving the write speed.

As shown in fig. 21, a specific example of an IO module provided in an embodiment of the present application is shown. The IO module comprises WD circuits, write assist circuits, SA and MUX. The write assist circuit includes a control circuit and a write assist current generating circuit.

The write assist current generating circuit in the write assist circuit comprises a PMOS switch tube and a PMOS current source, wherein the control circuit is divided into two parts, one part of the control circuit is positioned in each IO module and is a comparator and an OR gate, wherein the comparator is used for comparing WD_OUT signals with reference voltage V _REF Comparing, and performing OR operation on the result and the WT signal, and outputting the operation result to the grid electrode of the PMOS switching tube in the write auxiliary current generating circuit; another part of the control circuit is shared by all the write-assist circuits and is used for outputting a reference voltage V _REF 。

In the example of fig. 21, the WD circuit is a current source, and the write assist circuit generates a write assist current and charges the MUX/BL/SL nodes at the same time when the write operation starts, so that each node can reach a stable voltage faster, and the current or voltage on the memory cell can reach a stable value faster, thereby improving the write speed.

Generating a reference voltage V _REF The circuit of (2) is shown in fig. 22. The dummy write circuit is composed of a dummy WD circuit and a dummy array, wherein the dummy write drive current is applied to the dummy array, and when the voltage generated at the output end of the dummy WD circuit is approximately equal to the stable voltage value of the WD circuit during writing, the stable voltage value can be used as a reference voltage V _REF And (3) using.

In addition, the embodiment of the application also provides an input-output module which is coupled with the storage array and comprises a driving circuit and a control circuit. As shown in fig. 8, the driving circuit is configured to generate a driving signal according to a writing signal and data to be written, where the driving signal is configured to drive the memory array to write the data to be written; the control circuit comprises an inverter, a delay device and a NAND gate circuit; the inverter is used for performing inverting operation on the write signal to obtain an inverted signal; the delayer is used for carrying out delay operation on the write-in signal to obtain a delay signal; the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.

It should be noted that, the specific structure and the working principle of the input/output module may be referred to the related description in fig. 8, and will not be described herein.

It should also be noted that the specific structure of the control circuit is not limited to the structure shown in fig. 8. In the embodiment of the application, the control circuit can generate a short pulse triggered by the rising edge or the falling edge of the writing signal, and the specific structure of the control circuit is not limited.

In addition, the embodiment of the application also provides an input-output module which is coupled with the storage array and comprises a driving circuit and a control circuit. As shown in fig. 11, the driving circuit is configured to generate a driving signal according to a writing signal and data to be written, where the driving signal is configured to drive the memory array to write the data to be written; the control circuit comprises a comparator and an OR gate circuit; the comparator is used for comparing the voltage value of the reference voltage and the voltage value of the driving signal and outputting a comparison signal; the OR gate circuit is used for performing OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.

It should be noted that, the specific structure and the working principle of the input/output module may be referred to the related description in fig. 11, and will not be described herein.

It should also be noted that the specific structure of the control circuit is not limited to the structure shown in fig. 11. In the embodiment of the application, the control circuit can generate a short pulse triggered by the rising edge or the falling edge of the writing signal, and the specific structure of the control circuit is not limited.

Based on the same inventive concept, the embodiment of the present application also provides a memory, see fig. 23. The memory 2300 includes a memory array 2301 and the aforementioned input-output module 600, the input-output module 600 being coupled to the memory array 2301 for driving the memory array 2301 to write data to be written.

It should be noted that, the implementation manner and technical effects of the implementation manner not described in detail in the memory 2300 may be referred to the related description in the input/output module 600, and are not described herein again.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.

Claims

An input-output module, wherein the input-output module is coupled to a memory array, comprising:

the driving circuit is used for generating a driving signal according to a writing signal and data to be written, and the driving signal is used for driving the storage array to write the data to be written;

a write assist circuit coupled to an output of the drive circuit for outputting a write assist current when the memory array is writing the data to be written; when the write current flowing through the memory array reaches a first threshold, the write assist current is stopped from being output.
The input-output module of claim 1, wherein the write assist circuit comprises:

a write assist current generating circuit for generating the write assist current;

a control circuit for controlling the write assist current generation circuit to output the write assist current when the memory array writes the data to be written; and controlling the write assist current generating circuit to stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold.
The input-output module according to claim 1 or 2, wherein the control circuit includes:

the inverter is used for performing inverting operation on the write-in signal to obtain an inverted signal;

the delayer is used for carrying out delay operation on the write-in signal to obtain a delay signal;

the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generating circuit; when the enable signal is valid, the write assist current generating circuit outputs the write assist current.
The input-output module according to claim 1 or 2, wherein the control circuit includes:

the comparator is used for comparing the reference voltage with the voltage value of the driving signal and outputting a comparison signal;

the OR gate circuit is used for carrying out OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for enabling the write auxiliary current generation circuit; when the enable signal is valid, the write assist current generating circuit outputs the write assist current.
The input-output module of claim 4, wherein the control circuit further comprises:

and the reference voltage generation module is coupled with the comparator and is used for outputting the reference voltage.
The input-output module as set forth in claim 5, wherein the reference voltage generation module comprises:

the analog driving circuit is used for generating a module driving signal which is used for driving the analog storage array to write analog data;

the analog storage array is used for writing the analog data under the drive of the analog drive signal;

and the voltage output module is used for outputting the stable value as the reference voltage when the output voltage of the analog driving circuit reaches the stable value.
The input-output module according to any one of claims 2 to 6, wherein the write assist current generating circuit includes:

the control electrode of the first switching tube is coupled with the control circuit and is used for being turned on or turned off under the control of the control circuit; the first electrode of the first switching tube is coupled with a voltage source, and the second electrode of the first switching tube is coupled with the output end of the driving circuit.
The input-output module according to any one of claims 2 to 6, wherein the write assist current generating circuit includes:

the control electrode of the second switching tube is coupled with the control circuit and is used for being turned on or turned off under the control of the control circuit;

and the current source is coupled with the second switching tube and is used for outputting the output current to the output end of the driving circuit under the condition that the second switching tube is conducted.
The input-output module according to any one of claims 1 to 8, further comprising:

and the multi-path gate is coupled with the driving circuit and is used for writing the data to be written into all or part of memory cells in the memory array according to the driving signal.
The input-output module according to any one of claims 1 to 9, further comprising:

and the sense amplifier SA is used for reading the data to be read stored in the storage array.
An input-output module, wherein the input-output module is coupled to a memory array, comprising:

the driving circuit is used for generating a driving signal according to a writing signal and data to be written, and the driving signal is used for driving the storage array to write the data to be written;

the control circuit comprises an inverter, a delay device and a NAND gate circuit; the inverter is used for performing inverting operation on the write-in signal to obtain an inverted signal; the delayer is used for carrying out delay operation on the write-in signal to obtain a delay signal; the NAND gate circuit is used for carrying out NAND operation on the inverted signal and the delay signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.
An input-output module, wherein the input-output module is coupled to a memory array, comprising:

the driving circuit is used for generating a driving signal according to a writing signal and data to be written, and the driving signal is used for driving the storage array to write the data to be written;

the control circuit comprises a comparator and an OR gate circuit; the comparator is used for comparing the reference voltage with the voltage value of the driving signal and outputting a comparison signal; the OR gate circuit is used for performing OR operation on the comparison signal and the write signal to obtain an enabling signal, and the enabling signal is used for controlling the output of the write auxiliary current to the output end of the driving signal.
The input-output module of claim 12, wherein the control circuit further comprises:

and the reference voltage generating circuit is coupled with the comparator and is used for outputting the reference voltage.
A memory comprising a memory array and an input-output module as claimed in any one of claims 1 to 13 coupled to the memory array for driving the memory array to write data to be written.