CN116707515A - Anti-false trigger circuit, method, system, power amplifier circuit and device - Google Patents
Anti-false trigger circuit, method, system, power amplifier circuit and device Download PDFInfo
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- CN116707515A CN116707515A CN202310632286.4A CN202310632286A CN116707515A CN 116707515 A CN116707515 A CN 116707515A CN 202310632286 A CN202310632286 A CN 202310632286A CN 116707515 A CN116707515 A CN 116707515A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
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Abstract
Description
技术领域technical field
本发明涉及集成电路技术领域，具体涉及一种防误触发电路、方法、系统、功放电路和设备。The invention relates to the technical field of integrated circuits, in particular to an anti-false trigger circuit, method, system, power amplifier circuit and equipment.
背景技术Background technique
现有N型功率管在使用时，由于栅极处的寄生效果，可能会出现毛刺现象，而对于毛刺现象，当N型功率管栅压为0V，处于关断状态时，若栅极上出现毛刺，则会导致N型功率管导通，从而产生误触发情况，影响电路的正常使用。When the existing N-type power tube is in use, due to the parasitic effect at the gate, glitches may appear. For the glitch phenomenon, when the grid voltage of the N-type power tube is 0V and it is in the off state, if there is a glitch on the grid Glitches will cause the N-type power transistor to be turned on, resulting in false triggering and affecting the normal use of the circuit.
发明内容Contents of the invention
本发明针对现有技术中的缺点，提供了一种防误触发电路、方法、系统、功放电路和设备，解决了现有N型功率管因毛刺发生误触发情况的问题。Aiming at the shortcomings in the prior art, the present invention provides an anti-false triggering circuit, method, system, power amplifier circuit and equipment, which solves the problem of false triggering of existing N-type power tubes due to glitches.
为了解决上述技术问题，本发明通过下述技术方案得以解决：In order to solve the above technical problems, the present invention is solved through the following technical solutions:
一种防误触发电路，包括输入电路、毛刺触发电路和逻辑电路，所述输入电路的输出端与毛刺触发电路的输入端相连，所述毛刺触发电路的输出端、输入电路的输入端均与逻辑电路的输入端相连。An anti-false trigger circuit, comprising an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected to the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are connected to the The input terminals of the logic circuit are connected.
可选的，所述毛刺触发电路包括反相触发器和同相延迟电路，所述反相触发器的输出端与同相延迟电路的输入端相连。Optionally, the glitch trigger circuit includes an inverting flip-flop and a non-inverting delay circuit, and an output end of the inverting flip-flop is connected to an input end of the non-inverting delay circuit.
可选的，所述同相延迟电路包括偶数个倒相器，且偶数个所述倒相器串联设置。Optionally, the non-inverting delay circuit includes an even number of inverters, and the even number of inverters is arranged in series.
可选的，所述逻辑电路包括与电路、缓冲扩流电路和NMOS管，所述与电路的输出端连接缓冲扩流电路的输入端，所述缓冲扩流电路的输出端与NMOS管的栅极相连。Optionally, the logic circuit includes an AND circuit, a buffer current expansion circuit and an NMOS transistor, the output terminal of the AND circuit is connected to the input terminal of the buffer current expansion circuit, and the output terminal of the buffer current expansion circuit is connected to the gate of the NMOS transistor. Pole connected.
可选的，所述输入电路包括反相驱动电路，所述反相驱动电路用于实现逐级加强。Optionally, the input circuit includes an anti-phase driving circuit, and the anti-phase driving circuit is used to implement step-by-step strengthening.
可选的，所述反相驱动电路包括奇数个倒相器，且奇数个所述倒相器串联设置。Optionally, the inverting drive circuit includes an odd number of inverters, and the odd number of inverters is arranged in series.
一种功放电路，所述功放电路包括上述任意一项所述的防误触发电路，还包括N型功率管信号输入电路，所述防误触发电路的输出端与N型功率管的栅极相连，所述信号输入电路与N型功率管的漏极相连。A power amplifier circuit, the power amplifier circuit includes the anti-false trigger circuit described in any one of the above, and also includes an N-type power tube signal input circuit, and the output terminal of the anti-false trigger circuit is connected to the gate of the N-type power tube , the signal input circuit is connected to the drain of the N-type power transistor.
一种设备，所述设备包括如上述所述的功放电路。A device includes the power amplifier circuit as described above.
一种防止毛刺误触发的方法，所述防止毛刺误触发的方法应用于如上述任意一项所述的防误触发电路，包括以下步骤：A method for preventing false triggering of glitches, the method for preventing false triggering of glitches is applied to the anti-false triggering circuit as described in any one of the above, comprising the following steps:
获取毛刺的原始幅度和原始宽度，并设定幅度阈值和宽度阈值；Obtain the original amplitude and original width of the glitch, and set the amplitude threshold and width threshold;
判断所述毛刺是否同时达到毛刺幅度阈值和毛刺宽度阈值，若是，则解除NMOS管的栅下拉，反之则保持NMOS管的栅下拉。It is judged whether the burr reaches the burr amplitude threshold and the burr width threshold at the same time, and if so, the gate pull-down of the NMOS transistor is released, otherwise, the gate pull-down of the NMOS transistor is maintained.
一种防止毛刺误触发系统，所述系统执行如上述所述的防止毛刺误触发的方法，包括毛刺获取单元和分析判断单元；A system for preventing false triggering of glitches, the system implements the method for preventing false triggering of glitches as described above, including a glitch acquisition unit and an analysis and judgment unit;
所述毛刺获取单元用于获取毛刺的原始幅度和原始宽度，并设定幅度阈值和宽度阈值；The glitch acquisition unit is used to acquire the original amplitude and original width of the glitch, and set the amplitude threshold and the width threshold;
所述分析判断单元用于判断所述毛刺是否同时达到毛刺幅度阈值和毛刺宽度阈值，若是，则解除NMOS管的栅下拉，反之则保持NMOS管的栅下拉。The analysis and judgment unit is used to judge whether the burr reaches the burr amplitude threshold and burr width threshold at the same time, and if so, releases the gate pull-down of the NMOS transistor, otherwise keeps the gate pull-down of the NMOS transistor.
采用本发明提供的技术方案，与现有技术相比，具有如下有益效果：Compared with the prior art, the technical solution provided by the invention has the following beneficial effects:
通过毛刺触发电路的设置，提供了毛刺解除N型功率管的栅下拉的条件，同时，通过毛刺触发电路中的反向触发器设定毛刺触发的毛刺幅度要求，通过同相延迟电路设定毛刺触发的毛刺宽度要求，且两者为同时满足的关系，有效防止了N型功率管栅上的毛刺对下拉管的关断作用，从而下拉管有效地对N型功率管保持下拉能力，进而防止了N型功率管的误触发。The setting of the glitch trigger circuit provides the conditions for the glitch to release the gate pull-down of the N-type power transistor. At the same time, the glitch amplitude requirement of the glitch trigger is set through the reverse trigger in the glitch trigger circuit, and the glitch trigger is set through the non-inverting delay circuit. The burr width requirements, and the relationship between the two are satisfied at the same time, effectively preventing the burr on the N-type power tube grid from shutting down the pull-down tube, so that the pull-down tube can effectively maintain the pull-down capability of the N-type power tube, thereby preventing False triggering of N-type power tubes.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1为本实施例一提出的一种防误触发电路的电路图；FIG. 1 is a circuit diagram of a false trigger prevention circuit proposed in Embodiment 1;
图2为本实施例二提出的一种功放电路的电路图。FIG. 2 is a circuit diagram of a power amplifier circuit proposed in the second embodiment.
具体实施方式Detailed ways
下面结合实施例对本发明做进一步的详细说明，以下实施例是对本发明的解释而本发明并不局限于以下实施例。The present invention will be further described in detail below in conjunction with the examples, the following examples are explanations of the present invention and the present invention is not limited to the following examples.
实施例一Embodiment one
如图1所示，一种防误触发电路，包括输入电路、毛刺触发电路和逻辑电路，输入电路的输出端与毛刺触发电路的输入端相连，毛刺触发电路的输出端、输入电路的输入端均与逻辑电路的输入端相连，具体地，输入电路包括反相驱动电路，反相驱动电路用于实现逐级加强，毛刺触发电路包括反相触发器和同相延迟电路，反相触发器的输出端与同相延迟电路的输入端相连，As shown in Figure 1, a kind of anti-false trigger circuit, comprises input circuit, glitch trigger circuit and logic circuit, the output end of input circuit is connected with the input end of glitch trigger circuit, the output end of glitch trigger circuit, the input end of input circuit They are all connected to the input terminal of the logic circuit. Specifically, the input circuit includes an inverting drive circuit, which is used to realize step-by-step strengthening. The glitch trigger circuit includes an inverting flip-flop and a non-inverting delay circuit. The output of the inverting flip-flop The terminal is connected to the input terminal of the non-inverting delay circuit,
具体地，反相驱动电路包括奇数个倒相器，且奇数个倒相器串联设置，奇数个设置用于实现反相，设定反相驱动电路的输入端为in，输出端为out，其中，当in为“1”，out为“0”时，输出端out连接N型功率管的栅极(在图1中未显示)，此时输出端out为“0”，然后经过反相触发器和同相延迟电路则变为“1”。Specifically, the inverting drive circuit includes an odd number of inverters, and the odd number of inverters is arranged in series, and the odd number of settings is used to achieve inversion, and the input terminal of the inverting drive circuit is set as in, and the output terminal is set as out, where , when in is "1" and out is "0", the output terminal out is connected to the gate of the N-type power transistor (not shown in Figure 1), and the output terminal out is "0" at this time, and then the inverting trigger The device and the non-inverting delay circuit become "1".
而由于逻辑电路包括与电路、缓冲扩流电路和NMOS管，与电路的输出端连接缓冲扩流电路的输入端，缓冲扩流电路的输出端与NMOS管的栅极相连，NMOS管的漏极与输出端out相连，NMOS管的源极接地设置，缓冲扩流电路用于缓冲和驱动下拉管，因此与电路AND在输入in为“1”，反相延迟电路输入“1”时，其输出也为“1”，且缓冲扩流电路(即BUF电路)也输出“1”，于是，NMOS管的下拉管mn1开启，对输出out增强下拉，从而增强N型功率管栅极的下拉能力。And since the logic circuit includes an AND circuit, a buffer current expansion circuit and an NMOS tube, the output end of the AND circuit is connected to the input end of the buffer current expansion circuit, the output end of the buffer current expansion circuit is connected to the gate of the NMOS tube, and the drain of the NMOS tube It is connected to the output terminal out, the source of the NMOS tube is grounded, and the buffer expansion circuit is used to buffer and drive the pull-down tube, so when the input of the AND circuit AND is "1" and the input of the inverting delay circuit is "1", its output It is also "1", and the buffer current expansion circuit (that is, the BUF circuit) also outputs "1", so the pull-down transistor mn1 of the NMOS transistor is turned on, and the pull-down of the output out is enhanced, thereby enhancing the pull-down capability of the gate of the N-type power transistor.
进一步地，同相延迟电路包括偶数个倒相器，且偶数个倒相器串联设置，BUF电路包括偶数个倒相器，且偶数个倒相器串联设置，反向触发器为反相施密特触发器，具有迟滞效应。Further, the non-inverting delay circuit includes an even number of inverters, and the even number of inverters is arranged in series, the BUF circuit includes an even number of inverters, and the even number of inverters is arranged in series, and the reverse trigger is an inverting Schmitt Flip-flop with hysteresis effect.
具体地，当输出端out上有毛刺时，毛刺需要满足两个条件才能解除下拉管mn1对输出端out的下拉，第一是毛刺的幅度要达到反相施密特触发器翻转的触发点，而工作人员可通过设置触发点的触发电压实现触发条件的设置，只需设置的触发电压低于所设定的幅值，则毛刺将无法触发反相施密特触发器，即不满足解除下拉管mn1对N型功率管的栅下拉的第一个条件。Specifically, when there is a glitch on the output terminal out, the glitch needs to meet two conditions to release the pull-down of the output terminal out by the pull-down tube mn1. The first is that the amplitude of the glitch must reach the trigger point of the inverted Schmitt trigger, The staff can set the trigger condition by setting the trigger voltage of the trigger point. As long as the set trigger voltage is lower than the set amplitude, the glitch will not be able to trigger the inverting Schmitt trigger, that is, the release of the pull-down will not be satisfied. The first condition for the gate pull-down of the N-type power transistor by the tube mn1.
第二个条件则是毛刺的宽度，即脉冲的宽度，通过同相延迟电路实现毛刺宽度与延迟电路时间的比较，仅当毛刺宽度比同相延迟电路的时间更长，方能解除下拉管mn1对N型功率管的栅下拉，同时，由于反向施密特触发器与同相延迟电路为串联，因此，只有同时满足以上两个条件后，方可解除下拉管mn1对N型功率管的栅下拉，反之则下拉管mn1保持对N型功率管的栅下拉，防止了因毛刺的产生而导致误触发现象发生。The second condition is the width of the glitch, that is, the width of the pulse. The comparison between the width of the glitch and the time of the delay circuit is realized through the non-inverting delay circuit. Only when the width of the glitch is longer than the time of the non-inverting delay circuit can the pull-down tube mn1 pair N be released. At the same time, since the reverse Schmitt trigger and the non-inverting delay circuit are connected in series, the gate pull-down of the pull-down transistor mn1 to the N-type power transistor can be released only after the above two conditions are met at the same time. On the contrary, the pull-down transistor mn1 keeps pulling down the gate of the N-type power transistor, which prevents false triggering caused by glitches.
实施例二Embodiment two
如图2所述，一种功放电路，功放电路包括实施例一所述的防误触发电路，还包括N型功率管信号输入电路，防误触发电路的输出端与N型功率管的栅极相连，信号输入电路与N型功率管的漏极相连N型功率管的源极接地设置，具体地，N型功率管所产生的毛刺通过C点传输给防误触发电路，然后通过防误触发电路的栅下拉条件设置处理，实现防止误触发的功能，具体可以为CLASSD功放电路。As shown in Figure 2, a power amplifier circuit, the power amplifier circuit includes the anti-false trigger circuit described in Embodiment 1, and also includes an N-type power tube signal input circuit, the output terminal of the anti-false trigger circuit and the grid of the N-type power tube connected, the signal input circuit is connected to the drain of the N-type power tube, and the source of the N-type power tube is grounded. Specifically, the glitch generated by the N-type power tube is transmitted to the anti-false trigger circuit through point C, and then through the anti-false trigger The gate pull-down condition setting process of the circuit realizes the function of preventing false triggering, specifically, it can be a CLASSD power amplifier circuit.
实施例三Embodiment three
一种设备，所述设备包括如实施例二的功放电路，例如含有功放电路的音频设备，具体的，可以为耳机、蓝牙音箱等，在本实施例中不做详细限定。A device, the device includes the power amplifier circuit in Embodiment 2, for example, an audio device including the power amplifier circuit, specifically, earphones, bluetooth speakers, etc., which are not limited in detail in this embodiment.
实施例四Embodiment four
一种防止毛刺误触发的方法，防止毛刺误触发的方法应用于如实施一任意一项的防误触发电路，包括以下步骤：获取毛刺的原始幅度和原始宽度，并设定幅度阈值和宽度阈值；判断毛刺是否同时达到毛刺幅度阈值和毛刺宽度阈值，若是，则解除NMOS管的栅下拉，反之则保持NMOS管的栅下拉，具体地，由于实施例一详细赘述了防止毛刺误触发的原理，因此在本实施例中不做详细阐述。A method for preventing false triggering of glitches, the method for preventing false triggering of glitches is applied to an anti-false triggering circuit of any item, comprising the following steps: obtaining the original amplitude and original width of the glitches, and setting the amplitude threshold and the width threshold Determine whether the burr reaches the burr amplitude threshold and the burr width threshold at the same time, if so, release the grid pull-down of the NMOS transistor, otherwise keep the grid pull-down of the NMOS transistor, specifically, because the first embodiment has described in detail the principle of preventing the false triggering of the burr, Therefore, no detailed description will be given in this embodiment.
实施例五Embodiment five
一种防止毛刺误触发系统，系统执行如实施例四所述的防止毛刺误触发的方法，包括毛刺获取单元和分析判断单元；毛刺获取单元用于获取毛刺的原始幅度和原始宽度，并设定幅度阈值和宽度阈值；分析判断单元用于判断毛刺是否同时达到毛刺幅度阈值和毛刺宽度阈值，若是，则解除NMOS管的栅下拉，反之则保持NMOS管的栅下拉。A system for preventing false triggering of glitches, the system executes the method for preventing false triggering of glitches as described in Embodiment 4, including a glitch acquisition unit and an analysis and judgment unit; the glitch acquisition unit is used to acquire the original amplitude and original width of the glitch, and set Amplitude threshold and width threshold; the analysis and judgment unit is used to judge whether the burr reaches the burr amplitude threshold and burr width threshold at the same time, if so, release the gate pull-down of the NMOS transistor, otherwise keep the gate pull-down of the NMOS transistor.
以上所述，仅为本发明的较佳实施例，并非对本发明任何形式上和实质上的限制，应当指出，对于本技术领域的普通技术人员，在不脱离本发明方法的前提下，还将可以做出若干改进和补充，这些改进和补充也应视为本发明的保护范围。凡熟悉本专业的技术人员，在不脱离本发明的精神和范围的情况下，当可利用以上所揭示的技术内容而做出的些许更动、修饰与演变的等同变化，均为本发明的等效实施例；同时，凡依据本发明的实质技术对上述实施例所作的任何等同变化的更动、修饰与演变，均仍属于本发明的技术方案的范围内。The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any form and in essence. Several improvements and supplements can be made, and these improvements and supplements should also be regarded as the protection scope of the present invention. Those who are familiar with this profession, without departing from the spirit and scope of the present invention, when they can use the technical content disclosed above to make some changes, modifications and equivalent changes of evolution, are all included in the present invention. Equivalent embodiments; at the same time, all changes, modifications and evolutions of any equivalent changes made to the above-mentioned embodiments according to the substantive technology of the present invention still belong to the scope of the technical solution of the present invention.
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