CN116663490A

CN116663490A - Verification method, platform, device and medium of asynchronous memory chip

Info

Publication number: CN116663490A
Application number: CN202310645385.6A
Authority: CN
Inventors: 邱玉泉; 何凯; 张超建
Original assignee: STMicroelectronics Shenzhen R&D Co Ltd
Current assignee: STMicroelectronics Shenzhen R&D Co Ltd
Priority date: 2023-05-31
Filing date: 2023-05-31
Publication date: 2023-08-29

Abstract

A verification method, platform, device and medium for asynchronous memory chip relate to the technical field of chip verification, and the method comprises the following steps: acquiring the running state of equipment to be tested; writing preset verification data into a storage unit of the device to be tested under the condition that the device to be tested is in a writing state; determining that the equipment to be tested is in a reading state, and if the verification data is written into the storage unit of the equipment to be tested, controlling the equipment to be tested to read the data in the storage unit, and sampling the reading result of the equipment to be tested to obtain sampling data; and if the sampling data are inconsistent with the verification data, generating information that the verification of the device to be tested is not passed. According to the application, the verification data is firstly written into the device to be tested in the writing state, the reading result of the device to be tested on the verification data is sampled in the reading state, and the obtained sampling data is compared with the verification data, so that the efficiency of the read-write function of the device to be tested can be improved.

Description

Verification method, platform, device and medium of asynchronous memory chip

Technical Field

The application belongs to the technical field of chip verification, and particularly relates to a verification method, a verification platform, a verification device and a verification medium for an asynchronous memory chip.

Background

With the rapid development of integrated circuits, chip functions are increasingly complex, test verification work in chip design has become the most time-consuming work in a chip research and development process, the proportion of the research and development period occupied by the test verification work is increasingly large, the verification workload has already occupied 65% to 70% of the whole chip research and development, and the large workload is occupied by building a verification platform, debugging the verification platform and waveform checking work in the verification process, so that how to improve the verification efficiency becomes important.

Under the prior art, most of common effective modes for realizing quick verification of an asynchronous memory adopt a simple UVM verification platform to complete scene construction, generate simulation waveforms, check read-write operations of an asynchronous memory chip in a mode of manually opening the waveforms, and judge whether the read-write operations are correct.

Disclosure of Invention

The application aims to provide an authentication method, a platform, a device and a readable medium of an asynchronous memory chip, and aims to solve the problem that the efficiency of passing manual authentication is low in the traditional chip authentication method.

A first aspect of an embodiment of the present application provides a method for verifying an asynchronous memory chip, including the steps of:

acquiring the running state of equipment to be tested;

writing preset data into a storage unit of the device to be tested and a reference model under the condition that the device to be tested is in a writing state, and recording the writing address of the data, wherein the reference model is used for simulating the device to be tested;

determining that the device to be tested is in a read state, and that verification data is written into a storage unit of the device to be tested, controlling a reference model to obtain the verification data according to a writing address of the data, controlling the device to be tested to read the data in the storage unit, and sampling a reading result of the device to be tested to obtain sampling data;

and if the sampling data are inconsistent with the verification data, generating information that the verification of the device to be tested is not passed.

In this embodiment, compared with respectively verifying the read-write function of the device under test, the method includes writing verification data into the device under test in a write state, sampling a read result of the device under test on the verification data in a read state, and comparing the obtained sampling data with the verification data, so that the efficiency of verifying the read-write function of the device under test can be improved.

Further, under the condition that the device to be tested is in a writing state, writing preset data into a storage unit and a reference model of the device to be tested, and further comprising the following steps:

when the equipment to be tested is in a writing state, writing preset data into a storage unit of the equipment to be tested according to a first writing and reading time sequence, and writing the preset data into a reference model according to a second writing and reading time sequence.

Further, before acquiring the operation state of the device to be tested, the method comprises the following steps:

at the falling edge of the high-speed sampling clock, confirming that the high-speed sampling clock completes the sampling period of a preset part, and acquiring a control signal of the equipment to be tested;

and confirming that the equipment to be tested is in a writing state or a reading state according to the control signal of the equipment to be tested.

In this embodiment, the high-speed sampling clock samples the control signal of the device to be tested at the falling edge and when the sampling period of the preset part is completed, so that a more accurate control signal sampling result can be obtained, and the state of the device to be tested can be better judged.

Further, at the falling edge of the high-speed sampling clock, confirming that the high-speed sampling clock completes the sampling period of the preset part, and obtaining the control signal of the device to be tested includes:

determining the preset maximum sampling times of the sampling period of the high-speed sampling clock;

generating a sampling counting signal of the high-speed sampling clock, wherein the sampling counting signal is used for recording the sampling times of the high-speed sampling clock at the current address;

confirming that the high-speed sampling clock is at the falling edge;

and confirming that the high-speed sampling clock completes the sampling period of the preset part according to the sampling counting signal and the maximum sampling times of the sampling period, and obtaining the control signal of the equipment to be tested.

In this embodiment, by presetting the maximum sampling number of sampling periods of the high-speed sampling clock, it is possible to accurately determine whether the high-speed sampling clock has completed a sampling period of a preset portion in the process of sampling by the high-speed sampling clock.

Further, controlling the device to be tested to read the data in the storage unit, and sampling the read result of the device to be tested to obtain sampling data, including:

sampling output data of the equipment to be tested to obtain N sampling data which are continuously sampled;

when N pieces of sampling data sampled continuously are the same, storing the sampling data;

and confirming that the high-speed sampling clock completes the sampling period, and acquiring the last stored sampling data.

In this embodiment, the data is continuously collected, so that the collected last valid data can cover the previous invalid data and is transmitted after the address period counting is finished, and the invalid data generated in the simulation process is prevented from affecting the verification result.

Further, before acquiring the operation state of the device under test, the method further includes the following steps:

different test cases are created according to the test stimulus, and control signals of the device to be tested are generated according to the test cases.

In the embodiment, according to the functions of the asynchronous memory chip to be tested, test excitation with different functions is generated through a preset waveform file, and different test cases are created to complete function verification.

Further, after acquiring the operation state of the device under test, the method further includes the following steps:

and the initial state of the equipment to be tested is a non-chip-selection state.

In this embodiment, since the asynchronous memory chip has other states in addition to the read-write state, verification can also be performed for functions in other states of the device under test.

A second aspect of an embodiment of the present application provides an authentication platform for an asynchronous memory chip, including:

the monitor is used for acquiring the running state of the equipment to be tested;

the writing function unit is used for writing preset data into the storage unit of the equipment to be tested and the reference model under the condition that the equipment to be tested is in a writing state, recording the writing address of the data, and simulating the equipment to be tested by the reference model;

the read verification unit is used for determining that the equipment to be tested is in a read state, and the verification data is written into the storage unit of the equipment to be tested, controlling the reference model to obtain the verification data according to the writing address of the data, controlling the equipment to be tested to read the data in the storage unit, and sampling the reading result of the equipment to be tested to obtain sampling data;

and the comparator is used for comparing the sampling data with the verification data to obtain a verification result of the device to be tested.

A third aspect of an embodiment of the present application provides an authentication device for an asynchronous memory chip, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method as described above when executing the computer program.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method as described above.

Drawings

FIG. 1 is a schematic flow chart of an asynchronous memory chip verification method according to an embodiment of the application;

FIG. 2 is a schematic flow chart of acquiring verification data in a verification method of an asynchronous memory chip according to an embodiment of the application;

FIG. 3 is a schematic flow chart of acquiring a control signal of the device under test in an asynchronous memory chip verification method according to an embodiment of the present application;

FIG. 4 is a schematic flow chart of sampling a device to be tested in an asynchronous memory chip verification method according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of generating test cases in an asynchronous memory chip verification method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a verification platform of an asynchronous memory chip according to an embodiment of the present application;

fig. 7 is a system block diagram of a UVM verification platform corresponding to a verification platform of an asynchronous memory chip according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a tree structure of an asynchronous memory chip verification platform according to an embodiment of the present application;

fig. 9 is a schematic diagram of an authentication device for an asynchronous memory chip according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments.

The following describes the technical solution in the embodiment of the present application with reference to the accompanying drawings. It should be understood that the specific examples in this specification are intended to facilitate a better understanding of the embodiments of the application by those skilled in the art and are not intended to limit the scope of the embodiments of the application.

It should be understood that, in various embodiments of the present application, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It should also be understood that the various embodiments described in this specification may be implemented either alone or in combination, and the present examples are not limited in this regard.

Unless defined otherwise, all technical and scientific terms used in the embodiments of the application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Common memories include synchronous memories (e.g., synchronous dynamic random access memories) and asynchronous memories (e.g., flash memories), wherein asynchronous memory functions are relatively simple and are widely applicable, but the design of asynchronous memory chips in asynchronous memories may vary according to the capacity and rate of storage required. For asynchronous memory chips of different designs, a designer needs to spend a lot of time to verify the design function of the asynchronous memory chip by different verification schemes. Since it takes a lot of time to verify the design function of the asynchronous memory chip, the development efficiency of the asynchronous memory chip is low.

In order to completely verify the design function of the asynchronous memory chip, a common method is to design a verification scene through a UVM verification platform and generate corresponding simulation waveforms, and test cases generated through the simulation waveforms are used for respectively checking the read operation and the write operation of the asynchronous memory chip and judging whether the read and write functions of the asynchronous memory chip are correct.

In view of this, fig. 1 shows a flow chart of a verification method of an asynchronous memory chip according to a preferred embodiment of the present application (fig. 1 shows a first embodiment of the present application), and for convenience of explanation, only the relevant parts of the embodiment are shown, and the details are as follows:

s102, acquiring the running state of the equipment to be tested.

And S104, under the condition that the equipment to be tested is in a writing state, writing preset data into a storage unit of the equipment to be tested and a reference model, and recording the writing address of the data, wherein the reference model is used for simulating the equipment to be tested.

S106, determining that the device to be tested is in a read state, and that the verification data is written into the storage unit of the device to be tested, controlling the reference model to obtain the verification data according to the writing address of the data, controlling the device to be tested to read the data in the storage unit, and sampling the reading result of the device to be tested to obtain the sampling data.

S108, if the sampling data are inconsistent with the verification data, generating information that the verification of the device to be tested is not passed.

It should be appreciated that different devices under test, i.e., asynchronous memory chips under test designed by different designs, perform substantially similar functions and thus share commonalities in designing the verification method of the asynchronous memory chip. In one embodiment of the application, the operation state of the device to be tested is judged by acquiring the port control signal of the device to be tested. Since the most important function of the asynchronous memory chip is the read-write state, in this embodiment, only the case where the device to be tested is in the read state or the write state is verified.

And when the device to be tested is confirmed to be in a writing state, writing preset verification data into a storage unit of the device to be tested. It should be noted that, the preset verification data may be a preset data packet generated according to the test case, or may be verification data after simulation verification is performed on the preset data packet by the simulation device.

When the device to be tested is confirmed to be in a read state, if the verification data is not stored in the storage unit of the device to be tested, the fact that preset verification data is not written into the device to be tested temporarily or the preset verification data is not written into the storage unit of the device to be tested in a previous write state is indicated, the write function failure possibly occurs, if the sampling data cannot be obtained under the condition that the write function fails, verification and error reporting are carried out, and a verification person can determine that the read function of the current device to be tested has a problem. When the sampling data is obtained, the sampling data can generally comprise a storage address and data corresponding to the storage address, and the success of verification can be confirmed only under the condition that the storage address is consistent with verification data and the data corresponding to the storage address is also consistent with the verification data, otherwise, the failure of verification is judged, so that a verification engineer can conveniently and quickly find out the problem, and the bug is tracked and positioned by combining waveforms.

In practical application, the transmitted verification data is stored and written into a memory during writing operation; during the reading operation, the actual reading data generated by the verification data through the equipment to be tested is sent to the comparator; simultaneously, during the reading operation, the data stored during the writing operation is read out and sent to the comparator; the comparator compares the received actual data with the data stored during the writing operation, and if the results are consistent, the verification is passed, otherwise, the relevant error information is printed in the log file.

The following illustrates a verification method for an asynchronous memory chip according to the present application in conjunction with different examples.

In one example, after confirming that a device under test (i.e., an asynchronous memory chip) is in a written state, writing preset verification data into a reference model, and recording a writing address of the verification data, wherein the reference model is used for simulating the device under test;

in determining that the sampling data is inconsistent with the verification data, the reference model needs to be controlled to read the verification data according to the write address of the verification data acquired in the writing state. And then comparing the verification data obtained by reading the reference model with the verification data obtained by reading the equipment to be tested, wherein the verification is successful when the comparison is consistent.

Referring to fig. 2, in an example, in a case where the device under test is in a writing state, writing preset data into a memory cell and a reference model of the device under test, further includes the steps of:

It should be noted that, the first write-read timing sequence and the second write-read timing sequence may be the same timing sequence or may be different timing sequences, and the reference model may more accurately simulate the asynchronous memory chip through the first write-read timing sequence and the second write-read timing sequence.

Referring to fig. 3, in another example, before acquiring an operation state of a device to be tested, a global high-speed sampling clock needs to be generated to ensure that time delays of signals reaching each logic unit are substantially the same.

It should be noted that, the above-mentioned high-speed sampling clock is not reliable in sampling at the rising edge, and in addition, the sampling period of the preset portion is generally half of the sampling period, so that the control signal of the device to be tested can be monitored more accurately.

Further, referring to fig. 4, in another example, in order to confirm that the high-speed sampling clock completes the sampling period of the preset portion, the method provided by the present application first presets the maximum sampling number of the sampling period of the high-speed sampling clock;

confirming that the high-speed sampling clock is at the falling edge;

It should be noted that, by monitoring the port signal of the asynchronous memory chip on the virtual interface, the port state of the control signal is sampled at the sampling period time to determine what working state of the asynchronous memory chip is, for example, taking the UVM verification platform as an example, a high-speed sampling clock required by the monitor is generated at the top file layer of the verification platform and is counted according to the clock during the sampling period, and the code examples are as follows:

the counter is cleared at address transition and the next address cycle is ready to begin counting.

In another example, referring to fig. 5, in order to more accurately acquire sampling data of a device under test in a read state, output data of the device under test is continuously sampled by a high-speed sampling clock, and N continuously sampled sampling data are acquired in a current sampling period;

according to the sampling counting signal and the maximum sampling times of the sampling period, confirming that the high-speed sampling clock completes the sampling period, and acquiring the finally stored sampling data, wherein the code example is as follows:

the code implementation of the address period ending to send the output dout data to the comparator scoreboard is as follows:

by adopting a mode of continuously collecting data, the last collected valid data can cover the invalid data before, and the invalid data is transmitted after the address period counting is finished.

Referring to FIG. 5, in one possible embodiment, a waveform file in VCD, VPD or FSDB format is generated by macro definition to facilitate a verification engineer selecting a desired waveform format according to requirements, and generating test stimulus from the waveform, creating different test cases from the test stimulus. If the device to be tested is not in the read-write state, the verification method provided by the application can verify other states of the chip for the non-chip-selection state or the read-inhibit state of the chip.

Referring to fig. 6 and 7, in an exemplary embodiment of the present application, a general verification methodology (Universal Verification Methodology, UVM) verification platform is taken as an example, and the present application is implemented by logic codes, where the entire verification platform includes a top document layer, a test case layer, and a verification environment layer.

The top file layer realizes data communication between the device to be tested and the verification platform through the virtual interface, and meanwhile, waveform files with different formats can be generated through macro definition, so that a verification engineer can conveniently select a required waveform format according to requirements.

The test case layer only needs to execute the test case establishment command at the terminal according to the simulation running script. The operation modes of the asynchronous memory chip include a basic write-read operation, a non-chip select operation and a read inhibit operation. Different test excitation is established for different operations supported by the asynchronous memory chip, so that directional test, random test, boundary test and abnormal test are completed, error information is checked through the generated log file, and then corresponding waveforms are opened to track and position specific problems.

And the verification environment layer is used for instantiating an agent, a reference model (reference model) and a comparator (comparator), and all logic components communicate by transmitting data packets through transaction level modeling (Transaction Level Modeling, TLM). A data transmission channel between a first agent (iagent) and a reference model, wherein a transmitted data packet (item) is sent to the reference model to store write data in a memory during a write operation; a data transmission channel between the second agent (oagent) and the comparator, which sends actual data generated by the device under test (Device Under Test, DUT) to the comparator during read operation; simultaneously, the reference model reads out data stored in the writing operation during the reading operation and sends the data to the comparator through a data transmission channel between the reference model and the comparator; the comparator compares the received actual data with the data stored in the writing operation period, the result is the pass, otherwise, relevant error information is printed in the log file, so that an engineer can conveniently and quickly find out the problem, and the bug is tracked and positioned by combining the waveform.

Wherein, the agents are divided into a first agent (iagent) and a second agent (oagent). The first proxy encapsulates components such as a sequence generator (sequence) and a driver (driver), wherein the sequence generator is responsible for connecting a sequence (sequence) with the driver; the driver is responsible for driving the data packets (items) obtained from the sequence onto a virtual interface (virtual interface) according to the write-read time sequence constraint of the parameter configuration file, sending the data packets out through a built-in port (analysis port) of the UVM verification platform, and receiving the signals by the virtual interface and sending the signals to the DUT (device under test). Meanwhile, the second agent and the reference model can also obtain the signals through a UVM built-in port (analysis export), and when the verification platform judges that the equipment to be tested is writing operation, data sent to the equipment to be tested by the writing operation time sequence are stored in a memory of the reference model according to the address information.

The second agent only comprises a monitor component, and the port state of the control signal is sampled at the moment that the sampling period reaches half by monitoring the port signal of the asynchronous memory chip on the virtual interface, so as to judge what working state of the asynchronous memory chip the second agent is in. And for the data output from the chip during the reading operation, sampling by a high-speed clock, storing when sampling is continuously performed for a plurality of times and the sampling is the same, and transmitting the data to the comparator for data comparison at the end time of the sampling period through a built-in port between the second agent and the comparator. The method is characterized in that invalid data exists in the post imitation, the invalid data can be generated when the data is read in the post imitation, and then the valid data is generated at the last moment under the condition of meeting the reading condition, so that the method of continuously collecting the data can be adopted, the last valid data collected can cover the invalid data before the address cycle count is finished, and the invalid data is transmitted.

The comparator defines two data receiving ports, one is used for connecting the data receiving ports defined between the reference model and the comparator, address data corresponding to a memory stored in the reference model are read out in a reading stage, the other is used for connecting the data receiving ports defined between the second agent and the comparator so as to obtain actual data, finally, the two data receiving ports are compared, the result is consistent, pass is obtained, otherwise, related error information is printed in a log file, so that an engineer can conveniently and quickly find out the problem, and the bug is tracked and positioned by combining waveforms.

Referring to fig. 8, the present application further provides an authentication platform for an asynchronous memory chip, including:

the writing function unit is used for writing preset verification data into the storage unit of the equipment to be tested under the condition that the equipment to be tested is in a writing state;

the read verification unit is used for determining that the equipment to be tested is in a read state, and verifying that the data are written into the storage unit of the equipment to be tested, controlling the equipment to be tested to read the data in the storage unit, and sampling the reading result of the equipment to be tested to obtain sampling data;

The application generates a high-speed clock through the top file layer, counts the address period, and the monitor module samples the port state of the control signal at the moment of half sampling period to judge which working state (including writing state/reading state/non-chip selection state/reading invalid state and the like) of the asynchronous chip is in, and realizes the storage and the reading of data according to the monitored working state. And when the read operation is judged, the data output from the chip is sampled through a high-speed clock, and the data is sent to the comparator to realize automatic comparison of the data. The method can also realize the function verification of the post imitation, and as invalid data exists in the post imitation, and invalid data can first appear when the data is read in the post imitation, and then valid data appears at the last moment under the condition of meeting the reading condition, the method of continuously collecting the data can be adopted to cover the invalid data before the last valid data is collected, and the invalid data is transmitted after the address period counting is finished. Therefore, the method can realize the function verification of the large-scale test case of the asynchronous memory chip, and can greatly improve the verification quality and the verification efficiency. As the functional structures of the asynchronous memory chips are similar, the verification platform can be quickly applied to the new type of asynchronous memory chips, and the construction time and the platform debugging time of the verification platform are greatly shortened.

Fig. 9 is a schematic diagram of an asynchronous memory chip verification device/terminal device according to an embodiment of the present application. As shown in fig. 9, the asynchronous memory chip authentication device/terminal apparatus 9 of this embodiment includes: a processor 90, a memory 91 and a computer program 92, such as an asynchronous memory chip authentication program, stored in the memory 91 and executable on the processor 90. The processor 90, when executing the computer program 92, implements the steps of the various asynchronous memory chip verification method embodiments described above, such as steps 101 through 104 shown in fig. 1. Alternatively, the processor 90, when executing the computer program 92, performs the functions of the modules/units of the apparatus embodiments described above, such as the functions of the modules 51 to 54 shown in fig. 5.

Illustratively, the computer program 92 may be partitioned into one or more modules/units that are stored in the memory 91 and executed by the processor 90 to complete the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions describing the execution of the computer program 92 in the asynchronous memory chip authentication device/terminal device 9.

The asynchronous memory chip authentication device/terminal device 9 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The asynchronous memory chip authentication device/terminal device may include, but is not limited to, a processor 90, a memory 91. It will be appreciated by those skilled in the art that fig. 9 is merely an example of an asynchronous memory chip authentication device/terminal device 9 and does not constitute a limitation of the asynchronous memory chip authentication device/terminal device 9, and may include more or less components than illustrated, or may combine some components, or different components, e.g., the asynchronous memory chip authentication device/terminal device may further include an input-output device, a network access device, a bus, etc.

The processor 90 may be a central processing unit (Central Processing Unit, CPU), other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 91 may be an internal storage unit of the asynchronous memory chip authentication device/terminal apparatus 9, for example, a hard disk or a memory of the asynchronous memory chip authentication device/terminal apparatus 9. The memory 91 may also be an external storage device of the asynchronous memory chip authentication device/terminal device 9, such as a plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card) or the like, which are provided on the asynchronous memory chip authentication device/terminal device 9. Further, the memory 91 may also include both an internal memory unit and an external memory device of the asynchronous memory chip authentication device/terminal device 9. The memory 91 is used for storing the computer program and other programs and data required for the asynchronous memory chip authentication device/terminal equipment. The memory 91 may also be used for temporarily storing data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A method for verifying an asynchronous memory chip, comprising:

acquiring the running state of equipment to be tested;

writing preset data into a storage unit of the device to be tested and a reference model under the condition that the device to be tested is in a writing state, and recording a writing address of the data, wherein the reference model is used for simulating the device to be tested;

determining that the equipment to be tested is in a read state, and that the data is written into a storage unit of the equipment to be tested, controlling the reference model to obtain verification data according to a writing address of the data, controlling the equipment to be tested to read the data in the storage unit, and sampling a reading result of the equipment to be tested to obtain sampling data;

and if the sampling data are inconsistent with the verification data, generating information that the verification of the equipment to be tested is not passed.

2. The method of claim 1, wherein writing preset data to the memory cell and the reference model of the device under test with the device under test in a written state comprises:

when the equipment to be tested is in a writing state, writing the preset data into a storage unit of the equipment to be tested according to a first writing and reading time sequence, and writing the preset data into the reference model according to a second writing and reading time sequence.

3. The method of claim 1, wherein prior to acquiring the operational status of the device under test, the method comprises the steps of:

at the falling edge of a high-speed sampling clock, confirming that the high-speed sampling clock completes the sampling period of a preset part, and acquiring a control signal of the equipment to be tested;

and according to the control signal of the equipment to be tested, confirming that the equipment to be tested is in a writing state or a reading state.

4. The method of claim 2, wherein at the falling edge of the high-speed sampling clock, confirming that the high-speed sampling clock completes a sampling period of a preset portion, and obtaining the control signal of the device under test comprises:

generating a sampling counting signal of the high-speed sampling clock, wherein the sampling counting signal is used for recording the sampling times of the high-speed sampling clock in the current sampling period;

confirming that the high-speed sampling clock is at a falling edge;

and confirming that the high-speed sampling clock completes the sampling period of the preset part according to the sampling counting signal and the maximum sampling times preset by the sampling period, and acquiring the control signal of the equipment to be tested.

5. The method of claim 3, wherein controlling the device under test to read the data in the memory cell and sample the read result of the device under test to obtain the sampled data comprises:

sampling output data of the equipment to be tested through the high-speed sampling clock to obtain sampling data;

when N sampling data continuously sampled by the high-speed sampling clock are the same, storing the sampling data;

and confirming that the high-speed sampling clock completes the sampling period, and acquiring the finally stored sampling data.

6. The method according to any one of claims 1 to 5, characterized in that before the acquisition of the operating state of the device under test, the method further comprises the steps of:

and creating different test cases according to the test stimulus, and generating control signals of the equipment to be tested according to the test cases.

7. The method of claim 6, wherein,

8. An authentication platform for an asynchronous memory chip, comprising:

the writing function unit is used for writing preset data into the storage unit of the equipment to be tested and the reference model under the condition that the equipment to be tested is in a writing state, and recording the writing address of the data, wherein the reference model is used for simulating the equipment to be tested;

9. An authentication device for an asynchronous memory chip comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 7 when executing the computer program.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 7.