CN116662006A - Multi-threaded processor renaming resource management method, system, device and medium - Google Patents

Abstract

The invention provides a renaming resource management method, a renaming resource management system, a renaming resource management device and a renaming resource management medium for a multithreading processor, wherein the renaming resource management method comprises the following steps: responding to thread instruction receiving, sequentially carrying out pipeline processing on the thread instruction according to the sequence of instruction fetching decoding, renaming, instruction scheduling and instruction submitting; when a thread instruction enters a renaming stage, a virtual renaming resource number is allocated for the thread instruction in a virtual renaming resource domain, and a resource corresponding mark is added to the virtual renaming resource number; when the thread instruction enters the instruction scheduling stage, judging whether the virtual renaming resource number corresponds to the real renaming resource according to the resource correspondence mark, if so, distributing the real renaming resource number for the thread instruction and scheduling the execution, otherwise, waiting until the virtual renaming resource number is converted into the real renaming resource number and then scheduling the execution. The invention can effectively reduce the probability that the linear instruction in the processor is blocked in the renaming stage due to insufficient renaming resources, and improve the running efficiency of the multithreading processor.

Description

Multi-threaded processor renaming resource management method, system, device and medium

technical field

The invention relates to the technical field of processor design, in particular to a multi-thread processor renaming resource management method, system, device and medium.

Background technique

When the processor is running, insufficient register renaming resources are a common cause of blocking pipeline operation. The way to deal with insufficient resources when renaming registers is generally to block the submission of front-end instructions first, wait for the renaming resources to be ready, and then release the blocked instruction stream. This simple blocking instruction flow processing method will not have a great impact on single-threaded processors with high instruction dependencies, but for multi-threaded processors, when certain types of renaming resources are insufficient, blocking Some threads that do not need this type of renaming resources will inevitably increase the false correlation of instruction processing between different threads, and all thread instructions will be blocked in the renaming pipeline, thereby reducing the operating efficiency of the multi-threaded processor.

Although the existing method of increasing the number of processor renaming resources can effectively reduce the pipeline blocking probability of multi-threaded processors, it will inevitably cause the processor area to be too large, and then introduce the problem of increased difficulty in timing convergence.

Contents of the invention

The purpose of the present invention is to provide a multi-threaded processor renaming resource management method, by setting a virtual renaming resource domain, dynamically manage the renaming resources that are allocated in the renaming stage and will be directly used after this stage, so as to block the pipeline The cycle is delayed to the reserved station, eliminating the false correlation between multi-threaded instructions, solving the application defects of the existing multi-threaded processor renaming resource management method, and reducing the thread instructions in the multi-threaded processor being blocked due to insufficient renaming resources. The probability of front-end pipeline improves the operating efficiency of multi-threaded processors.

In order to achieve the above purpose, it is necessary to provide a multi-threaded processor renaming resource management method and system for the above technical problems.

In the first aspect, the embodiment of the present invention provides a multi-threaded processor renaming resource management method. In response to receiving a thread instruction, the thread instruction is sequentially executed in the order of fetching and decoding, renaming, instruction scheduling, and instruction submission. Pipeline processing, the method includes the following steps:

When the thread instruction enters the renaming stage, assign a corresponding virtual rename resource number to the thread instruction in the preset virtual rename resource field, and add a resource corresponding mark to the virtual rename resource number;

When the thread instruction enters the instruction scheduling phase, judge whether the corresponding virtual renaming resource number corresponds to the real renaming resource according to the corresponding resource corresponding mark, if so, assign the real renaming resource number and schedule for the thread instruction Execute, otherwise, wait until the corresponding virtual rename resource number is converted to a real rename resource number before scheduling execution.

Further, the step of presetting the virtual renaming resource domain includes:

Sets a virtual rename resource domain of a preset size based on the real number of rename resources and the number of reservation station entries for multi-threaded processors.

Further, the resource correspondence mark includes a corresponding real resource and an uncorresponded real resource; the step of adding the resource corresponding mark to the virtual renamed resource number includes:

Acquiring the number of remaining renaming resources in the real renaming resource domain according to the preset resource counter; the counting upper limit of the resource counter is the real renaming resource number of the multi-threaded processor;

When the remaining number of rename resources is zero, set the resource corresponding flag of the virtual rename resource number as not corresponding to a real resource;

When the remaining number of rename resources is not zero, set the resource corresponding flag of the virtual rename resource number to correspond to a real resource.

Further, the step of adding the virtual rename resource number with a resource corresponding mark includes:

When the resource is correspondingly marked as not corresponding to a real resource, generate a corresponding first real resource conversion request and a second real resource conversion request according to the corresponding virtual renaming resource number and thread number respectively;

Writing the first real resource conversion request into the thread sub-first-in-first-out cache corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into the main first-in-first-out cache shared by all thread instructions.

Further, the step of converting the corresponding virtual rename resource number into a real rename resource number includes:

According to the resource counter, obtain the current remaining number of real renaming resources, and when the current remaining number of real renaming resources is not zero, obtain the monitoring information of each thread number; according to the monitoring information of each thread number, obtain the corresponding Real resource conversion priority, and according to the real resource conversion priority of each thread number, at least one thread number to be converted is obtained;

According to the thread number to be converted, the virtual rename resource number to be converted is obtained, and a corresponding real rename resource number is assigned to the virtual rename resource number to be converted;

In response to the allocation of the real rename resource number corresponding to the virtual rename resource number to be converted is completed, the corresponding first real resource conversion request and the second real resource conversion request are cleared.

Further, the monitoring information includes thread priority, the number of thread instructions in the instruction fetching and decoding phase, and the number of first real resource conversion requests in the first-in-first-out cache of the thread sub-cache.

Further, the step of obtaining the corresponding real resource conversion priority according to the monitoring information of each thread includes:

The weighted summation is performed on each piece of monitoring information according to the corresponding preset weight value to obtain the real resource conversion priority.

Further, the step of obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number includes:

Select the maximum value among all real resource conversion priorities, and use the thread number corresponding to the maximum value as the thread number to be converted.

Further, the step of obtaining the virtual renaming resource number to be converted according to the thread number to be converted includes:

When the thread number to be converted is one, read the first real resource conversion request first written in the corresponding thread sub-first-in-first-out cache, and write the first real resource conversion request corresponding to the first real resource conversion request first The rename resource number is used as the virtual rename resource number to be converted;

When there are multiple thread numbers to be converted, read the first written second real resource conversion request corresponding to the thread number to be converted from the main first-in-first-out cache, and write it first The thread number corresponding to the second real resource conversion request is used as the preferred conversion thread number, and the first real resource conversion request written first in the first-in-first-out cache of the thread sub-thread corresponding to the preferred conversion thread number is read, and the first The written virtual rename resource number corresponding to the first real resource conversion request is used as the virtual rename resource number to be converted.

In the second aspect, an embodiment of the present invention provides a resource management system for renaming a multithreaded processor. In response to receiving a thread instruction, the thread instruction is sequentially executed in the order of fetching and decoding, renaming, instruction scheduling, and instruction submission. Pipeline processing, the system includes:

A virtual resource allocation module, configured to assign a corresponding virtual rename resource number to the thread instruction in a preset virtual rename resource field when the thread instruction enters the renaming stage, and allocate the virtual rename resource Add the corresponding mark of the resource to the number;

The real resource conversion module is used to determine whether the corresponding virtual rename resource number has corresponded to the real rename resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, and if so, assign the thread instruction Real rename the resource number and schedule execution, otherwise, wait until the corresponding virtual rename resource number is converted into a real rename resource number before scheduling execution.

In the third aspect, the embodiment of the present invention also provides a multithreaded processor renaming resource management device, the device comprising:

a memory storing executable program code;

an actuator coupled to said memory;

The executor invokes the executable program code stored in the memory to execute the above method steps.

In a fourth aspect, the embodiment of the present invention further provides a computer storage medium, on which computer instructions are stored, and when the computer instructions are invoked, the above method steps are executed.

The above application provides a resource management method, system, device and medium for multi-threaded processor renaming. Through the method, in response to receiving thread instructions, the thread instructions are sequentially followed by fetching and decoding, renaming, and instruction scheduling. Pipeline processing is performed with the order of instruction submission. When the thread instruction enters the renaming stage, the corresponding virtual rename resource number is assigned to the thread instruction in the preset virtual rename resource field, and the virtual rename resource number is added to the resource corresponding mark. And when the thread instruction enters the instruction scheduling stage, judge whether the corresponding virtual renaming resource number corresponds to the real renaming resource according to the corresponding flag of the corresponding resource, if so, assign the real renaming resource number to the thread instruction and schedule execution, otherwise , wait until the corresponding virtual rename resource number is converted into a real rename resource number, and then schedule and execute the technical solution. Compared with the prior art, the multi-threaded processor renaming resource management method dynamically manages the renaming resources allocated in the renaming stage and will be directly used after this stage by setting a virtual renaming resource domain, so as to block the pipeline The cycle is delayed to the reserved station, eliminating the false correlation between multi-threaded instructions, effectively reducing the probability of thread instructions in the multi-threaded processor being blocked in the front-end pipeline due to insufficient renaming resources, improving the operating efficiency of the multi-threaded processor, and then It provides reliable technical support for the efficient operation of multi-threaded processors without increasing the area of the processor or increasing the difficulty of timing convergence.

Description of drawings

Fig. 1 is a schematic diagram of a multi-thread instruction processing flow diagram of an existing multi-thread processor;

Fig. 2 is a schematic diagram of the pipeline processing flow in the renaming stage when the existing renaming resources are insufficient;

3 is a schematic flow diagram of a method for managing resources renaming a multithreaded processor in an embodiment of the present invention;

FIG. 4 is a schematic diagram of a pipeline processing flow for renaming resource management using a multithreaded processor of the present invention;

FIG. 5 is a schematic flow diagram of converting a virtual renaming resource into a real renaming resource in an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a multi-threaded processor renaming resource management system in an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a resource management device for renaming a multithreaded processor in an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and beneficial effects of the present application clearer, the present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. Obviously, the embodiments described below are part of the embodiments of the present invention and are only used for The present invention is illustrated, but not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The multi-threaded processor renaming resource management method provided by the present invention is based on the renaming method shown in FIG. The resource allocation management method will cause other thread instructions that are not related to it to be blocked, which greatly reduces the renaming resource management defect of the multi-threaded processor pipeline efficiency. The renaming resources are only allocated rather than directly used in the naming stage. When the real renaming resources are insufficient, the pipeline blocking cycle is postponed to the effective management method of the real renaming resources in the reservation station of the instruction scheduling stage to effectively eliminate multi-threading. The false correlation between instructions reduces the probability of multi-threaded processors being blocked in the front-end pipeline due to insufficient renaming resources, and reliably improves the pipeline efficiency of multi-threaded processors. The following embodiments will describe in detail the resource management method for multi-threaded processor renaming of the present invention.

In one embodiment, as shown in FIG. 3 , a multi-threaded processor renaming resource management method is provided. In response to receiving a thread instruction, the thread instruction is sequentially followed by fetching and decoding, renaming, instruction scheduling, and instruction The order of submission is pipelined, including the following steps:

In this embodiment, the general pipeline sequence is still used in the pipeline processing process, including four pipeline processing stages: 1) instruction fetching and decoding stage; 2) renaming stage; 3) instruction scheduling stage; 4) instruction submitting stage. For a multi-threaded processor, the thread instructions input in the fetch-decode stage and the rename stage are executed sequentially, and in the instruction scheduling stage, the instructions are dynamically scheduled and executed according to whether the resources required for instruction processing are available, that is, Instructions in the stage will be executed in order from sequential execution to out-of-order execution, so that even if the resources required by the instructions that enter the instruction scheduling stage earlier are not available, the processor can also select instructions that have available resources from the instructions that enter the instruction scheduling stage later. It can be seen that in the instruction scheduling stage, the utilization rate of the processor pipeline is guaranteed to a certain extent by using the out-of-order processing method of non-correlation between instructions, and then the operating efficiency of the multi-thread processor is improved.

Based on the processing characteristics of each stage in the processor pipeline operation mechanism, in order to avoid the disadvantageous effect of lowering the pipeline efficiency caused by sequential processing in the renaming stage as much as possible, and better utilize the out-of-order processing in the instruction scheduling stage to improve pipeline utilization. advantage effect, and then further improve the operating efficiency of the multi-threaded processor, this embodiment is preferred, on the basis of continuing to use the existing processor pipeline processing timing, by adding a virtual rename resource domain as shown in Figure 4, combined with the counterweight The processing optimization of the naming stage and the instruction scheduling stage simply and reliably solves the problem of false correlation between low-correlation instructions of different threads caused by the blocking of the existing renaming stage, so as to truly realize the renaming of each renaming resource in the real renaming resource domain Efficient and reliable allocation management.

S11. When the thread instruction enters the renaming stage, assign a corresponding virtual rename resource number to the thread instruction in the preset virtual rename resource field, and add a resource corresponding mark to the virtual rename resource number ; Among them, the virtual renaming resource field can be understood as a set of virtual resources that are used to replace the real renaming resource field in advance, and realize the functions required by the real renaming resource field that are only allocated but not used in the renaming stage. In order to avoid the disadvantageous effect of lowering the pipeline efficiency caused by sequential processing in the renaming stage, in principle, the size of the virtual renaming resource field only needs to be larger than the real renaming resource field to meet the requirements to reduce the probability of pipeline blocking in the renaming stage to a certain extent. However, considering the limitations of the processing performance of each stage of the actual processor pipeline, in order to effectively reduce the blocking probability of the front-end pipeline without reducing the processing performance of each stage of the pipeline, this embodiment is preferably in the case where the storage performance of the instruction scheduling stage can support Next, increase the size of the virtual renaming resource domain as much as possible; specifically, the steps for setting the virtual renaming resource domain in advance include:

According to the number of real renaming resources and the number of reservation station entries of the multi-threaded processor, a virtual renaming resource domain with a preset size is set; among them, the reservation station is understood as the storage structure used to store instruction information in the instruction scheduling stage. In practical applications, when the instruction operand or the renaming resource is not ready, the instruction information will stay in the reservation station and wait until it meets the instruction scheduling condition and is scheduled to be executed before being moved out; The size is set to meet the application requirements of the above analysis as much as possible, and the optimal setting is the sum of the number of reserved station entries and the actual number of resources to be renamed.

The above resource corresponding flag can be understood as a record of whether the real renaming resource in the real renaming resource domain can be used when the thread instruction processing enters the instruction renaming stage and the virtual renaming resource number is assigned; Correspondingly, the resource corresponding flag includes the corresponding real resource and the uncorresponding real resource, wherein, the corresponding real resource can be understood as the thread instruction currently entering the renaming stage, while assigning the number of the virtual renaming resource, the real renaming resource There are also real renaming resources available in the domain, which can be directly scheduled and executed in the instruction scheduling stage; similarly, the uncorresponding real resources can be understood as the thread instruction currently entering the renaming stage is assigned the virtual renaming resource number At the same time, there is no real renaming resource available in the real renaming resource domain, and it needs to be scheduled and executed after the real renaming resource that is released is dynamically scheduled and allocated in the real renaming resource domain; It is a key mark to effectively manage the real rename resource domain in conjunction with the virtual rename resource domain. The resource corresponding mark of each virtual rename resource number is accurately recorded; specifically, the step of adding the resource corresponding mark to the virtual rename resource number includes:

Acquiring the number of remaining renaming resources in the real renaming resource domain according to the preset resource counter; the counting upper limit of the resource counter is the real renaming resource number of the multi-threaded processor;

When the remaining number of rename resources is zero, set the resource corresponding flag of the virtual rename resource number as not corresponding to a real resource;

When the remaining number of rename resources is not zero, set the resource corresponding flag of the virtual rename resource number to correspond to a real resource.

In practical applications, in principle, after the resource corresponding mark of the virtual renaming resource number of each thread instruction is accurately recorded through the above method steps, the corresponding resource corresponding mark can be queried in the instruction scheduling stage, according to a certain The dynamic management rules dynamically allocate real renaming resources, but considering that all instructions of all threads are assigned to the virtual renaming resource domain in sequence according to the time sequence of entering the renaming stage, regardless of the threads when entering the renaming stage The resource number of the real renaming resource may not be allocated, but in the subsequent instruction scheduling stage, the instruction needs to be allocated real renaming resources before it can be scheduled and executed. In order to facilitate the instruction scheduling stage to effectively perceive which thread instructions do not correspond to the real renaming Resources, and when there are many instructions that do not correspond to real renaming resources at the same time, it is possible to effectively and reasonably allocate virtual resources that do not correspond to real renaming resources while not losing multi-thread processing efficiency and following the existing pipeline work sequence. The renaming resource is converted into a real renaming resource, which provides a reliable guarantee for the efficient and reliable processing of each thread instruction in the multi-threaded processor. In this embodiment, preferably, by setting all thread instructions to be shared, all renaming is recorded according to the sequence of instruction input. The main first-in-first-out cache of the thread number of the instruction that does not correspond to the real rename resource in the stage, and simultaneously set up multiple thread sub-first-in first-out caches that correspond to each thread and record the virtual rename resource number of a single thread instruction according to the timing of instruction input Maintain each virtual renaming resource that does not correspond to the corresponding real renaming resource, and provide a reliable basis for dynamically screening out the threads that give priority to real renaming resources and the corresponding virtual renaming resource numbers in the instruction scheduling stage;

Specifically, as shown in FIG. 5, the step of adding the virtual rename resource number to the resource corresponding mark includes:

When the resource is correspondingly marked as not corresponding to a real resource, generate a corresponding first real resource conversion request and a second real resource conversion request according to the corresponding virtual renaming resource number and thread number respectively;

Writing the first real resource conversion request into the thread sub-first-in-first-out cache corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into the main first-in-first-out cache shared by all thread instructions; wherein , the number of thread sub-FIFO caches is the same as the total number of threads running in the processor, and the size of each thread sub-FIFO cache is consistent with the total number of entries supported by the reservation station; at the same time, the main FIFO cache The size is also consistent with the total number of entries backed by the reservation station.

S12. When the thread instruction enters the instruction scheduling stage, judge whether the corresponding virtual rename resource number corresponds to the real rename resource according to the corresponding resource corresponding flag, and if so, assign the real rename resource number to the thread instruction And schedule execution, otherwise, wait until the corresponding virtual rename resource number is converted into a real rename resource number before scheduling execution;

In practical applications, when the thread instruction processing enters the instruction scheduling stage, it will check whether the resource corresponding to the assigned virtual rename resource number corresponds to the corresponding real rename resource: if so, it is determined that the instruction can be scheduled for execution, And assign the real renaming resource number to it during scheduling execution; if not, it is determined that the instruction needs to wait for the real renaming resource to be allocated in the scheduling stage before it can be executed. Therefore, how to dynamically allocate real renaming resources according to the information recorded in the aforementioned main FIFO cache and each thread sub-FIFO cache will directly affect the operating efficiency of the multi-threaded processor.

Considering that the correlation of instructions of different threads in a multi-threaded processor is low, if the requests are only converted (allocated real renaming resources) according to the order in which the instructions generate conversion requests, it will cause false correlations between instructions of different threads In the event that the efficiency of the multi-threaded processor is damaged, this embodiment preferably monitors the relevant thread information that may affect the timeliness of instruction processing in real time, and when there are real renaming resources available, the obtained information of each thread The monitoring information is used as the scheduling basis for the real resource conversion request of each thread, and the virtual rename resource is converted into a real rename resource in a timely and reasonable manner; specifically, as shown in Figure 5, the corresponding virtual rename resource number is converted into The steps to actually rename a resource number include:

According to the resource counter, obtain the current remaining number of real renaming resources, and when the current remaining number of real renaming resources is not zero, obtain the monitoring information of each thread number; according to the monitoring information of each thread number, obtain the corresponding Real resource conversion priority, and according to the real resource conversion priority of each thread number, at least one thread number to be converted is obtained; among them, the monitoring information can be set according to the actual operation requirements of different multi-threaded processors. In principle, the more relevant information is collected, the more more, the more reliable the scheduling basis obtained based on the monitoring information is, but considering that the collection of monitoring information will occupy additional processor resources, in order to achieve a balance between the effectiveness of the scheduling basis and the occupancy of processor resources, the preferred monitoring information in this embodiment includes Thread priority, the number of thread instructions in the fetching and decoding phase, and the number of first real resource conversion requests in the first-in-first-out cache of the thread sub-cache;

At the same time, considering that each monitoring information has different influences on the priority of instruction processing, how to make reasonable use of each monitoring information will directly affect the reliability of the real resource conversion priority of each thread, and then affect the real renaming resource dynamics of the processor. The rationality of allocation, in order to have different influences on each monitoring information as much as possible in the calculation of real resource conversion priority, this implementation preferably assigns corresponding weights according to the influence of each monitoring information on the timeliness of instruction processing and combines them to obtain the corresponding real Resource conversion priority; specifically, the step of obtaining the corresponding real resource conversion priority according to the monitoring information of each thread includes:

Each monitoring information is weighted and summed according to the corresponding preset weight value to obtain the real resource conversion priority; wherein, the detailed process of calculating the real resource conversion priority can be realized by referring to the following example: For example, each thread sub-first-in The effective number of entries in the first-out cache is the number to be converted by each thread, and the preset weight value of such monitoring information can be set to 1; the instructions of each thread in the instruction fetching and decoding stage are instructions that are about to enter the renaming stage , the preset weight value of such monitoring information can be set to 0.4; the priority of each thread in the processor can be dynamically set according to high, medium, and low levels, and the corresponding preset weight values are assigned to 3, 2, and 1. Finally, accumulate the calculated priorities of various monitoring information of each thread; if thread 0 has a high priority, the number of requests to be converted in the first-in-first-out cache of the thread is x, and the fetching and decoding stage The number of instructions belonging to thread 0 is y, and the calculated real resource conversion priority of thread 0 is 3+x+0.4y; it should be noted that the preset weight values of various monitoring information in the above calculation process are only set It is an exemplary description, and may be preferably set according to actual conditions in actual applications, and no specific limitation is made here.

In addition, in order to meet the timeliness requirements of each thread instruction processing on the basis of following the timing of each thread instruction input as much as possible, and thus effectively ensure the high efficiency of the operation of the multi-thread processor, in this embodiment, preferably, when the processor When there is a real resource conversion request and there are remaining real renaming resources available in the real renaming resource domain, the processor will perform priority conversion on a thread with the highest conversion priority; specifically, the real resource conversion priority according to each thread number Level, the step of obtaining at least one thread number to be converted includes:

Select the maximum value among all real resource conversion priorities, and use the thread number corresponding to the maximum value as the thread number to be converted.

According to the thread number to be converted, the virtual rename resource number to be converted is obtained, and the corresponding real rename resource number is allocated for the virtual rename resource number to be converted; wherein, the thread number to be converted is based on each thread as shown above The maximum value of the corresponding real resource conversion priority sorting is determined, but in practical applications, it is very likely that several threads have the highest real resource conversion priority at a certain moment, then the filtered thread number to be converted is If there is more than one, it is necessary to introduce other selection basis to further determine the final preferred conversion thread number, and then determine the priority conversion request according to the preferred conversion thread number; based on the diversity of actual dynamic allocation of real renaming resource application scenarios, in order to ensure For the efficiency and accuracy of priority conversion request scheduling, in this embodiment, preferably, different priority conversion request scheduling schemes are set for different application scenarios with one or more thread numbers to be converted; specifically, according to the The steps for obtaining the number of the virtual rename resource to be converted for the thread number to be converted include:

When the thread number to be converted is one, read the first real resource conversion request first written in the corresponding thread sub-first-in-first-out cache, and write the first real resource conversion request corresponding to the first real resource conversion request first The rename resource number is used as the virtual rename resource number to be converted; it should be noted that when the thread number to be converted is one, the corresponding thread sub-first-in-first-out cache can be directly read directly according to the thread number to be converted, and the This thread reads out the conversion request at the top of the first-in-first-in cache (the oldest first real resource conversion request that was first written into the cache), and assigns a real resource number for renaming to realize the virtual rename corresponding to the request. The mapping between the named resource number and the real rename resource number provides preparation for the subsequent instruction scheduling execution;

When there are multiple thread numbers to be converted, read the first written second real resource conversion request corresponding to the thread number to be converted from the main first-in-first-out cache, and write it first The thread number corresponding to the second real resource conversion request is used as the preferred conversion thread number, and the first real resource conversion request written first in the first-in-first-out cache of the thread sub-thread corresponding to the preferred conversion thread number is read, and the first The number of the virtual rename resource corresponding to the written first real resource conversion request is used as the number of the virtual rename resource to be converted; it should be noted that when there are multiple thread numbers to be converted, each thread number to be converted needs to be divided into Match the thread numbers written in time sequence in the main FIFO cache, find the oldest second real resource conversion request written first corresponding to one of the thread numbers to be converted, and then read the second real resource conversion request The thread number in the real resource conversion request is used as the preferred conversion thread number, and the corresponding thread sub-first-in-first-out cache is read according to the preferred thread number pair, and the oldest real resource conversion first written in the cache is obtained request, and allocate the real rename resource number to it, realize the mapping between the virtual rename resource number corresponding to the request and the real rename resource number, and provide preparation for the subsequent instruction scheduling execution; for example, from the top The record to the top is "Thread 1, Thread 2, Thread 1, Thread 3, Thread 2", and the threads to be converted are Thread 2 and Thread 3, then the first written conversion request screened out from the main FIFO cache at this time is The content is the second real resource conversion request of "Thread 2". Read this request to get the corresponding preferred conversion thread number (Thread 2), and then read the first resource at the top of the first-in-first-out cache corresponding to Thread 2. The written first real resource conversion request obtains the virtual rename resource number (for example, 15) that needs to be converted, then it is the real rename resource number corresponding to the virtual rename resource number (15).

In response to the allocation of the real rename resource number corresponding to the virtual rename resource number to be converted is completed, clear the corresponding first real resource conversion request and the second real resource conversion request;

In this example, after realizing the effective conversion between the above-mentioned virtual rename resource and real rename resource, the filtered first real resource conversion request is cleared from the thread sub-FIFO cache, and the primary FIFO cache record The thread's oldest second real resource conversion request is also deleted in time to avoid invalid occupation of cache resources and effectively ensure the efficiency and reliability of subsequent real resource renaming resource dynamic allocation management.

In the embodiment of the present application, in response to the receipt of the thread instruction, the thread instruction is sequentially processed in the order of fetching and decoding, renaming, instruction scheduling, and instruction submission. When the thread instruction enters the renaming stage, the preset virtual rename In the naming resource field, assign the corresponding virtual renaming resource number to the thread instruction, add the resource corresponding mark to the virtual renaming resource number, and judge the corresponding virtual renaming resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage Whether the number corresponds to the real rename resource, if so, assign the real rename resource number to the thread instruction and schedule execution, otherwise, wait until the corresponding virtual rename resource number is converted into a real rename resource number and then schedule execution The solution, by setting the virtual renaming resource domain, dynamically manages the renaming resources that are allocated in the renaming stage and will be used directly after this stage, which not only reduces the probability of blocking instructions in the renaming stage, but also eliminates the lack of renaming resources. The impact of the delay is delayed to the instruction scheduling stage, which eliminates the false correlation between multi-threaded instructions, improves the utilization rate of the multi-threaded processor pipeline, and can take into account the multi-threaded processing when the virtual renaming resource is converted into a real renaming resource. The historical information between each thread instruction of the processor, the historical information among multiple threads, and the thread priority information, and the dynamic scheduling of real renaming resources are based on the validity guarantee and processor resource occupation. Reasonable balance, improve the performance of multi-threaded processors Operating efficiency, and then provide reliable technical support for the efficient operation of multi-threaded processors without increasing the area of the processor or increasing the difficulty of timing convergence.

It should be noted that although the various steps in the above flow chart are displayed sequentially according to the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders.

In one embodiment, as shown in FIG. 6 , a multithreaded processor renaming resource management system is provided. In response to receiving a thread instruction, the thread instruction is sequentially followed by instruction fetching and decoding, renaming, instruction scheduling, and instruction The order of submission is pipelined, and the system includes:

The virtual resource allocation module 1 is configured to assign a corresponding virtual rename resource number to the thread instruction in a preset virtual rename resource field when the thread instruction enters the renaming stage, and assign the virtual rename resource number to the virtual rename resource. A resource corresponding mark is added to the resource number; the resource corresponding mark includes a corresponding real resource and an uncorresponding real resource;

The real resource conversion module 2 is used to determine whether the corresponding virtual rename resource number corresponds to the real rename resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, and if so, it is the thread instruction Assign a real rename resource number and schedule execution, otherwise, wait until the corresponding virtual rename resource number is converted into a real rename resource number before scheduling execution.

For specific limitations on a multi-threaded processor renaming resource management system, refer to the above-mentioned limitation on a multi-threaded processor renaming resource management method, and the corresponding technical effects can also be obtained equally, and will not be repeated here. Each module in the above-mentioned multi-threaded processor renaming resource management system can be fully or partially realized by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory of the computer device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.

In one embodiment, as shown in FIG. 7 , a resource management device for renaming a multithreaded processor is provided, including: a memory storing executable program code; an executor coupled to the memory; the executor calls the executable code stored in the memory. The above method steps are executed when the program code is executed.

In one embodiment, a computer storage medium is provided, on which computer instructions are stored, and the above method steps are executed when the computer instructions are called.

To sum up, the embodiment of the present invention provides a multi-thread processor renaming resource management method, system, device, and medium. The multi-thread processor renaming resource management method realizes that thread commands are sequentially fetched in response to receiving thread commands. Refers to the sequence of decoding, renaming, instruction scheduling, and instruction submission for pipeline processing. When a thread instruction enters the renaming stage, the corresponding virtual renaming resource number is assigned to the thread instruction in the preset virtual renaming resource field, and the virtual Rename the resource number to add the resource corresponding mark, and when the thread instruction enters the instruction scheduling stage, according to the corresponding resource corresponding mark, judge whether the corresponding virtual rename resource number has corresponded to the real rename resource, and if so, assign the real resource to the thread instruction Rename the resource number and schedule execution, otherwise, wait until the corresponding virtual rename resource number is converted into a real rename resource number and then schedule the technical solution for execution. This method dynamically manages renaming by setting the virtual rename resource field. The renaming resources that are allocated in the stage and will be used directly after this stage delay the pipeline blocking cycle to the reservation station, eliminate the false correlation between multi-threaded instructions, and effectively reduce the renaming resources caused by thread instructions in multi-threaded processors. The probability of being blocked in the front-end pipeline due to insufficient resources improves the utilization rate of the multi-threaded processor pipeline, and can take into account the historical information between each thread instruction of the multi-threaded processor when the virtual renaming resource is converted into a real renaming resource , the historical information among multiple threads and the thread priority information, the dynamic scheduling of the real renaming resources is based on the validity guarantee and the processor resource occupation to make a reasonable balance, improve the operating efficiency of the multi-threaded processor, and then do not increase the processor area , While not increasing the difficulty of timing convergence, it provides reliable technical support for the efficient operation of multi-threaded processors.

Each embodiment in this specification is described in a progressive manner, and the same or similar parts of each embodiment can be directly referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment. It should be noted that the various technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of concise description, all possible combinations of the various technical features in the above-mentioned embodiments are not described. Where there is a contradiction, all should be deemed to be within the scope of this specification.

The above-mentioned embodiments only express several preferred implementation modes of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several improvements and substitutions without departing from the technical principle of the present invention, and these improvements and substitutions should also be regarded as the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the scope of protection of the claims.

Claims (12)

1. A method for renaming resources in a multithreaded processor, responsive to receipt of a thread instruction, for pipelining the thread instruction sequentially in the order of instruction fetch decoding, renaming, instruction scheduling, and instruction submission, the method comprising the steps of:

when the thread instruction enters a renaming stage, distributing a corresponding virtual renaming resource number for the thread instruction in a preset virtual renaming resource domain, and adding a resource corresponding mark to the virtual renaming resource number;

when the thread instruction enters an instruction scheduling stage, judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.

2. The method of claim 1, wherein the step of pre-setting a virtual rename resource domain comprises:

and setting a virtual renaming resource domain with a preset size according to the real renaming resource number and the reservation station entry number of the multithreading processor.

3. The multi-threaded processor renaming resource management method of claim 1 wherein the resource correspondence indicia includes corresponding real resources and non-corresponding real resources; the step of adding the virtual renamed resource number with a resource corresponding mark comprises the following steps:

obtaining the number of remaining renamed resources in the true renamed resource domain according to a preset resource counter; the upper limit of the count of the resource counter is the real renamed resource number of the multithreaded processor;

when the number of the remaining renamed resources is zero, setting the resource corresponding mark of the virtual renamed resource number as a real resource which is not corresponding to the virtual renamed resource number;

and when the number of the remaining renamed resources is not zero, setting the resource corresponding mark of the virtual renamed resource number as the corresponding real resource.

4. The method of claim 3, wherein the step of adding a resource correspondence tag to the virtual rename resource number comprises:

when the resource corresponding mark is not corresponding to the real resource, respectively generating a corresponding first real resource conversion request and a corresponding second real resource conversion request according to the corresponding virtual renamed resource number and thread number;

And writing the first real resource conversion request into a thread sub first-in first-out buffer memory corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into a main first-in first-out buffer memory shared by all thread instructions.

5. The method of claim 4, wherein the step of converting the corresponding virtual rename resource number to a real rename resource number comprises:

acquiring the current residual real renamed resource number according to the resource counter, and acquiring monitoring information of each thread number when the current residual real renamed resource number is not zero; obtaining corresponding real resource conversion priority according to the monitoring information of each thread number, and obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number;

obtaining a virtual rename resource number to be converted according to the thread number to be converted, and distributing a corresponding real rename resource number for the virtual rename resource number to be converted;

and responding to the completion of the allocation of the real renamed resource numbers corresponding to the virtual renamed resource numbers to be converted, and clearing the corresponding first real resource conversion request and second real resource conversion request.

6. The method of claim 5, wherein the monitoring information includes thread priority, a number of thread instructions to fetch a decode stage, and a first real resource translation request number of a thread child first-in-first-out cache.

7. The method of claim 5, wherein the step of obtaining the corresponding real resource conversion priority based on the monitoring information of each thread comprises:

and carrying out weighted summation on each monitoring information according to the corresponding preset weight value to obtain the real resource conversion priority.

8. The method of claim 5, wherein the step of obtaining at least one thread number to be translated based on real resource translation priorities of respective thread numbers comprises:

and selecting the maximum value in all the real resource conversion priorities, and taking the thread number corresponding to the maximum value as the thread number to be converted.

9. The method of claim 5, wherein the step of obtaining a virtual rename resource number to be converted from the thread number to be converted comprises:

When the thread number to be converted is one, reading a first real resource conversion request written first in a corresponding thread sub first-in first-out buffer memory, and taking a virtual rename resource number corresponding to the first real resource conversion request written first as the virtual rename resource number to be converted;

when the number of the threads to be converted is multiple, reading a first written second real resource conversion request corresponding to the threads to be converted from the main first-in first-out buffer memory, taking the thread number corresponding to the first written second real resource conversion request as a preferred conversion thread number, reading a first real resource conversion request which is written first in the thread sub first-in first-out buffer memory corresponding to the preferred conversion thread number, and taking a virtual renaming resource number corresponding to the first real resource conversion request which is written first as the virtual renaming resource number to be converted.

10. A multithreaded processor renaming resource management system for sequentially pipelining thread instructions in the order of instruction fetch decoding, renaming, instruction scheduling, and instruction submission in response to thread instruction receipt, the system comprising:

The virtual resource allocation module is used for allocating corresponding virtual renaming resource numbers for the thread instructions in a preset virtual renaming resource domain when the thread instructions enter a renaming stage, and adding resource corresponding marks to the virtual renaming resource numbers;

and the real resource conversion module is used for judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.

11. A multi-threaded processor renaming resource management device, the device comprising:

a memory storing executable program code;

an actuator coupled to the memory;

the executor invoking the executable program code stored in the memory to perform the multi-threaded processor renaming resource management method of any of claims 1-9.

12. A computer storage medium having stored thereon computer instructions which, when invoked, perform the multi-threaded processor renaming resource management method of any of claims 1-9.