CN116627871A - A signal transmission circuit, computing equipment and storage backplane - Google Patents

Abstract

The embodiment of the application discloses a signal transmission circuit, a computing device and a storage backboard, wherein the signal transmission circuit comprises a first circuit board, a first storage backboard and a second storage backboard, the first circuit board comprises a first expansion interface, the first storage backboard comprises a first upstream interface and a first downstream interface, the first upstream interface is connected with the first downstream interface, the second storage backboard comprises a second upstream interface, and the first upstream interface is connected with the first expansion interface; the second upstream interface is connected with the first downstream interface, or the first circuit board further comprises a second expansion interface, and the second upstream interface is connected with the first downstream interface and the second expansion interface respectively. The embodiment of the application can reduce the wiring difficulty of the main board, save hardware resources and improve the flexibility of expansion of the storage backboard.

Description

A signal transmission circuit, computing equipment and storage backplane

technical field

The present application relates to the field of computer technology, in particular to a signal transmission circuit, computing equipment and a storage backplane.

Background technique

With the advancement of computer technology, the functions and performance of servers are also continuously improved and improved, and they are also playing an increasingly important role in cloud computing, data centers, big data and other fields. In order to meet the growing demand for data storage, the requirements for server storage capacity are also increasing. At the same time, in order to meet the storage requirements of different storage capacities, the server is usually required to support flexible expansion of the storage capacity.

Generally, one or more expansion interfaces are reserved on the motherboard of the server, and the one or more expansion interfaces can be used to connect different storage subsystems (such as storage backplanes) to expand the storage capacity of the server. Since a set of expansion interfaces can be connected to a storage backplane, for a designed motherboard, if the number of expansion interfaces reserved on it is too small, the expansion requirements of the storage backplane cannot be met. However, if too many extended interfaces are reserved on it, resources will be wasted.

Contents of the invention

The embodiment of the present application discloses a signal transmission circuit, a computing device and a storage backplane, which can reduce the difficulty of mainboard wiring, save hardware resources, and improve the flexibility of storage backplane expansion.

The first aspect discloses a signal transmission circuit, the signal transmission circuit includes a first circuit board, a first storage backplane and a second storage backplane; the first circuit board includes a first expansion interface; the first storage backplane includes A first upstream interface and a first downstream interface, the first upstream interface is connected to the first downstream interface; the second storage backplane includes a second upstream interface; the first upstream interface is connected to the first expansion interface; the second Two upstream interfaces are connected to the first downstream interface, or the first circuit board further includes a second expansion interface, and the second upstream interface is respectively connected to the first downstream interface and the second expansion interface.

In this embodiment of the present application, the first storage backplane may include a first upstream interface and a first downstream interface, and the first downstream interface may be connected to the first downstream interface. Based on this, the second upstream interface of the second storage backplane can be connected to the first downstream interface of the first storage backplane, and the cascade transmission of signals can be realized. The expansion interface is reserved on the board, which can reduce the number of reserved expansion interfaces, thereby reducing the difficulty of wiring the main board and saving hardware resources. Moreover, in this way, the expansion of the storage backplane is not limited by the number of expansion interfaces, and the type and type of reserved connectors, etc., which can meet more storage backplane expansion scenarios. The flexibility of storage backplane expansion can be improved.

As a possible implementation manner, the signal transmission circuit further includes a third storage backplane, where the third storage backplane includes a third upstream interface; the second storage backplane further includes a second downstream interface; the third upstream interface connected to the second downstream interface, or, the first circuit board further includes a third expansion interface, and the third upstream interface is respectively connected to the second downstream interface and the third expansion interface.

In this embodiment of the application, when the second storage backplane includes a downstream interface, the third storage backplane can also perform cascade expansion based on the downstream interface of the second storage backplane, and may not depend on or partially depend on the first circuit board In this way, the flexibility of storage backplane expansion can be further improved.

As a possible implementation, the first expansion interface includes a first high-speed signal interface, a first management signal interface, and a first power signal interface; the second expansion interface includes a second high-speed signal interface, a second management signal interface, and a second At least one of the power signal interfaces; the first upstream interface and the second upstream interface both include a high-speed signal interface, a management signal interface, and a power signal interface, and the first downstream interface includes a high-speed signal interface, a management signal interface, and a power signal interface at least one of

The high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface are respectively connected to the first high-speed signal interface, the first management signal interface and the first power signal interface of the first expansion interface;

If the first downstream interface includes a high-speed signal interface, a management signal interface, and a power signal interface, the high-speed signal interface, the management signal interface, and the power signal interface in the first downstream interface are respectively connected to the high-speed signal interface and the management signal interface in the first upstream interface. Correspondingly connected to the power signal interface, the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface;

If the first downstream interface includes any one or any two of a high-speed signal interface, a management signal interface, and a power signal interface, any one or any two of the first downstream interfaces are respectively connected to the high-speed signal interface in the first upstream interface. The corresponding one or two of the signal interface, the management signal interface and the power signal interface, and the corresponding one or two of the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface are connected, and the second The rest of the upstream interfaces are correspondingly connected to corresponding interfaces of the second high-speed signal interface, the second management signal interface and the second power signal interface of the second extension interface.

In this embodiment of the present application, the downstream interface of the first storage backplane may include at least one of a high-speed signal interface, a management signal interface, and a power signal interface. That is to say, the first downstream interface may include seven situations, namely: only Including high-speed signal interface, only including management signal interface, including only power signal interface, including both high-speed signal interface and management signal interface, including both management signal interface and power signal interface, including both high-speed signal interface and power signal interface, including high-speed Signal interface, management signal interface and power signal interface. Based on these seven different situations, the connections between the first downstream interface and the second upstream interface may be different. If the first downstream interface includes a certain signal interface (such as a power signal interface), the signal interface can be connected to the corresponding signal interface in the second upstream interface, if the first downstream interface does not include a certain signal interface (such as a high-speed signal interface) , the signal interface may be connected to a corresponding signal interface in the second extension interface. It can be seen that in an actual scenario, the setting of the downstream interface of the storage backplane includes various situations, and the flexibility is high. In the embodiment of the present application, the first downstream interface may include a management signal interface and a power signal interface at the same time, which can reduce the reservation of the management signal interface and the power signal interface on the first circuit board, thereby reducing the difficulty of wiring the main board. Moreover, in this manner, the transmission of high-speed signals can be based on the second expansion interface on the first circuit board, which can ensure the efficiency of high-speed signal transmission.

As a possible implementation manner, the first expansion interface includes a first high-speed signal interface, a first management signal interface, and a first power signal interface; the second expansion interface includes a second high-speed signal interface, a second management signal interface, and At least one of the second power signal interface; the first upstream interface and the second upstream interface both include a high-speed signal interface, a management signal interface, and a power signal interface, and the first downstream interface includes a high-speed signal interface, a management signal interface, and a power supply At least one of the signal interfaces; the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface are respectively connected with the first high-speed signal interface, the first management signal interface and the first power signal interface of the first expansion interface connection; if the first downstream interface includes a high-speed signal interface, the high-speed signal interface in the first downstream interface is connected to the high-speed signal interface in the first upstream interface, and the high-speed signal interface in the first downstream interface is also connected to the first The high-speed signal interface in the second upstream interface is connected; if the first downstream interface does not include a high-speed signal interface, the high-speed signal interface in the second upstream interface is connected to the second high-speed signal interface of the second expansion interface; if the first The downstream interface includes a management signal interface, and the management signal interface in the first downstream interface is connected to the management signal interface in the first upstream interface; the management signal interface in the first downstream interface is also connected to the management signal interface in the second upstream interface. Signal interface connection; if the first downstream interface does not include a management signal interface, the management signal interface in the second upstream interface is connected to the second management signal interface of the second expansion interface; if the first downstream interface includes a power signal interface , the power signal interface in the first downstream interface is connected to the power signal interface in the first upstream interface; the power signal interface in the first downstream interface is also connected to the power signal interface in the second upstream interface; if the The first downstream interface does not include a power signal interface, and the power signal interface of the second upstream interface is connected to the second power signal interface of the second extension interface.

In this embodiment of the present application, the downstream interface of the first storage backplane may include at least one of a high-speed signal interface, a management signal interface, and a power signal interface. That is to say, the first downstream interface may include seven situations, namely: only Including high-speed signal interface, only including management signal interface, including only power signal interface, including both high-speed signal interface and management signal interface, including both management signal interface and power signal interface, including both high-speed signal interface and power signal interface, including high-speed Signal interface, management signal interface and power signal interface. Based on these seven different situations, the connections between the first downstream interface and the second upstream interface may be different. If the first downstream interface includes a certain signal interface (such as a power signal interface), the signal interface can be connected to the corresponding signal interface in the second upstream interface, if the first downstream interface does not include a certain signal interface (such as a high-speed signal interface) , the signal interface may be connected to a corresponding signal interface in the second extension interface. It can be seen that in an actual scenario, the setting of the downstream interface of the storage backplane includes various situations, and the flexibility is high.

As a possible implementation manner, the first storage backplane further includes an extension chip, the extension chip includes an upstream interface and a downstream interface, and the high-speed signal interface in the first upstream interface is connected to the upstream interface of the extension chip; if the The first downstream interface includes a high-speed signal interface, the extension chip includes at least two downstream interfaces, one of the downstream interfaces of the extension chip is connected to the high-speed signal interface in the first downstream interface, and the remaining downstream interfaces of the extension chip are connected to the first downstream interface. connected to a storage interface of a storage backplane; if the first downstream interface does not include a high-speed signal interface, the downstream interface of the expansion chip is connected to the storage interface of the first storage backplane; the storage interface is used to connect to a storage disk.

In the embodiment of the present application, when the number of high-speed signal channels corresponding to the high-speed signal interface in the first upstream interface is insufficient, the number of high-speed signal channels can be expanded through an expansion chip, so as to support cascading of storage backplanes or storage disks.

As a possible implementation manner, the first storage backplane further includes a backplane controller, and if the first downstream interface includes a management signal interface, the backplane controller is connected to the management signal interface of the first upstream interface, The backplane controller is also connected to the management signal interface in the first downstream interface.

In the embodiment of the present application, the cascading of management signal lines (such as management bus, single-ended signal lines, etc.) normal access. In some embodiments, the backplane controller can forward data (for example, I2C data, JTAG data, etc.), exchange information between upper and lower backplanes, etc., so as to ensure cascade communication between storage backplanes.

As a possible implementation manner, the first storage backplane further includes a voltage adjustment module, the power signal interface in the first upstream interface is connected to the input end of the voltage adjustment module, and the output end of the voltage adjustment module Used to supply power to components on the first storage backplane.

In this embodiment of the present application, the input terminal of the voltage adjustment module of the first storage backplane can be connected to the power signal interface of the first upstream interface, so that the voltage adjustment module can convert the input voltage into The supply voltage required by the components on the board.

As a possible implementation manner, the first high-speed signal interface of the first circuit board further includes a peripheral component interconnect express (PCIe) interface, and the PCIe interface is used for connecting a PCIe device.

In the embodiment of the present application, since the PCIe device may include a high-speed signal interface, and the first circuit board may be provided with a PCIe interface, therefore, in some cases, when the PCIe device is connected to the PCIe interface provided on the first circuit board, the second A high-speed signal interface of a circuit board may be a high-speed signal interface of the PCIe device. It can be seen that based on the PCIe interface and the PCIe device, the flexibility of storage backplane expansion can be further improved.

As a possible implementation manner, the PCIe device is a redundant array of independent disks card.

As a possible implementation manner, the second downstream interface includes at least one of a high-speed signal interface, a management signal interface, and a power signal interface; if the second downstream interface includes a high-speed signal interface, the high-speed signal in the second downstream interface The interface is connected to the high-speed signal interface in the second upstream interface; if the second downstream interface includes a management signal interface, the management signal interface in the second downstream interface is connected to the management signal interface in the second upstream interface; if the The second downstream interface includes a power signal interface, and the power signal interface in the second downstream interface is connected to the power signal interface in the second upstream interface.

The second aspect discloses a computing device, and the computing device includes the signal transmission circuit provided in the above first aspect and any possible implementation manner of the first aspect.

The third aspect discloses a storage backplane, the storage backplane includes an upstream interface and a downstream interface, the upstream interface includes a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface includes a high-speed signal interface, a management signal interface, and a power supply At least one of the signal interfaces; if the downstream interface of the storage backplane includes a high-speed signal interface, the high-speed signal interface in the downstream interface is connected to the high-speed signal interface in the upstream interface; if the downstream interface of the storage backplane includes a management signal interface, the management signal interface in the downstream interface is connected to the management signal interface in the upstream interface; if the downstream interface of the storage backplane includes a power signal interface, the power signal interface in the downstream interface is connected to the power signal interface in the upstream interface interface connection.

A fourth aspect discloses a computing device, and the computing device includes the storage backplane provided in the above third aspect.

It should be understood that the implementation and beneficial effects of the above-mentioned multiple aspects or any possible implementation manners of the present application may refer to each other.

Description of drawings

Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a computing device in a related art disclosed in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a computing device in another related technology disclosed in the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a storage backplane disclosed in an embodiment of the present application;

Fig. 4 is a schematic diagram of transmission of a power signal disclosed in an embodiment of the present application;

Fig. 5 is a schematic diagram of transmission of another power signal disclosed in the embodiment of the present application;

FIG. 6 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

Fig. 7 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

FIG. 8 is a schematic diagram of a high-speed signal transmission disclosed in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

FIG. 10 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

Fig. 11 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

FIG. 12A is a schematic diagram of an I2C bus cascade connection disclosed in the embodiment of the present application;

FIG. 12B is a schematic diagram of signal transmission of an I2C bus cascade connection disclosed in the embodiment of the present application;

Fig. 12C is a schematic diagram of signal transmission of a URAT bus cascade connection disclosed in the embodiment of the present application;

FIG. 13A is a schematic diagram of a SGPIO bus cascading disclosed in the embodiment of the present application;

Fig. 13B is a schematic diagram of signal transmission of a SGPIO bus cascade connection disclosed in the embodiment of the present application;

FIG. 14A is a schematic diagram of a JTAG bus cascading disclosed in the embodiment of the present application;

Fig. 14B is a schematic diagram of signal transmission of a JTAG bus cascade connection disclosed in the embodiment of the present application;

FIG. 14C is a schematic diagram of a cascaded PRESENT signal line disclosed in the embodiment of the present application;

FIG. 14D is a schematic diagram of a Board_ID signal line cascade connection disclosed in the embodiment of the present application;

Fig. 15 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

Fig. 16 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

Fig. 17 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

Fig. 18 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

Fig. 19 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

Fig. 20 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

Fig. 21 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application;

Fig. 22 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application;

Fig. 23 is a schematic diagram of a signal transmission circuit disclosed in an embodiment of the present application;

Fig. 24 is a schematic diagram of another signal transmission circuit disclosed in the embodiment of the present application.

Detailed ways

The embodiment of the present application discloses a signal transmission circuit, a computing device and a storage backplane, which can reduce the difficulty of mainboard wiring, save hardware resources, and improve the flexibility of storage backplane expansion. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

In order to better understand the embodiment of the present application, the application scenario of the embodiment of the present application is firstly described below.

The signal transmission circuit and computing device provided by the embodiments of the present application can be applied to storage backplane expansion scenarios in the server field, which can improve the flexibility of server storage backplane expansion and save hardware resources.

Exemplarily, the server may be a server of various structures and types such as a heterogeneous server, a rack server, a cabinet server, and a high-density server, which is not limited in this embodiment of the present application.

In order to better understand the embodiment of the present application, the related technologies of the embodiment of the present application are firstly described below.

The peripheral component interconnect express (PCIe) technology has been developed from PCIe 1.0 version to PCIe 5.0 version (5th generation PCIe technology). Currently, the data link speed of PCIe 5.0 can reach 32 giga transmission per second (GT/s), twice that of PCIe 4.0, and has backward compatibility.

PCIe is a high-speed serial computer expansion bus standard. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. In order to meet the transmission requirements of different devices, PCIe data transmission includes different specifications such as X1, X4, X8, and X16. X1 represents 1 Lane (channel), including two directions of sending and receiving, and each direction includes 1 pair of differential signals. Therefore, 1 Lane can transmit 2 pairs of differential signals. Similarly, X2 means 2 Lanes, which can transmit 4 pairs of differential signals, X8 means 8 Lanes, which can transmit 16 pairs of differential signals, and X16 means 16 Lanes, which can transmit 32 pairs of differential signals. Among them, the more the number of Lanes, the faster the data transmission rate can be.

Redundant arrays of independent disks (RAID) card can combine multiple hard disks to form a hard disk group (logical hard disk) to provide higher storage performance than a single hard disk, and can also provide data backup function to improve the reliability of data storage.

Generally, one or more expansion interfaces are reserved on the main system (mainboard) of the server, and these one or more expansion interfaces can be used to connect different storage subsystems (such as storage backplanes) to expand the server. storage capacity. Specifically, please refer to FIG. 1 , which is a schematic structural diagram of a computing device in a related art provided by an embodiment of the present application. As shown in FIG. 1 , the computing device 100 may include a mainboard 101 , and the mainboard 101 may include four sets of expansion interfaces, that is, an expansion interface 1011 - an expansion interface 1014 . Wherein, each set of expansion interfaces can include power signal interfaces, management signal interfaces and high-speed signal interfaces, and can be connected to one storage backplane. Therefore, four sets of expansion interfaces can expand up to four storage backplanes. The power signal interface can be used to output electricity on the main board 101 to the storage backplane, so as to supply power to components on the storage backplane (such as backplane controller, hard disk, etc.). The management signal interface can be used to transmit management signals (control signals), so that components (such as hard disks) on the storage backplane can be managed, such as performing firmware upgrades, turning on storage disk indicators on the storage backplane, and the like. The high-speed signal interface can be used to transmit high-speed signals such as peripheral component interconnect express (PCIe) signals, serial attached small computer system interface (SAS) signals, and SATA (serial advanced technology attachment) signals. The signal is used to read and write data to the hard disk on the storage backplane.

The expansion interface on the main board 101 can be connected to the storage backplane according to actual needs, can be partially connected to the storage backplane, or can be completely connected to the storage backplane. For example, when all storage backplanes are connected, the power signal interface, management signal interface, and high-speed signal interface of the expansion interface 1011 can be respectively connected to the power signal interface, management signal interface, and high-speed signal interface of the storage backplane 1 (102). The power signal interface, management signal interface and high-speed signal interface of the expansion interface 1012 can be respectively connected to the power signal interface, management signal interface and high-speed signal interface of the storage backplane 2 (103). The power signal interface, management signal interface and high-speed signal interface of the expansion interface 1013 can be respectively connected to the power signal interface, management signal interface and high-speed signal interface of the storage backplane 3 (104). The power signal interface, management signal interface and high-speed signal interface of the expansion interface 1014 can be respectively connected to the power signal interface, management signal interface and high-speed signal interface of the storage backplane 4 (105).

In the above manner, for a mainboard, when the storage backplane or storage capacity needs to be expanded, multiple storage backplanes can be connected in parallel through the expansion interface reserved on the mainboard to realize expansion. However, this method is not very flexible, and the expansion is limited by the number of expansion interfaces on the motherboard.

It should be understood that the interfaces (such as power signal interfaces, management signal interfaces, and high-speed signal interfaces) in the embodiments of the present application may be connectors or other conductive terminals. Wherein, the management signal is generally a low-speed signal, therefore, the management signal interface may be a low-speed signal connector. That is, management signals can be transmitted through low-speed signal connectors. Similarly, the power signal interface may be a power signal connector (power connector), and the high-speed signal interface may be a high-speed signal connector (such as a PCIe connector, a SAS connector, a SATA connector, etc.). It should also be understood that in the embodiment of the present application, the function of the interface or the connector is mainly to implement signal transmission between various components, which can be selected according to actual conditions, and is not limited in the embodiment of the present application.

Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a computing device in another related art disclosed in an embodiment of the present application. As shown in Figure 2, the computing device 200 may include a motherboard 201, and the motherboard 201 may include a central processing unit (central processing unit, CPU) 2011, a high-speed signal connector 2012, a power connector 2013, a low-speed signal connector 2014, and a PCIe connector (PCIe expansion slot) 2015, power connector 2018 and low-speed signal connector 2019. When the storage backplane needs to be expanded, it can be expanded through the high-speed signal connectors, power supply connectors, and low-speed signal connectors on the motherboard. For example, for the storage backplane a (202), its high-speed signal connector 2021 can be connected to the high-speed signal connector 2012 on the motherboard through a cable, and its power connector 2022 can be connected to the power connector 2013 on the motherboard through a cable. The low-speed signal connector 2023 can be connected to the low-speed signal connector 2014 on the motherboard through a cable. For another example, for the storage backplane b (203), at this time, since there is no corresponding high-speed signal interface on the motherboard to connect to, the RAID card 2016 can be inserted into the slot of the PCIe connector 2015 first. Specifically, the RAID card 2016 can be inserted into the slot of the PCIe connector 2015 through its own gold finger, thereby realizing the electrical connection between the RAID card 2016 and the PCIe connector 2015, so that the central processing unit 2011 on the motherboard 201 can send data to the RAID controller card. The card 2016 outputs high-speed signals. The RAID card 2016 may include a high-speed signal connector 2017, and the high-speed signal connector 2017 may be connected to the high-speed signal connector 2031 on the storage backplane b (203) through a cable. The power connector 2032 on the storage backplane b (203) can be connected to the power connector 2018 on the mainboard through a cable, and the low-speed signal connector 2033 on the storage backplane b (203) is connected to the low-speed signal on the mainboard The devices 2019 can be connected by cables.

It can be seen from FIG. 2 that the storage backplane a (202) may include 8 storage connectors (hard disk interface), and the storage backplane b (203) may include 4 storage connectors. It is assumed that the central processing unit 2011 and the storage backplane a ( 202) and the hard disk on the storage backplane b (203) communicate through PCIe signals. At this time, each storage connector can correspond to 1 PCIe Lane (channel). Therefore, the high-speed signal connector 2021 and the high-speed signal connector 2012 can Both are PCIe X8 connectors (such as Slimline x8 connectors), and the high-speed signal connector 2031 and the high-speed signal connector 2017 may both be PCIe X4 connectors (such as Slimline x4 connectors). Wherein, the storage connector can be used for inserting a hard disk.

From the relevant description corresponding to Figure 2 above, it can be known that for a motherboard that has been designed (that is, the designed motherboard), the number of high-speed signal connectors, the number of power connectors, the number of low-speed signal connectors, and the number of PCIe connections on the board The number of storage backplanes is fixed, so there is a limit to the number of storage backplanes it can support expansion. Moreover, since the number of channels (such as PCIe channels) corresponding to the high-speed signal connector on the motherboard is also fixed, it is generally only compatible with a specific storage backplane, and its scope of application is small.

For a motherboard under design, it is generally impossible to determine how many high-speed signal connectors, power connectors, low-speed signal connectors, PCIe connectors, etc. need to be reserved to meet future expansion needs. Too much will cause problems such as design redundancy, insufficient space, difficult motherboard wiring, and increased costs. If the various connectors are reserved too little, it will not be able to meet the later expansion requirements, and the motherboard needs to be redesigned, resulting in server products. The development cycle is long. Moreover, the shape of the reserved connector or the number of corresponding channels cannot be determined, which may not be able to meet various application scenarios in the future.

In addition, due to the limited number of high-speed signal connectors on the motherboard, it is generally necessary to develop different storage backplanes for different storage requirements. For the storage backplane, if you need to support 8 hard disks, you generally need to develop a storage backplane with 8 hard disk interfaces. If you need to support 16 hard disks, you generally need to develop a storage backplane with 16 hard disk interfaces. In this way, there will be too many types of storage backplanes, which is inconvenient for maintenance.

In order to solve the above problems, the embodiment of the present application discloses a storage backplane, which may include an upstream interface and a downstream interface. The upstream interface of a storage backplane can be connected to the expansion interface on the motherboard, or it can be connected to another storage backplane. downstream interface. In this way, multiple storage backplanes can be cascaded, and in some cases, reserving an expansion interface on the mainboard can meet the expansion requirements of the storage backplanes.

An embodiment of the present application provides a storage backplane (hard disk backplane), which may include an upstream interface and a downstream interface. Wherein, the upstream interface of the storage backplane may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface of the storage backplane may include at least one of a high-speed signal interface, a management signal interface, and a power signal interface, that is, a downstream interface It can include 7 different situations. These 7 situations are: only include high-speed signal interface, only include management signal interface, only include power supply signal interface, include both high-speed signal interface and management signal interface, and include both high-speed signal interface and power supply The signal interface also includes a management signal interface and a power signal interface, and also includes a high-speed signal interface, a management signal interface and a power signal interface.

It should be noted that the high-speed signal interface in the upstream interface of one storage backplane can be connected to the high-speed signal interface in the expansion interface on the first circuit board, or can be connected to the high-speed signal interface in the downstream interfaces of other storage backplanes. The management signal interface in the upstream interface of one storage backplane can be connected to the management signal interface in the expansion interface on the first circuit board, or can be connected to the management signal interface in the downstream interfaces of other storage backplanes. The power signal interface in the upstream interface of one storage backplane can be connected to the power signal interface in the expansion interface on the first circuit board, or can be connected to the power signal interface in the downstream interfaces of other storage backplanes. Wherein, the first circuit board may be a main board, or other circuit boards including expansion interfaces.

Wherein, when the high-speed signal interface in the upstream interface of a storage backplane is connected to the high-speed signal interface in the expansion interface on the first circuit board, high-speed signals (such as PCIe signals, SAS signals, SATA signal, etc.) transmission. When the high-speed signal interface in the upstream interface of one storage backplane is connected to the high-speed signal interface in the downstream interface of other storage backplanes, the inter-board transmission of high-speed signals can be realized, and the communication between multiple cascaded storage backplanes can be realized. The storage backplane connected to the first circuit board implements high-speed signal transmission with the first circuit board. Similarly, when the management signal interface in the upstream interface of a storage backplane is connected to the management signal interface in the expansion interface on the first circuit board, the management signal can be transmitted with the first circuit board. When the management signal interface in the upstream interface of one storage backplane is connected to the management signal interface in the downstream interface of other storage backplanes, the inter-board transmission of management signals can be realized, and the communication between multiple cascaded storage backplanes can be realized. The storage backplane connected to the first circuit board realizes the transmission of management signals with the first circuit board. When the power signal interface in the upstream interface of a storage backplane is connected to the power signal interface in the expansion interface on the first circuit board, the power signal can be transmitted with the first circuit board. When the power signal interface in the upstream interface of one storage backplane is connected to the power signal interface in the downstream interface of another storage backplane, the inter-board transmission of the power signal can be realized, and the connection between multiple cascaded storage backplanes can The storage backplane connected to the first circuit board implements power signal transmission with the first circuit board.

It can be seen that this kind of storage backplane can reduce the settings of high-speed connectors, power connectors, low-speed signal connectors, and PCIe connectors on the first circuit board by cascading the upstream interface and downstream interface, and can expand storage according to actual needs. In addition, the expansion quantity of the storage backplane may not be limited by the number of high-speed connectors and power connectors on the first circuit board, and the flexibility is relatively high.

The computing device and seven different types of storage backplanes provided by the present application are illustrated below with reference to FIGS. 3-24 .

The following describes the case where the downstream interface of the storage backplane only includes a power signal interface, please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of a storage backplane disclosed in an embodiment of the present application. As shown in FIG. 3 , the storage backplane 300 may include an upstream interface 301 and a downstream interface 302 . Wherein, the upstream interface 301 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 302 may include a power signal interface.

The power signal interface in the upstream interface 301 of the storage backplane 300 may be connected to the power signal interface in the downstream interface 302, so as to implement power signal transmission between the upstream interface and the downstream interface.

It should be understood that the high-speed signal interface in the upstream interface 301 of the storage backplane 300 can be connected to the corresponding component (such as a hard disk interface) on the storage backplane 300, so as to transmit high-speed signals (such as PCIe signals, SAS signals, SATA signals) etc.), read and write hard disk data, etc. The management signal interface in the upstream interface 301 of the storage backplane 300 can be connected with the corresponding components (such as the storage backplane controller) on the storage backplane 300, so as to transmit management signals (such as joint test working group signals, internal integration circuit signals, etc.), to control components on the storage backplane 300 (such as hard disks). The power signal interface in the upstream interface 301 of the storage backplane 300 can be connected with corresponding components on the storage backplane 300 (such as storage backplane controller, hard disk, etc.), so as to transmit power signals and supply power to these components.

In the embodiment of the present application, since the power supply voltages required by various components on the storage backplane 300 can include multiple types (such as 1.8V, 3.3V, 5V, etc.), the power supply signal transmission on the storage backplane 300 can also use multiple voltages. different ways. For example, the power signal interface in the upstream interface of the storage backplane can receive a voltage (such as 12V, 24V, etc.), and then can be converted to a different voltage by the voltage regulator module (voltage regulator module, VRM) on the storage backplane. Voltage, such as 1.8V, 3.3V, 5V, etc. For another example, the power supply signal in the upstream interface of the storage backplane can directly receive different voltage signals, such as 1.8V, 3.3V, 5V, etc., and then provide these voltages to corresponding components on the storage backplane 300 respectively. In the embodiment of the present application, there is no restriction on the voltage input by the power signal interface in the upstream interface of the storage backplane 300 and the voltage output by the power signal interface in the downstream interface of the storage backplane 300 .

The two modes of power signal transmission on the storage backplane are briefly introduced below with reference to FIG. 4 and FIG. 5 . Please refer to FIG. 4 . FIG. 4 is a schematic diagram of transmission of a power signal disclosed in an embodiment of the present application. As shown in FIG. 4 , the power signal input by the power signal interface in the upstream interface 301 of the storage backplane 300 can be 12V, and the 12V power signal can be transferred to the power signal interface in the downstream interface 302 of the storage backplane 300 . The storage backplane 300 can include 3 voltage adjustment modules, namely VRM1 (303), VRM2 (304) and VRM3 (305). The electricity is converted to 5V electricity, VRM2 (304) can be used to convert the 5V electricity output by VRM1 (303) to 1.8V electricity, and VRM3 (305) can be used to input 12V from the power signal interface in the upstream interface 301 The electricity is converted to 3.3V electricity. In this way, power of 1.8V, 3.3V, and 5V can be obtained, which can be provided to corresponding components on the storage backplane 300 for use. It should be understood that the conversion, transmission, etc. of the power signal shown in FIG. 4 are only exemplary illustrations, and are not intended to be limiting. In other embodiments of the present application, VRM2 (304) can also be a voltage adjustment module from 12V to 1.8V or a voltage adjustment module from 3.3V to 1.8V, and VRM1 (303) can also be a voltage from 5V to 3.3V Adjust mods. In some other embodiments of the present application, the 1.8V, 3.3V, and 5V power signals obtained after conversion by the voltage adjustment module can be directly transferred to the power signal interface in the downstream interface 302 of the storage backplane 300, and the downstream interface 302 does not need to input 12V power signal.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of transmission of another power signal disclosed in the embodiment of the present application. As shown in FIG. 5 , the voltage input by the power signal interface in the upstream interface 301 of the storage backplane 300 can be the voltage required by each component on the storage backplane 300, such as 1.8V, 3.3V and 5V, and the 1.8V, 3.3V The power signal of V and 5V can be transferred to the power signal interface in the downstream interface 302 of the storage backplane 300, and the power signal interface of the upstream interface 301 and the power signal interface of the downstream interface 302 respectively have at least three terminals to input the above-mentioned 1.8V , 3.3V and 5V power supply signals. In addition, the 1.8V, 3.3V, and 5V power signals can be used by corresponding components on the storage backplane 300 . It can be understood that the above two modes of power signal transmission can be used alone or in combination.

The following exemplifies the cascading of storage backplanes whose downstream interfaces only include power signal interfaces. Please refer to FIG. 6 . FIG. 6 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 6, the computing device 600 may include a first circuit board 601, and the first circuit board 601 may include an expansion interface 1 (6011), an expansion interface 2 (6012), and an expansion interface 3 (6013). Wherein, the expansion interface 1 (6011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the expansion interface 2 (6012) and the expansion interface 3 (6013) may include a high-speed signal interface and a management signal interface. When the storage backplane 1 (602) needs to be expanded for the computing device 600, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 6021 of the storage backplane 1 (602) can be connected to the first circuit board correspondingly The high-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (6011) on 601. When it is necessary to expand the storage backplane 2 (603) for the computing device 600, the high-speed signal interface and the management signal interface in the upstream interface 6031 of the storage backplane 2 (603) can be connected to the corresponding ports on the first circuit board 601 respectively. The high-speed signal interface and management signal interface in the expansion interface 2 (6012), and the power signal interface in the upstream interface 6031 of the storage backplane 2 (603) can be correspondingly connected to the downstream interface 6022 of the storage backplane 1 (602) power signal interface. When it is necessary to expand the storage backplane 3 (604) for the computing device 600, the high-speed signal interface and the management signal interface in the upstream interface 6041 of the storage backplane 3 (604) can be connected to the corresponding ports on the first circuit board 601 respectively. The high-speed signal interface and management signal interface in the expansion interface 3 (6013), and the power signal interface in the upstream interface 6041 of the storage backplane 3 (604) can be correspondingly connected to the downstream interface 6032 of the storage backplane 2 (603) power signal interface. It should be understood that the cascading of storage backplanes shown in FIG. 6 is only an illustration and is not limiting. In other embodiments of the present application, more or fewer storage backplanes as shown in FIG. 3 may be included. , and can be cascaded according to the actual situation.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the power supply signals between the storage backplanes can be transmitted in cascade. All of the storage backplanes reserve power signal interfaces, so that the number of power signal interfaces on the first circuit board can be reduced, thereby reducing the difficulty of wiring on the first circuit board.

It can be understood that, when the above-mentioned first power transmission mode is adopted, the first circuit board 601 can output a voltage (such as 12V) to the storage backplane 1 (602), and the number of pins (Pins) of the power connector can be as follows: 2Pin power connector, and a voltage adjustment module needs to be installed on each storage backplane. When adopting the above-mentioned second power transmission mode, the first circuit board 601 needs to be provided with a plurality of voltage adjustment modules, through which multiple voltage adjustment modules can output various voltages to the storage backplane 1 (602) (such as 1.8 V, 3.3V, 5V, etc.), at this time, the number of pins of the power connector can be 8Pin power connector, which is used to output the above three different voltage signals, and there is no need to set a voltage adjustment module on each storage backplane. Groups can reduce the number of settings of voltage adjustment modules, thereby reducing the overall cost. In actual scenarios, you can flexibly choose to use different transmission methods according to the actual situation.

It should be understood that the high-speed signal interface, power signal interface and management signal interface in the upstream interface 6021 of the storage backplane 1 (602) in FIG. Signal interface, power signal interface and management signal interface, but in other embodiments of the present application, different interfaces among the upstream interfaces of a storage backplane may also be connected to corresponding interfaces on different circuit boards. For example, assume that the computing device includes a circuit board 1 and a circuit board 2, wherein the circuit board 1 (such as a motherboard) includes a high-speed signal interface and a management signal interface, and the circuit board 2 (such as a power backplane) includes a power signal interface. , the high-speed signal interface and the management signal interface in the upstream interface of the storage backplane 1 can be respectively connected to the corresponding high-speed signal interface and management signal interface on the circuit board 1, and the power signal interface of the storage backplane 1 can be connected to the circuit board 2 Corresponding power signal interface.

It should be noted that the computing device may include a power supply unit (power supply unit, PSU), and the PSU may convert 220V, 380V, etc. into 48V/12V, and the converted 48V/12V may be provided to the first circuit board, and may be passed The first circuit board is directly provided to the storage backplane, or provided to the storage backplane after being converted by the first circuit board.

The following describes the case where the downstream interface of the storage backplane only includes a high-speed signal interface. Please refer to FIG. 7 , which is a schematic structural diagram of another storage backplane disclosed in an embodiment of the present application. As shown in FIG. 7 , a storage backplane 700 may include an upstream interface 701 and a downstream interface 702 . Wherein, the upstream interface 701 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 702 may include a high-speed signal interface.

The high-speed signal interface in the upstream interface 701 of the storage backplane 700 may be connected to the high-speed signal interface in the downstream interface 702, so as to implement high-speed signal transmission between the upstream interface and the downstream interface. It should be understood that the high-speed signal interface in the upstream interface 701 of the storage backplane 700 can also be connected to the corresponding components (such as hard disk interface) on the storage backplane 700, so as to transmit high-speed signals (such as PCIe signals, SAS signals, SATA signal, etc.), read and write hard disk data, etc.

It can be understood that the number of high-speed signal channels (such as PCIe channels, SAS channels, etc.) included in the high-speed signal interface in the upstream interface is limited, while each storage interface on the storage backplane and the high-speed signal interface in the downstream interface need Occupies a certain number of high-speed signal channels. Therefore, when the high-speed signal interface in the upstream interface includes insufficient high-speed signal channels, the number of high-speed signal channels can be expanded through the expansion chip. For example, a PCIe link (PCIe channel) may be extended through a PCIe switch chip to provide more PCIe interfaces for connecting PCIe devices. For another example, the SAS channel can be extended through the SAS expansion chip. It should be noted that, in this embodiment of the application, the number of high-speed signal channels included in the high-speed signal interface in the upstream interface of the storage backplane 700 and the number of high-speed signal channels included in the high-speed signal interface in the downstream interface of the storage backplane 700 No limit.

The manner of high-speed signal transmission on the storage backplane is exemplarily described below with reference to FIG. 8 . Please refer to FIG. 8 . FIG. 8 is a schematic diagram of a high-speed signal transmission disclosed in an embodiment of the present application. As shown in FIG. 8 , the storage backplane 700 may further include an expansion chip 703 and multiple storage interfaces (four are shown in the figure). The expansion chip 703 may include an upstream port (uplink port, UP) 7031 and multiple downstream ports (downlink port, DP), such as a downstream port 7032 and a downstream port 7033 . The upstream interface of the extension chip 703 may be connected to the high-speed signal interface in the upstream interface 701 of the storage backplane 700 to expand the high-speed signal channels included in the high-speed signal interface in the upstream interface 701 . The downstream interface of the extension chip 703 is an extended interface, and these extended interfaces can be connected to other high-speed signal devices (such as PCIe devices), and can also be connected to upstream interfaces of other expansion chips to expand and obtain more high-speed signal channels. For example, the downstream interface 7033 of the expansion chip 703 can be connected to the storage interface 704, and the storage interface 704 can be connected to a hard disk, so that reading and writing of data on the hard disk can be realized. The downstream interface 7032 of the extension chip 703 can be connected to the high-speed signal interface in the downstream interface 702 of the storage backplane 700 to provide high-speed signal channels to other cascaded storage backplanes.

The following exemplifies cascading of storage backplanes whose downstream interfaces only include high-speed signal interfaces. Please refer to FIG. 9 . FIG. 9 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 9 , the computing device 900 may include a first circuit board 901, and the first circuit board 901 may include an expansion interface 1 (9011), an expansion interface 2 (9012), and an expansion interface 3 (9013). Wherein, the expansion interface 1 (9011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the expansion interface 2 (9012) and the expansion interface 3 (9013) may include a power signal interface and a management signal interface. When the storage backplane 1 (902) needs to be expanded for the computing device 900, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 9021 of the storage backplane 1 (902) can be connected to the first circuit board correspondingly High-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (9011) on 901. When it is necessary to expand the storage backplane 2 (903) for the computing device 900, the power signal interface and the management signal interface in the upstream interface 9031 of the storage backplane 2 (903) can be respectively connected to the corresponding ports on the first circuit board 901. The power signal interface and management signal interface in the expansion interface 2 (9012), and the high-speed signal interface in the upstream interface 9031 of the storage backplane 2 (903) can be correspondingly connected to the downstream interface 9022 of the storage backplane 1 (902) high-speed signal interface. When it is necessary to expand the storage backplane 3 (904) for the computing device 900, the power signal interface and the management signal interface in the upstream interface 9041 of the storage backplane 3 (904) can be connected to the corresponding ports on the first circuit board 901 respectively. The power signal interface and management signal interface in the expansion interface 3 (9013), and the high-speed signal interface in the upstream interface 9041 of the storage backplane 3 (904) can be correspondingly connected to the downstream interface 9032 of the storage backplane 2 (903) high-speed signal interface. It should be understood that the storage backplane cascading shown in FIG. 9 is only an illustration and is not limiting. In other embodiments of the present application, more or less storage backplanes as shown in FIG. 7 or 8 may be included Storage backplane, and can be cascaded according to the actual situation.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the high-speed signals between the storage backplanes can be cascaded and transmitted. Therefore, a high-speed signal interface can be reserved on the first circuit board, and there is no need for each High-speed signal interfaces are reserved on the block storage backplanes, thereby reducing the number of high-speed signal interfaces on the first circuit board, thereby reducing the difficulty of wiring on the first circuit board.

It should be noted that the high-speed channels can be expanded by using expansion chips on the storage backplane, but when multiple storage backplanes are cascaded in multiple stages, there will be cascading of multiple expansion chips at this time. When multiple expansion chips are cascaded, the data transmission efficiency of the higher layer can be higher, and the transmission efficiency of the lower layer can be lower. Therefore, in order to avoid low data transmission efficiency, the number of cascaded storage backplanes can be controlled to be less than Some threshold (such as 3 or 4). For example, as shown in FIG. 3 may include extension chip 1, extension chip 2, and extension chip 3, which are respectively used to expand the high-speed signal channels of the high-speed signal interface transmission in the upstream interfaces of storage backplane 1, storage backplane 2, and storage backplane 3. The upstream interface of expansion chip 2 and the storage interface on storage backplane 1 (902) can be respectively connected to the downstream interface of expansion chip 1, and the upstream interface of expansion chip 3 and the storage interface on storage backplane 2 (903) can be respectively connected to the expansion The downstream interface of the chip 2 and the storage interface on the storage backplane 3 ( 904 ) can be connected to the downstream interface of the expansion chip 3 . Among them, when the downstream interface of an expansion chip transmits data, it will be limited by the upstream interface of the expansion chip, because the number of high-speed signal channels included in the upstream interface is fixed, which is equivalent to multiple devices connected to the downstream interface (such as multiple hard disk) will share the number of high-speed signal channels included in the upstream interface. Therefore, the transmission efficiency of the storage disks (such as hard disks) on the higher-level storage backplane 1 (902) is higher than that of the storage disks (such as hard disks) on the lower-level storage backplane 2 (903) and storage backplane 3 (904). Such as hard disk) transmission efficiency. Moreover, the lower the level, the longer the forwarding link, which also leads to lower transmission efficiency.

It can be understood that the computing device may include chips such as a CPU and a south bridge chip (platform controller hub, PCH) that can transmit high-speed signals (such as PCIe signals, SAS signals, SATA signals, etc.), and the high-speed signal interface on the first circuit board It can be connected to the corresponding pins of the CPU and PCH chips for transmitting high-speed signals.

In some embodiments, one or more PCIe interfaces may be provided on the first circuit board, and the one or more PCIe interfaces may be used to connect PCIe devices. Moreover, some PCIe devices (such as RAID cards) can provide high-speed signal interfaces, therefore, in some embodiments, the high-speed signal interface of the first circuit board can be a high-speed signal interface on the PCIe device.

The following describes the case where the downstream interface of the storage backplane only includes a management signal interface. Please refer to FIG. 10 , which is a schematic structural diagram of another storage backplane disclosed in an embodiment of the present application. As shown in FIG. 10 , a storage backplane 1000 may include an upstream interface 1001 and a downstream interface 1002 . Wherein, the upstream interface 1001 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1002 may include a management signal interface.

The management signal interface in the upstream interface 1001 of the storage backplane 1000 may be connected to the management signal interface in the downstream interface 1002, so as to realize the transmission of management signals between the upstream interface and the downstream interface. It should be understood that the management signal interface in the upstream interface 1001 of the storage backplane 1000 can also be connected to the corresponding components (such as hard disk interface, storage backplane controller) on the storage backplane 1000, so as to facilitate the transmission of management signals. Components on the backplane, such as hard disks, are managed.

The cascading of storage backplanes in which the downstream interfaces of the storage backplanes only include management signal interfaces is described below as an example. Please refer to FIG. 11 . FIG. 11 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 11 , the computing device 1100 may include a first circuit board 1101 , and the first circuit board 1101 may include an expansion interface 1 ( 11011 ), an expansion interface 2 ( 11012 ) and an expansion interface 3 ( 11013 ). Wherein, the expansion interface 1 (11011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the expansion interface 2 (11012) and the expansion interface 3 (11013) may include a power signal interface and a high-speed signal interface. When the storage backplane 1 (1102) needs to be expanded for the computing device 1100, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 11021 of the storage backplane 1 (1102) can be connected to the first circuit board correspondingly High-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (11011) on 1101. When it is necessary to expand the storage backplane 2 (1103) for the computing device 1100, the power signal interface and the high-speed signal interface in the upstream interface 11031 of the storage backplane 2 (1103) can be respectively connected to the first circuit board 1101 correspondingly. The power signal interface and high-speed signal interface in the expansion interface 2 (11012), and the management signal interface in the upstream interface 11031 of the storage backplane 2 (1103) can be correspondingly connected to the downstream interface 11022 of the storage backplane 1 (1102) management signal interface. When it is necessary to expand the storage backplane 3 (1104) for the computing device 1100, the power signal interface and the high-speed signal interface in the upstream interface 11041 of the storage backplane 3 (1104) can be respectively connected to the first circuit board 1101 correspondingly. The power signal interface and high-speed signal interface in the expansion interface 3 (11013), and the management signal interface in the upstream interface 11041 of the storage backplane 3 (1104) can be correspondingly connected to the downstream interface 11032 of the storage backplane 2 (1103) management signal interface. It should be understood that the cascading of storage backplanes shown in FIG. 11 is just an example and not limiting. In other embodiments of the present application, more or less storage backplanes as shown in FIG. 10 may be included. , and can be cascaded according to the actual situation.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the management signals between the storage backplanes can be transmitted in cascade, therefore, a management signal interface can be reserved on the first circuit board, and there is no need to provide The block storage backplanes all reserve management signal interfaces, so that the number of management signal interfaces on the first circuit board can be reduced, thereby reducing the difficulty of wiring on the first circuit board.

It can be understood that the management bus on the storage backplane can include multiple types, such as JTAG (joint testaction group, joint test working group) bus, SGPIO (serial general-purpose input/output, serial general-purpose input/output) bus, UART (universal asynchronous receiver/transmitter, universal asynchronous transceiver) bus, I2C (inter-integrated circuit, internal integrated circuit) bus, etc., and the storage backplane can also include single-ended signal lines, such as PRESENT signal lines (in-bit signal line), Board_ID signal line (storage backplane identification code signal line), etc. Correspondingly, the management signals on the storage backplane can include various types, such as JTAG signal, SGPIO signal, UART signal, I2C signal, PRESENT signal (such as the storage backplane in-position signal), Board_ID signal (such as the identification code of the storage backplane )wait.

Among them, the cascade connection of the above-mentioned management signal lines (such as management bus, single-ended signal line, etc.) or the cascade transmission of management signals, as well as the normal access of slave devices (such as hard disks), can be controlled by the backplane on the storage backplane. implement. The backplane controller may be a processor (such as a CPU), a complex programmable logic device (complex programmable logic device, CPLD), an application specific integrated circuit, a field programmable gate array, etc., and the following description will be made where the backplane controller is a CPLD.

The cascading of buses such as the JTAG bus, the I2C bus, and the SGPIO bus will be exemplarily described below. Among them, the I2C bus is a bidirectional two-wire synchronous serial bus, through which two signal lines (serial data line SDA and serial clock line SCL) can transmit information between devices connected to the bus. Please refer to FIG. 12A . FIG. 12A is a schematic diagram of an I2C bus cascade connection disclosed in an embodiment of the present application. As shown in FIG. 12A, a computing device 1200 may include a first circuit board 1201 and multiple cascaded storage backplanes, such as storage backplane 1 (1202), storage backplane 2 (1203) and storage backplane 3 (1204). . I2C signal transmission may be performed between the first circuit board 1201 and multiple cascaded storage backplanes. Specifically, the baseboard management controller (baseboard management controller, BMC) 12011 on the first circuit board 1201 can be connected to the management signal interface 12012, and the management signal interface 12012 can be connected to the management in the upstream interface on the storage backplane 1 (1202). The signal interface 12022 is connected, and the management signal interface 12022 can be connected with the CPLD (12021) on the storage backplane 1 (1202), and the CPLD (12021) can be connected with other I2C devices (such as hard disk, temperature sensor) on the storage backplane 1 (1202). etc.) and the management signal interface 12023 in the downstream interface are connected. The management signal interface 12032 in the upstream interface on the storage backplane 2 (1203) can be connected to the management signal interface 12023 in the downstream interface on the storage backplane 1 (1202), and the management signal interface 12032 can be connected to the storage backplane 2 (1203 ), the CPLD (12031) can be connected with other I2C devices on the storage backplane 2 (1203) and the management signal interface 12033 in the downstream interface. The management signal interface 12042 in the upstream interface on the storage backplane 3 (1204) can be connected to the management signal interface 12033 in the downstream interface on the storage backplane 2 (1203), and the management signal interface 12042 can be connected to the storage backplane 3 (1204 ), the CPLD (12041) can be connected with other I2C devices on the storage backplane 3 (1204) and the management signal interface 12043 in the downstream interface. It should be understood that the manner of cascading the I2C bus shown in FIG. 12A is only an example and not a limitation.

In order to understand the I2C bus cascading shown in FIG. 12A more clearly, please refer to FIG. 12B . FIG. 12B is a schematic diagram of signal transmission of an I2C bus cascading disclosed in an embodiment of the present application. As shown in Figure 12B, the two I2C pins of the BMC (12011) can be connected to the two I2C pins of the CPLD (12021) through a signal management interface (not shown in Figure 12B) to realize the connection between the BMC (12011) and the CPLD. (12021) Transmission of SCL signal and SDL signal. The other two I2C pins of the CPLD (12021) can be connected to the two I2C pins of the CPLD (12031) through a signal management interface (not shown in Figure 12B), so as to realize the connection between the CPLD (12021) and the CPLD (12031) Transmission of SCL signal and SDL signal. The other two I2C pins of the CPLD (12031) can be connected to the two I2C pins of the CPLD (12041) through a signal management interface (not shown in Figure 12B), so as to realize the connection between the CPLD (12031) and the CPLD (12041) Transmission of SCL signal and SDL signal. It should be understood that the CPLDs on each storage backplane may also be connected to other I2C devices on the storage backplane (not shown in FIG. 12B ). The aforementioned I2C pins may be GPIO (general-purpose input/output, general-purpose input/output) pins of the CPLD.

It should be noted that, in the embodiment of the present application, the CPLD on the storage backplane may play a role of forwarding in the I2C link. For example, when the BMC on the first circuit board communicates with the I2C device on the back-level storage backplane, the CPLD on the front one-level or multi-level storage backplane can forward the I2C device on the back-level storage backplane. Data transmitted between BMC and BMC. Moreover, the CPLD on a storage backplane can forward the data transmitted between other I2C devices on the local storage backplane and the BMC. Specifically, in a possible implementation manner, since the I2C addresses of the I2C devices on different cascaded storage backplanes may conflict, the BMC on the first circuit board communicates with the I2C device on the storage backplane During I2C communication, the Board_ID of the storage backplane and the corresponding I2C address can be indicated, and the conflict of the I2C address can be avoided through the Board_ID. For example, suppose the Board_ID of storage backplane 1 (1202) in Figure 12B is 01, the Board_ID of storage backplane 2 (1203) is 10, and the Board_ID of storage backplane 3 (1204) is 11. When the temperature sensor on the storage backplane 3 (1204) performs I2C communication, the BMC (12011) can send relevant data to the CPLD (12021), and indicate that the corresponding Board_ID is 11, and the corresponding I2C device address is the address of the temperature sensor, such as 010. After the CPLD (12021) receives the data sent by the BMC (12011), the CPLD (12021) can determine that the indicated Board_ID is 11, which is different from its own Board_ID 01, and can forward the data to the CPLD (12031). After the CPLD (12031) receives the data sent by the CPLD (12021), the CPLD (12031) can determine that the indicated Board_ID is 11, which is different from its own Board_ID 10, and can continue to forward the data to the CPLD (12041). After the CPLD (12041) receives the data sent by the CPLD (12031), the CPLD (12041) can determine that the indicated Board_ID 11 is the same as the Board_ID of its own storage backplane, and can send data to the storage backplane 3 according to the indicated I2C address 010 Temperature sensor on (1204). It should be understood that the relevant description of the above I2C communication is only an illustration and does not constitute a limitation thereto.

The cascade connection of the UART bus and the I2C bus is similar, and reference may be made to the related description of the above-mentioned FIG. 12A . Wherein, the UART bus includes a transmit (TX) signal line and a receive (RX) signal line, and its equivalent signal transmission schematic diagram can be referred to FIG. 12C . As shown in Figure 12C, the two UART pins of the BMC (12011) can be connected to the two UART pins of the CPLD (12021) through a signal management interface (not shown in Figure 12C) to realize the connection between the BMC (12011) and the CPLD (12021) Transmission of TX signal and RX signal. The other two UART pins of the CPLD (12021) can be connected to the two UART pins of the CPLD (12031) through a signal management interface (not shown in Figure 12C), so as to realize the connection between the CPLD (12021) and the CPLD (12031) Transmission of TX signal and RX signal. The other two UART pins of the CPLD (12031) can be connected with the two UART pins of the CPLD (12041) through a signal management interface (not shown in Figure 12C), so as to realize the connection between the CPLD (12031) and the CPLD (12041) Transmission of TX signal and RX signal. It should be understood that the CPLD on the storage backplane can forward the TX signal and the RX signal. For example, the CPLD (12021) on the storage backplane 1 (1202) can forward the TX signal sent by the BMC (12011) to the CPLD (12031), and can also forward the RX signal sent by the CPLD (12031) to the BMC (12011).

The SGPIO bus is a serial bus that can be used for a controller (such as a CPLD, RAID card, etc.) to output the status of a storage disk (such as a solid-state disk). Please refer to FIG. 13A . FIG. 13A is a schematic diagram of a SGPIO bus cascading disclosed in an embodiment of the present application. As shown in FIG. 13A, a computing device 1300 may include a first circuit board 1301 and multiple cascaded storage backplanes, such as storage backplane 1 (1302), storage backplane 2 (1303) and storage backplane 3 (1304). . SGPIO signals can be transmitted between the first circuit board 1301 and multiple cascaded storage backplanes. Specifically, the CPLD or south bridge chip (platform controller hub, PCH) 13011 on the first circuit board 1301 can be connected to the management signal interface 13012, and the management signal interface 13012 can be connected to the upstream interface on the storage backplane 1 (1302). The management signal interface 13022 is connected, and the management signal interface 13022 can be connected with the CPLD (13021) on the storage backplane 1 (1302), and the CPLD (13021) can be connected with other I2C devices on the storage backplane 1 (1302) and downstream interfaces The management signal interface 13023 is connected. The connection relationship between the storage backplane 2 (1303) and the storage backplane 3 (1304) is similar to that shown in FIG. 12A , and reference may be made to the corresponding description in FIG. 12A . It should be understood that the way of cascading the SGPIO bus shown in FIG. 13A is just an example and not a limitation.

In order to understand the SGPIO bus cascading shown in FIG. 13A more clearly, please refer to FIG. 13B . FIG. 13B is a schematic diagram of signal transmission of a SGPIO bus cascading disclosed in an embodiment of the present application. As shown in FIG. 13B , the SGPIO bus may include four signal lines of Sclok, Sload, Sdataout, and Sdatain, and the Sdatain signal line is optional. Wherein, Sclok may be a clock signal line, Sload may be an end signal line of the current bit stream, Sdataout may be a data output signal line, and Sdatain may be a data input signal line. The four SGPIO pins of CPLD/PCH (13011) can be connected with the four SGPIO pins of CPLD (13021) to realize Sclok signal, Sload signal, Sdataout signal between CPLD/PCH (13011) and CPLD (13021) and Sdatain signal transmission. The other four SGPIO pins of CPLD (13021) can be connected with four SGPIO pins of CPLD (13031) to realize the Sclok signal, Sload signal, Sdataout signal and Sdatain signal between CPLD (13021) and CPLD (13031) transmission. The other four SGPIO pins of CPLD (13031) can be connected with four SGPIO pins of CPLD (13041) to realize the Sclok signal, Sload signal, Sdataout signal and Sdatain signal between CPLD (13031) and CPLD (13041) transmission. It should be understood that the CPLDs on each storage backplane may also be connected to the storage disk indicator lights on the storage backplane (not shown in FIG. 13B ). The aforementioned SGPIO pins may be GPIO pins of the CPLD.

It should be noted that, in the embodiment of the present application, the CPLD on the storage backplane may play a forwarding role in the SGPIO link. For example, the CPLD (13021) may forward the Sclok signal, the Sload signal and the Sdataout signal sent by the CPLD/PCH (13011) on the first circuit board to the CPLD (13031). In addition, the CPLDs on each storage backplane can light up the storage disk indicators on the storage backplane based on the received Sdataout signal. Specifically, in a possible implementation, the CPLD/PCH (13011) can send the lighting signals of all storage disks to the CPLD (13021) in the order of the storage backplanes, assuming that the storage backplane 1 (1302), the storage backplane 2 (1303) and the storage backplane 3 (1304) are inserted with 4 hard disks. At this time, the lighting signal sent by CPLD/PCH (13011) may include lighting data corresponding to 12 hard disks. Among them, the first 4 lighting data of the lighting signal sent by the CPLD/PCH (13011) can be the lighting signals corresponding to the 4 hard disks on the storage backplane 1 (1302), and the middle 4 lighting data can be the lighting signals of the storage backplane 2 (1303). ), the last 4 lighting data can be the lighting signals corresponding to the 4 hard disks on the storage backplane 3 (1304). When the CPLD (13021) on the storage backplane 1 (1302) receives the lighting signal sent by the CPLD/PCH (13011), it can take the first 4 lighting data to light up the 4 hard disks on the storage backplane 1 (1302) corresponding indicator light. For example, assuming that 4 hard disks are respectively numbered 00, 01, 10 and 11, the 4 lighting data can correspond to the 4 hard disks in sequence. Similarly, the CPLD (13031) on the storage backplane 2 (1303) can light up the indicator lights corresponding to the 4 hard disks on the storage backplane 2 (1303) according to the middle 4 lighting data in the lighting signal. The CPLD (13041) on the storage backplane 3 (1304) can turn on the indicator lights corresponding to the 4 hard disks on the storage backplane 3 (1304) according to the last 4 lighting data in the lighting signal.

The JTAG bus is generally used to test chips, etc., and perform firmware upgrades (such as upgrading the firmware of the CPLD on the storage backplane), etc., and multiple chips can be connected in series through the JTAG interface to form a JTAG chain. Each device can be tested separately. JTAG signals generally include TCK (time cycle clock, clock signal), TMS (test mode selection, test mode selection signal), TDI (test data in, test data input signal) and TDO (test data out, test data output signal). Please refer to FIG. 14A . FIG. 14A is a schematic diagram of a JTAG bus cascading disclosed in an embodiment of the present application. As shown in FIG. 14A, a computing device 1400 may include a first circuit board 1401 and multiple cascaded storage backplanes, such as storage backplane 1 (1402), storage backplane 2 (1403) and storage backplane 3 (1404). . JTAG signal transmission can be performed between the first circuit board 1401 and multiple cascaded storage backplanes. Specifically, the BMC (14011) on the first circuit board 1401 can be connected to the management signal interface 14012, and the connection lines can include four signal lines including TCK signal line, TMS signal line, TDI signal line and TDO signal line. The management signal interface 14012 can be connected to the management signal interface 14023 in the upstream interface on the storage backplane 1 (1402), and the management signal interface 14023 can be connected to the JTAG connector (14022) on the storage backplane 1 (1402), which is connected to Can include 3 signal lines for TDI signal, TCK signal and TMS signal to JTAG connector (14022). The management signal interface 14023 can also be connected to the management signal interface 14024 on the storage backplane 1 (1402), and its connection can include 3 signal lines, which are used to transmit the TCK signal and the TMS signal to the management signal interface 14024 and receive the management signal from the management signal interface 14024. TDO signal of interface 14024. The management signal interface 14023 can also be connected to the CPLD (14021), and the connection can include 2 signal lines for transmitting the TCK signal and the TMS signal to the CPLD (14021). The CPLD (14021) can also be connected with the JTAG connector (14022), and its connection can include a signal line for receiving the TDO signal from the JTAG connector (14022). The CPLD (14021) may also be connected to the management signal interface 14024, and the connection may include a signal line for outputting a TDO signal to the management signal interface 14024. Relevant connections between storage backplane 2 (1403) and storage backplane 3 (1404) are similar to storage backplane 1 (1402), and reference may be made to relevant descriptions of storage backplane 1. It should be noted that the last board in the cascade, that is, the storage backplane 3 (1404), the TDI and TDO pins in the management signal interface in the downstream interface need to be connected together to form a complete data transmission loop . It should be understood that the way of cascading the JTAG bus shown in FIG. 14A is just an example and not a limitation.

For a clearer understanding of the JTAG bus cascading shown in FIG. 14A , please refer to FIG. 14B , which is a schematic diagram of signal transmission of a JTAG bus cascading disclosed in an embodiment of the present application. As shown in Figure 14B, the TMS pin and TCK pin of BMC (14011) can be connected with JTAG connector 14022, JTAG connector 14032, JTAG connector 14042, CPLD (14021), CPLD (14031) and CPLD (14041) respectively The TMS pin and TCK pin of the JTAG connector 14022, JTAG connector 14032, JTAG connector 14042, CPLD (14021), CPLD (14031) and CPLD (14041) corresponding TMS pin and TCK pin Output TMS signal and TCK signal. The TDI pin of BMC (14011) can be connected with the TDI pin of JTAG connector 14022, the TDO pin of JTAG connector 14022 can be connected with the TDI pin of CPLD (14021), the TDO pin of CPLD (14021) can be connected with The TDI pin of JTAG connector 14032 is connected, the TDO pin of JTAG connector 14032 can be connected with the TDI pin of CPLD (14031), the TDO pin of CPLD (14031) can be connected with the TDI pin of JTAG connector 14042, The TDO pin of the JTAG connector 14042 can be connected to the TDI pin of the CPLD (14041), and the TDO pin of the CPLD (14041) can be connected to the TDO pin of the BMC (14011), so that a complete data transmission loop can be formed.

It should be noted that, when the JTAG connector in FIG. 14A and FIG. 14B is not connected to an external device, its TDI pin and TDO pin can be short-circuited so as to transmit data. And, it can be understood that, in some embodiments, the JTAG connector in the above-mentioned Fig. 14A and Fig. 14B can not be set, and the TDI pin of the BMC (14011) can be connected to the TDI pin of the CPLD (14021), and the CPLD (14021 )’s TDO pin can be connected to the TDI pin of the CPLD (14031), and the TDO pin of the CPLD (14031) can be connected to the TDI pin of the CPLD (14041).

The PRESENT signal line is mainly used to identify whether the storage backplane is online, and generally includes one signal line, as shown in FIG. 14C . FIG. 14C is a schematic diagram of a cascaded PRESENT signal line disclosed in an embodiment of the present application. As shown in FIG. 14C, the first circuit board 1405 may include a power supply VDD and a resistor R1. When the first circuit board 1405 is not cascaded with the storage backplane 1 (1406), the first end of the resistor R1 is connected to VDD, and the first end of the resistor R1 The second terminal is in a floating state, and the voltage detected by the CPLD (14051) through the PRESENT pin may be VDD, and at this time it may be determined that the first circuit board (1405) is not cascaded with a storage backplane. When the first circuit board 1405 is cascaded to the storage backplane 1 (1406), the first end of the resistor R1 is connected to VDD, the second end of the resistor R1 can be grounded on the storage backplane 1 (1406), and the CPLD (14051) passes the PRESENT The voltage detected by the pin may be 0V, and at this time it may be determined that the first circuit board (1405) is cascaded with a storage backplane. Similarly, when the storage backplane 1 (1406) is cascaded with the storage backplane 2 (1407), the voltage detected by the CPLD (14061) through the PRESENT pin can be 0V, and at this time the level of the storage backplane 1 (1406) can be determined Another storage backplane is connected. It should be understood that the cascading of the PRESENT signal lines shown in FIG. 14C is just an example and not a limitation.

The Board_ID signal line is mainly used to store the CPLD on the backplane to set and store the identification code of the backplane, and generally includes one or more signal lines. Please refer to Figure 14D, which is a cascade connection of Board_ID signal lines disclosed in the embodiment of this application schematic diagram. As shown in FIG. 14D, the first circuit board 1405 may include a power supply VDD and a resistor R5, and the storage backplane 1 (1406) may include a resistor R6. When the first circuit board 1405 is cascaded with the storage backplane 1 (1406), The first ends of the resistors R5 and R6 are connected to VDD, and the second ends of the resistors R5 and R6 are grounded. Wherein, the two Board_ID pins of the CPLD (14061) can be respectively connected to the second terminal of the resistor R5 and the first terminal of the resistor R6, and the detected voltages can be 0V and VDD respectively. 0V is low level 0, and VDD is high level 1. At this time, the CPLD (14061) can determine that the Board_ID of the storage backplane is 01, that is to say, the Board_ID of the storage backplane 1 (1406) is 01. After the CPLD (14061) determines the Board_ID of the storage backplane where it is located, it can send the Board_ID to the CPLD on the next cascaded storage backplane, that is, the CPLD (14071) on the storage backplane 2 (1407), The CPLD (14071) may add 1 to the received Board_ID value as the Board_ID of its own storage backplane, and may determine that the Board_ID of the storage backplane 2 (1407) is 10. Similarly, the CPLD (14071) can send the Board_ID of its own storage backplane to the CPLD on the next cascaded storage backplane, that is, the CPLD (14081) on the storage backplane 3 (1408), and the CPLD (14081) You can add 1 to the received Board_ID value as the Board_ID of the storage backplane where you are located, and you can determine that the Board_ID of the storage backplane 3 (1408) is 11. It should be noted that, the setting of the Board_ID signal line in FIG. 14D is just an example and not a limitation. In other embodiments of the present application, more or fewer devices may be used, and different connection relationships may be used.

It should be understood that when the above-mentioned management bus is cascaded, the CPLD on the storage backplane needs to forward data (for example, I2C data, JTAG data, etc.), exchange information between upper and lower backplanes, and so on.

The following describes the case where the downstream interface of the storage backplane includes both a high-speed signal interface and a management signal interface. Please refer to FIG. 15 , which is a schematic structural diagram of another storage backplane disclosed in an embodiment of the present application. As shown in FIG. 15 , a storage backplane 1500 may include an upstream interface 1501 and a downstream interface 1502 . Wherein, the upstream interface 1501 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a management signal interface and a high-speed signal interface.

The management signal interface in the upstream interface 1501 of the storage backplane 1500 may be connected to the management signal interface in the downstream interface 1502, so as to realize the transmission of management signals between the upstream interface and the downstream interface. At the same time, the high-speed signal interface in the upstream interface 1501 of the storage backplane 1500 may be connected to the high-speed signal interface in the downstream interface 1502, so as to implement high-speed signal transmission between the upstream interface and the downstream interface. Wherein, the specific connection relationship between the high-speed signal interface in the upstream interface 1501 of the storage backplane 1500 and the high-speed signal interface in the downstream interface 1502 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes a high-speed signal interface. description and will not be repeated here. The specific connection relationship between the management signal interface in the upstream interface 1501 of the storage backplane 1500 and the management signal interface in the downstream interface 1502 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the management signal interface, and you can refer to the relevant description above. I won't repeat them here.

The cascading of the storage backplanes in which the downstream interface of the storage backplane includes both the high-speed signal interface and the management signal interface is exemplarily described below. Please refer to FIG. 16 . FIG. 16 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 16 , the computing device 1600 may include a first circuit board 1601, and the first circuit board 1601 may include an expansion interface 1 (16011), an expansion interface 2 (16012), and an expansion interface 3 (16013). Wherein, the expansion interface 1 (16011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the expansion interface 2 (16012) and the expansion interface 3 (16013) may include a power signal interface. When the storage backplane 1 (1602) needs to be expanded for the computing device 1600, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 16021 of the storage backplane 1 (1602) can be connected to the first circuit board correspondingly High-speed signal interface, power signal interface and management signal interface in expansion interface 1 (16011) on 1601. When it is also necessary to expand the storage backplane 2 (1603) for the computing device 1600, the power signal interface in the upstream interface 16031 of the storage backplane 2 (1603) can be correspondingly connected to the expansion interface 2 (16012) on the first circuit board 1601. ), and the management signal interface and high-speed signal interface in the upstream interface 16031 of the storage backplane 2 (1603) can be correspondingly connected to the management signal interface and the downstream interface 16022 of the storage backplane 1 (1602). High-speed signal interface. When it is also necessary to expand the storage backplane 3 (1604) for the computing device 1600, the power signal interface in the upstream interface 16041 of the storage backplane 3 (1604) can be correspondingly connected to the expansion interface 3 (16013) on the first circuit board 1601. ), and the management signal interface and high-speed signal interface in the upstream interface 16041 of the storage backplane 3 (1604) can be correspondingly connected to the management signal interface and the management signal interface in the downstream interface 16032 of the storage backplane 2 (1603). High-speed signal interface.

It should be noted that, in some embodiments, the power signal interfaces of the expansion interface 1 (16011), the expansion interface 2 (16012) and the expansion interface 3 (16013) on the first circuit board may be the same power signal interface. Specifically, since the same output voltage can supply power to multiple parallel-connected loads (such as storage backplanes), one power signal interface on the first circuit board can provide power to multiple parallel-connected storage backplanes through a multiplicity of cables. powered by.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the management signals and high-speed signals between the storage backplanes can be transmitted in cascade. Therefore, a management signal interface and a management signal interface can be reserved on the first circuit board. The high-speed signal interface does not need to reserve a management signal interface and a high-speed signal interface for each storage backplane, thereby reducing the number of management signal interfaces and high-speed signal interfaces on the first circuit board, thereby reducing the difficulty of wiring the first circuit board .

The following describes the case where the downstream interface of the storage backplane includes both a high-speed signal interface and a power signal interface. Please refer to FIG. 17 , which is a schematic structural diagram of another storage backplane disclosed in an embodiment of the present application. As shown in FIG. 17 , a storage backplane 1700 may include an upstream interface 1701 and a downstream interface 1702 . Wherein, the upstream interface 1701 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a power signal interface and a high-speed signal interface.

The power signal interface in the upstream interface 1701 of the storage backplane 1700 may be connected to the power signal interface in the downstream interface 1702, so as to implement power signal transmission between the upstream interface and the downstream interface. At the same time, the high-speed signal interface in the upstream interface 1701 of the storage backplane 1700 may be connected to the high-speed signal interface in the downstream interface 1702, so as to implement high-speed signal transmission between the upstream interface and the downstream interface. Among them, the specific connection relationship between the high-speed signal interface in the upstream interface 1701 of the storage backplane 1700 and the high-speed signal interface in the downstream interface 1702 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes a high-speed signal interface. description and will not be repeated here. The specific connection relationship between the power signal interface in the upstream interface 1701 of the storage backplane 1700 and the power signal interface in the downstream interface 1702 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the power signal interface, and you can refer to the above related description. I won't repeat them here.

The cascading of storage backplanes in which the downstream interfaces of the storage backplanes include both high-speed signal interfaces and power supply signal interfaces is exemplarily described below. Please refer to FIG. 18 . FIG. 18 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 18, a computing device 1800 may include a first circuit board 1801, and the first circuit board 1801 may include an expansion interface 1 (18011), an expansion interface 2 (18012), and an expansion interface 3 (18013). Wherein, the expansion interface 1 (18011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the expansion interface 2 (18012) and the expansion interface 3 (18013) may include a management signal interface. When the storage backplane 1 (1802) needs to be expanded for the computing device 1800, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 18021 of the storage backplane 1 (1802) can be connected to the first circuit board correspondingly The high-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (18011) on the 1801. When it is necessary to expand the storage backplane 2 (1803) for the computing device 1800, the management signal interface in the upstream interface 18031 of the storage backplane 2 (1803) can be correspondingly connected to the expansion interface 2 (18012) on the first circuit board 1801. ), and the power signal interface and high-speed signal interface in the upstream interface 18031 of the storage backplane 2 (1803) can be correspondingly connected to the power signal interface and the downstream interface 18022 of the storage backplane 1 (1802). High-speed signal interface. When it is necessary to expand the storage backplane 3 (1804) for the computing device 1800, the management signal interface in the upstream interface 18041 of the storage backplane 3 (1804) can be correspondingly connected to the expansion interface 3 (18013) on the first circuit board 1801. ), and the power signal interface and high-speed signal interface in the upstream interface 18041 of the storage backplane 3 (1804) can be connected to the power signal interface and the downstream interface 18032 of the storage backplane 2 (1803) correspondingly High-speed signal interface.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the power supply signal and high-speed signal between the storage backplanes can be transmitted in cascade. Therefore, a power signal interface and a power signal interface can be reserved on the first circuit board. The high-speed signal interface does not need to reserve a power signal interface and a high-speed signal interface for each storage backplane, thereby reducing the number of power signal interfaces and high-speed signal interfaces on the first circuit board, thereby reducing the wiring difficulty of the first circuit board ,save costs.

The following describes the case where the downstream interface of the storage backplane includes both the management signal interface and the power signal interface. Please refer to FIG. 19 , which is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application. As shown in FIG. 19 , a storage backplane 1900 may include an upstream interface 1901 and a downstream interface 1902 . Wherein, the upstream interface 1901 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a power signal interface and a management signal interface.

The power signal interface in the upstream interface 1901 of the storage backplane 1900 may be connected to the power signal interface in the downstream interface 1902, so as to implement power signal transmission between the upstream interface and the downstream interface. Meanwhile, the management signal interface in the upstream interface 1901 of the storage backplane 1900 may be connected to the management signal interface in the downstream interface 1902, so as to realize the transmission of management signals between the upstream interface and the downstream interface. Wherein, the specific connection relationship between the management signal interface in the upstream interface 1901 of the storage backplane 1900 and the management signal interface in the downstream interface 1902 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the management signal interface. description and will not be repeated here. The specific connection relationship between the power signal interface in the upstream interface 1901 of the storage backplane 1900 and the power signal interface in the downstream interface 1902 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the power signal interface, and you can refer to the relevant description above. I won't repeat them here.

The cascading of the storage backplanes in which the downstream interfaces of the storage backplanes include both the management signal interface and the power supply signal interface is exemplarily described below. Please refer to FIG. 20 , which is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 20, the computing device 2000 may include a first circuit board 2001, and the first circuit board 2001 may include an expansion interface 1 (20011), an expansion interface 2 (20012) and an expansion interface 3 (20013). Wherein, the extension interface 1 (20011) may include a high-speed signal interface, a power signal interface and a management signal interface, and the extension interface 2 (20012) and the extension interface 3 (20013) may include a high-speed signal interface. When it is necessary to expand the storage backplane 1 (2002) for the computing device 2000, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 20021 of the storage backplane 1 (2002) can be respectively connected to the first circuit board correspondingly The high-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (20011) on 2001. When it is also necessary to expand the storage backplane 2 (2003) for the computing device 2000, the high-speed signal interface in the upstream interface 20031 of the storage backplane 2 (2003) can be correspondingly connected to the expansion interface 2 (20012) on the first circuit board 2001. ), and the power signal interface and management signal interface in the upstream interface 20031 of the storage backplane 2 (2003) can be connected to the power signal interface and the management signal interface in the downstream interface 20022 of the storage backplane 1 (2002) correspondingly Manage signal interface. When it is also necessary to expand the storage backplane 3 (2004) for the computing device 2000, the high-speed signal interface in the upstream interface 20041 of the storage backplane 3 (2004) can be correspondingly connected to the expansion interface 3 (20013) on the first circuit board 2001. ), and the power signal interface and management signal interface in the upstream interface 20041 of the storage backplane 3 (2004) can be connected to the power signal interface and the management signal interface in the downstream interface 20032 of the storage backplane 2 (2003) correspondingly Manage signal interface.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the power supply signal and management signal between the storage backplanes can be transmitted in cascade. Therefore, a power signal interface and a power signal interface can be reserved on the first circuit board. The management signal interface does not need to reserve a power signal interface and a management signal interface for each storage backplane, thereby reducing the number of power signal interfaces and management signal interfaces on the first circuit board, thereby reducing the difficulty of wiring the first circuit board ,save costs.

The following describes the situation that the downstream interface of the storage backplane includes a high-speed signal interface, a management signal interface, and a power signal interface at the same time. Please refer to FIG. 21. FIG. 21 is a schematic structural diagram of another storage backplane disclosed in the embodiment of the present application . As shown in FIG. 21 , a storage backplane 2100 may include an upstream interface 2101 and a downstream interface 2102 . Wherein, the upstream interface 2101 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a high-speed signal interface, a management signal interface, and a power signal interface.

The power signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected to the power signal interface in the downstream interface 2102, so as to implement power signal transmission between the upstream interface and the downstream interface. The high-speed signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected to the high-speed signal interface in the downstream interface 2102, so as to implement high-speed signal transmission between the upstream interface and the downstream interface. The management signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected to the management signal interface in the downstream interface 2102, so as to realize the transmission of management signals between the upstream interface and the downstream interface. Wherein, the specific connection relationship between the management signal interface in the upstream interface 2101 of the storage backplane 2100 and the management signal interface in the downstream interface 2102 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the management signal interface. description and will not be repeated here. The specific connection relationship between the power signal interface in the upstream interface 2101 of the storage backplane 2100 and the power signal interface in the downstream interface 2102 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes the power signal interface, and you can refer to the above related description. I won't repeat them here. The specific connection relationship between the high-speed signal interface in the upstream interface 2101 of the storage backplane 2100 and the high-speed signal interface in the downstream interface 2102 is the same as the above-mentioned case where the downstream interface of the storage backplane only includes a high-speed signal interface, and you can refer to the above related descriptions, I won't repeat them here.

The cascading of storage backplanes in which the downstream interfaces of the storage backplanes include high-speed signal interfaces, management signal interfaces, and power supply signal interfaces is exemplarily described below. Please refer to FIG. 22 . FIG. 22 is a schematic structural diagram of another computing device disclosed in an embodiment of the present application. As shown in FIG. 22, the computing device 2200 may include a first circuit board 2201, and the first circuit board 2201 may include an expansion interface 1 (22011), and the expansion interface 1 (22011) may include a high-speed signal interface, a power signal interface, and a management signal interface. When the storage backplane 1 (2202) needs to be expanded for the computing device 2200, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 22021 of the storage backplane 1 (2202) can be connected to the first circuit board correspondingly The high-speed signal interface, power signal interface and management signal interface in the expansion interface 1 (22011) on the 2201. When it is necessary to expand the storage backplane 2 (2203) for the computing device 2200, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 22031 of the storage backplane 2 (2203) can be correspondingly connected to the storage backplane 1 (2202) the high-speed signal interface, the power signal interface and the management signal interface in the downstream interface 22022. When it is necessary to expand the storage backplane 3 (2204) for the computing device 2200, the high-speed signal interface, power signal interface and management signal interface in the upstream interface 22041 of the storage backplane 3 (2204) can be correspondingly connected to the storage backplane 2 (2203) the high-speed signal interface, the power signal interface and the management signal interface in the downstream interface 22032.

It can be seen that in the above method, when the storage backplane is extended for the computing device, the management signals, power signals and high-speed signals between the storage backplanes can be transmitted in cascade. Therefore, a management signal can be reserved on the first circuit board interface, a power signal interface, and a high-speed signal interface, it is not necessary to reserve a management signal interface, a power signal interface, and a high-speed signal interface for each storage backplane, thereby reducing the number of management signal interfaces and power signal interfaces on the first circuit board. and the number of high-speed signal interfaces, thereby reducing the difficulty of wiring the first circuit board and saving costs.

It should be noted that, the above-mentioned connection of the interface between the first circuit board and the storage backplane, and the connection of the interface between different storage backplanes are mainly used for conducting signals and not converting signals. For example, the high-speed signal interface in the downstream interface 9022 of the storage backplane 1 (902) in FIG. 9 can be connected to the high-speed signal interface in the upstream interface 9031 of the storage backplane 2 (903). The high-speed signal received by the signal interface is transmitted to the high-speed signal interface in the upstream interface 9031 , and the high-speed signal received by the high-speed signal interface in the upstream interface 9031 can also be transmitted to the high-speed signal interface in the downstream interface 9022 . For another example, the management signal interface in the downstream interface 11022 of the storage backplane 1 (1102) in FIG. 11 may be connected to the management signal interface in the upstream interface 11031 of the storage backplane 2 (1103), and The management signal received by the management signal interface is transmitted to the management signal interface in the upstream interface 11031 , and the management signal received by the management signal interface in the upstream interface 11031 may also be transmitted to the management signal interface in the downstream interface 11022 .

It can be understood that the high-speed signal interface, power signal interface, and management signal interface on the first circuit board are usually connected by cables to the high-speed signal interface, power signal interface, and management signal interface on the storage backplane. In a computing device, the distance between the first circuit board and the storage backplane is generally set relatively far, therefore, generally a plurality of long cables are required to realize the connection. When multiple storage backplanes are cascaded, the distance between the multiple storage backplanes is generally relatively short, and even in some embodiments, the storage backplanes can be directly plugged together, thus greatly reducing the calculation The length of the cable inside the device. It should be noted that, in the embodiment of the present application, there is no limitation on the connection mode between the various components, and various ways such as cables and direct plug-in may be used.

In some embodiments, the last cascaded storage backplane may not include downstream interfaces, which can reduce the number of overall power signal interfaces, high-speed signal interfaces, and management signal interfaces. For example, the storage backplane 604 in FIG. 6 may not include the downstream interface 6042, and corresponding power signal interfaces may be reduced. For another example, the storage backplane 904 in FIG. 9 may not include the downstream interface 9042, and corresponding high-speed signal interfaces may be reduced.

It should be understood that, based on the above seven types of storage backplanes, in actual situations, their use is flexible and changeable, and the same type of storage backplane can be used (for example, a storage backplane whose downstream interface only includes a power signal interface) can be used. For cascading, multiple types of storage backplanes (such as a storage backplane whose downstream interface only includes a power signal interface and a storage backplane whose downstream interface includes both a high-speed signal interface and a power signal interface) can also be used for cascading. Moreover, the cascading mode is also flexible and changeable. For example, the power signal interface in the upstream interface of one storage backplane can be connected to the power signal interface in the downstream interface of another storage backplane, or can be connected to the power supply on the first circuit board. signal interface. For another example, the power signal interface, high-speed signal interface and management signal interface in the upstream interface of one storage backplane can be respectively connected to the power signal interface, high-speed signal interface and management signal interface in the downstream interfaces of three different storage backplanes.

In addition, in actual scenarios, the most suitable multiple storage backplanes can be selected for cascading according to storage requirements. For example, suppose there are currently three types of storage backplanes, storage backplane a, storage backplane b, and storage backplane c, where storage backplane a can support 8 hard disks, and storage backplane b can support 4 hard disks. Storage backplane c can support two hard disks. If the customer's requirement is 16 hard disks, then two storage backplane a can be cascaded. If the customer's requirement is 12 hard disks, then a storage backplane a and a storage backplane b can be selected for cascading. If the customer's requirement is 6 hard disks, then a storage backplane b and a storage backplane c can be selected for cascading. The above three methods can meet the needs of users, and there is no need to develop a new storage backplane according to the needs of users, and the expansion can be completed by using the existing storage backplane. Moreover, cascading different storage backplanes can be applied to a variety of different scenarios, with high flexibility and practicability.

The following is an exemplary introduction to the cascading use of storage backplanes. When the system or computing equipment requires storage capacity or fewer storage disks, one storage backplane can be selected without cascading. As shown in FIG. 23 , assuming that the system needs to support 8 hard disks, at this time, only the storage backplane 1 (2300) can be expanded, and its downstream interfaces can include management signal interfaces and power signal interfaces at the same time. Specifically, the management signal interface in the upstream interface of the storage backplane 1 (2300) can be a low-speed signal connector 2301, which can be connected to the motherboard management signal, and the power signal interface in the upstream interface of the storage backplane 1 (2300) can be A power connector 2302, which can be connected to the motherboard power signal. The management signal interface in the downstream interface of the storage backplane 1 (2300) may be a low-speed signal connector 2303, which has a corresponding connection relationship with the low-speed signal connector 2301 (not shown in FIG. 23 ), and the low-speed signal connector 2301 also has a corresponding connection relationship with other components (such as CPLD, storage interface) on the storage backplane 1 (2300) (not shown in FIG. 23 ). The power signal interface in the downstream interface of the storage backplane 1 (2300) can be a power connector 2304, which has a corresponding connection relationship with the power connector 2302 (not shown in Figure 23), and the power connector 2302 is connected to the storage Other components (such as CPLD and storage interface) on the backplane 1 (2300) also have corresponding connections (not shown in FIG. 23 ) to supply power to the CPLD and the hard disk connected to the storage interface. The high-speed signal interfaces in the upstream interface of the storage backplane 1 (2300) can be SLM X4 (Slimline X4) connector 2305 and SLM X4 connector 2306, which can be connected to the high-speed signal of the motherboard (such as PCIe signal). The SLM X4 (Slimline X4) connector 2305 and the SLM X4 connector 2306 can be connected to the storage interface on the storage backplane 1 (2300), for example, the SLM X4 connector 2306 can be connected to the corresponding high-speed signal pin on the storage interface 2307.

When the system or computing equipment requires more storage capacity or more storage disks, 2-level, 3-level or more storage backplanes can be cascaded to achieve a smooth upgrade of storage system capacity specifications. As shown in Figure 24, assuming that the system needs to support 16 hard disks, a same storage backplane can be cascaded on the basis of Figure 23. At this time, storage backplane 1 (2300) and storage backplane 2 ( 2400). Specifically, the management signal interface in the upstream interface of the storage backplane 2 (2400) can be a low-speed signal connector 2401, which can be connected to the low-speed signal connector 2303 on the storage backplane 1 (2300), so as to implement a management signal interface. between transfers. Similarly, the power signal interface in the upstream interface of the storage backplane 2 (2400) can be a power connector 2402, which can be connected to the power connector 2304 on the storage backplane 1 (2300), so as to realize inter-board transmission of power signals . There is a corresponding connection relationship between the low-speed signal connector 2403 on the storage backplane 2 (2400) and the low-speed signal connector 2401 (not shown in FIG. Other components (such as CPLD, storage interface) also have a corresponding connection relationship (not shown in FIG. 24 ). There is a corresponding connection relationship between the power connector 2404 on the storage backplane 2 (2400) and the power connector 2402 (not shown in FIG. 24 ), and the power connector 2402 and other components on the storage backplane 2 (2400) (such as CPLD, storage interface) also has a corresponding connection relationship (not shown in FIG. 24 ). The high-speed signal interfaces in the upstream interface of the storage backplane 2 (2400) can be SLM X4 (Slimline X4) connector 2405 and SLMX4 connector 2406, which can be connected to the high-speed signal of the motherboard. The SLM X4 (Slimline X4) connector 2405 and the SLM X4 connector 2406 can be connected to the storage interface on the storage backplane 2 (2400), for example, the SLM X4 connector 2406 can be connected to the corresponding high-speed signal pin on the storage interface 2407. It can be seen that when multiple storage backplanes are cascaded in Figure 24, the requirements for power connectors and low-speed signal connectors on the motherboard remain unchanged, and there is no need to redesign the motherboard, which has high practicability and flexibility.

It should be noted that FIGS. 1 to 24 are only exemplary illustrations, and the embodiment of the present application does not limit them. Moreover, it can be understood that some of the drawings in Figures 1-24 have omitted part of the connection relationship for the convenience of description, but those skilled in the art can understand the complete connection relationship in combination with related technologies and the drawings provided in this application. For example, for FIG. 3, the storage backplane 300 may include a storage interface, and the storage interface included in the storage backplane 300 may be correspondingly connected to the high-speed signal interface, the management signal interface, and the power signal interface in the upstream interface 301 (FIG. 3 not shown). For another example, referring to FIG. 8 , the storage interface included in the storage backplane 700 may also be correspondingly connected to the power signal interface and the management signal interface in the upstream interface 701 (not shown in FIG. 8 ).

In the foregoing implementation manner, flexible expansion of multiple storage backplanes can be realized by cascading the upstream interface and the downstream interface between the storage backplanes. In actual scenarios, the number of storage backplanes and the types of storage backplanes can be flexibly configured according to the actual storage capacity required. There is no need to develop new storage backplanes for new storage requirements, which can reduce the types of backplanes and reduce the cost of products and systems. maintenance costs. Moreover, by adopting this cascading method, the number of high-speed signal interfaces, power signal interfaces, management signal interfaces and PCIe expansion interfaces reserved on the first circuit board can be correspondingly reduced, but at the same time, it can be compatible with various storage requirements, and can Reduce the development difficulty of the first circuit board.

It should be noted that related information (that is, the same information or similar information) and related descriptions in the above different embodiments may refer to each other.

It should be understood that the "connection" in this application can be understood as a direct connection (that is, an electrical connection); it can also be understood as an indirect connection, that is, a connection through other devices, components, modules, devices, etc.

The technical terms used in the embodiments of the present invention are only used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "the" and "the" are used to include the plural forms as well, unless the context clearly dictates otherwise. Further, the use of "comprising" and/or "comprising" used in the description means that there are said features, integers, steps, operations, elements and/or components, but it does not exclude the existence or addition of one or more other features, integers, steps, operations, elements and/or components.

It should also be understood that in each embodiment of the present application, "at least one" and "one or more" refer to one, two or more than two. The term "and/or" is used to describe the association relationship of associated objects, indicating that there may be three types of relationships; for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists alone, Wherein A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship.

Reference to "one embodiment" or "some embodiments" or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically stated otherwise.

The corresponding structures, materials, acts, and equivalents of all means or step and function elements in the appended claims, if any, are intended to include any structure, material, or act for performing the function in combination with other explicitly claimed elements. The description of the present invention has been presented for purposes of example and description, but is not intended to be exhaustive or to limit the invention to the form disclosed.

The specific implementation described above has further described the purpose, technical solutions and beneficial effects of the application in detail. It should be understood that the above description is only a specific implementation of the application, and is not intended to limit the scope of the application. Scope of protection: All modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of this application shall be included within the scope of protection of this application.

Claims (10)

1. A signal transmission circuit, characterized in that it includes a first circuit board, a first storage backplane and a second storage backplane; the first circuit board includes a first expansion interface; the first storage backplane includes A first upstream interface and a first downstream interface, the first upstream interface is connected to the first downstream interface; the second storage backplane includes a second upstream interface; the first upstream interface is connected to the first extension Interface connection; the second upstream interface is connected to the first downstream interface; or, the first circuit board further includes a second expansion interface, and the second upstream interface is respectively connected to the first downstream interface and the first downstream interface The second expansion interface is connected. 2. The signal transmission circuit according to claim 1, wherein the signal transmission circuit further comprises a third storage backplane, the third storage backplane includes a third upstream interface; the second storage backplane It also includes a second downstream interface; the third upstream interface is connected to the second downstream interface; or, the first circuit board further includes a third expansion interface, and the third upstream interface is connected to the second downstream interface respectively. The interface is connected to the third extension interface. 3. The signal transmission circuit according to claim 1 or 2, wherein the first expansion interface comprises a first high-speed signal interface, a first management signal interface and a first power signal interface; the second expansion interface including at least one of a second high-speed signal interface, a second management signal interface, and a second power signal interface; the first upstream interface and the second upstream interface both include a high-speed signal interface, a management signal interface, and a power signal interface, The first downstream interface includes at least one of a high-speed signal interface, a management signal interface, and a power signal interface; The high-speed signal interface, the management signal interface, and the power signal interface in the first upstream interface are respectively connected to the first high-speed signal interface, the first management signal interface, and the first power signal interface of the first expansion interface; If the first downstream interface includes a high-speed signal interface, a management signal interface, and a power signal interface, the high-speed signal interface, management signal interface, and power signal interface in the first downstream interface are respectively connected to the high-speed signal interface in the first upstream interface. The signal interface, management signal interface, and power signal interface, and the high-speed signal interface, management signal interface, and power signal interface in the second upstream interface are connected correspondingly; If the first downstream interface includes any one or any two of a high-speed signal interface, a management signal interface, and a power signal interface, any one or any two of the first downstream interfaces are connected to the first upstream The corresponding one or two of the high-speed signal interface, the management signal interface and the power signal interface in the interface, and the corresponding one or two of the high-speed signal interface, the management signal interface and the power signal interface of the second upstream interface are connected , and the rest of the second upstream interfaces are connected to corresponding interfaces of the second high-speed signal interface, the second management signal interface, and the second power signal interface of the second extension interface. 4. The signal transmission circuit according to claim 3, wherein the first storage backplane further includes an extension chip, the extension chip includes an upstream interface and a downstream interface, and the high-speed signal in the first upstream interface The interface is connected to the upstream interface of the expansion chip; If the first downstream interface includes a high-speed signal interface, the extension chip includes at least two downstream interfaces, one of the downstream interfaces of the extension chip is connected to the high-speed signal interface in the first downstream interface, and the extension chip The rest of the downstream interfaces are connected to the storage interfaces of the first storage backplane; If the first downstream interface does not include a high-speed signal interface, the downstream interface of the extension chip is connected to the storage interface of the first storage backplane; the storage interface is used to connect to a storage disk. 5. The signal transmission circuit according to claim 3 or 4, wherein the first storage backplane further includes a backplane controller, and if the first downstream interface includes a management signal interface, the backplane controller The controller is connected to the management signal interface in the first upstream interface, and the backplane controller is also connected to the management signal interface in the first downstream interface. 6. The signal transmission circuit according to any one of claims 3-5, wherein the first storage backplane further includes a voltage adjustment module, and the power signal interface in the first upstream interface is connected to the The input end of the voltage adjustment module is connected, and the output end of the voltage adjustment module is used to supply power to components on the first storage backplane. 7. The signal transmission circuit according to any one of claims 3-6, wherein the first high-speed signal interface of the first circuit board also includes a fast peripheral component interconnection PCIe interface, and the PCIe interface is used for Connect PCIe devices. 8. The signal transmission circuit according to any one of claims 2-7, wherein the second downstream interface includes at least one of a high-speed signal interface, a management signal interface, and a power signal interface; If the second downstream interface includes a high-speed signal interface, the high-speed signal interface in the second downstream interface is connected to the high-speed signal interface in the second upstream interface; If the second downstream interface includes a management signal interface, the management signal interface in the second downstream interface is connected to the management signal interface in the second upstream interface; If the second downstream interface includes a power signal interface, the power signal interface in the second downstream interface is connected to the power signal interface in the second upstream interface. 9. A computing device, comprising the signal transmission circuit according to any one of claims 1-8. 10. A storage backplane, characterized in that the storage backplane includes an upstream interface and a downstream interface, the upstream interface includes a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface includes a high-speed signal interface, at least one of a management signal interface and a power signal interface; If the downstream interface of the storage backplane includes a high-speed signal interface, the high-speed signal interface in the downstream interface is connected to the high-speed signal interface in the upstream interface; If the downstream interface of the storage backplane includes a management signal interface, the management signal interface in the downstream interface is connected to the management signal interface in the upstream interface; If the downstream interface of the storage backplane includes a power signal interface, the power signal interface in the downstream interface is connected to the power signal interface in the upstream interface.