CN116504890B - An infrared reverse polarity light-emitting diode epitaxial wafer, preparation method and LED - Google Patents

Abstract

The invention provides an infrared reverse polarity light-emitting diode epitaxial wafer, a preparation method and an LED. The epitaxial wafer comprises: a substrate, a first semiconductor layer, a quantum well layer and a second semiconductor layer deposited on the substrate in sequence; The quantum well layer includes M periodically alternately arranged InGaAs well layers, AlGaAs well layer protection layers, AlGaAsP barrier layers and AlGaAs absorbing buffer layers, and the growth rate of the AlGaAs absorbing buffer layers is the same as the growth rate of the AlGaAsP barrier layers. 1/4~1/3 of the speed, the present invention prevents the PH ₃ in the AlGaAsP barrier layer from intruding into the InGaAs well layer, and simultaneously eliminates the problem of the fuzzy interface between the well barriers, so that the growth quality of the InGaAs well layer is improved. The reliability and photoelectric efficiency of the epitaxial wafer are effectively improved.

Description

An infrared reverse polarity light-emitting diode epitaxial wafer, preparation method and LED

technical field

The invention belongs to the technical field of LED epitaxial wafers, and in particular relates to an infrared reverse polarity light-emitting diode epitaxial wafer, a preparation method and an LED.

Background technique

Infrared LEDs are widely used in the field of security monitoring and sensors. With the development of biometrics and smart devices, infrared LEDs are used more and more, and their status is gradually rising.

At present, the quantum wells of infrared LEDs are mostly made of InGaAs/AlGaAsP materials. The longer the wavelength, the more In components of InGaAs, the larger the lattice, and the greater the mismatch with the GaAs substrate. Therefore, the barrier layer uses AlGaAsP material and the well layer InGaAs material is used to form the complementarity of tensile stress and compressive stress, but there will be some problems, that is, the PH ₃ in the AlGaAsP barrier layer will invade the InGaAs well layer, causing the infrared wavelength to drift, the well barrier interface is not clear, the reliability is reduced, and the photoelectric efficiency reduce.

Contents of the invention

In order to solve the above-mentioned technical problems, the present invention provides a kind of infrared reverse polarity light-emitting diode epitaxial wafer, preparation method and LED, solves the stress problem of quantum well and has prevented PH ₃ in AlGaAsP barrier layer from invading in InGaAs well layer, also simultaneously The problem of blurred interface between the well barriers is eliminated, the growth quality of the InGaAs well layer is improved, and the reliability and photoelectric efficiency of the epitaxial wafer are effectively improved.

In the first aspect, the embodiment of the present invention provides the following technical solutions, an infrared reverse polarity light-emitting diode epitaxial wafer, including a substrate and a first semiconductor layer, a quantum well layer and a second semiconductor layer sequentially deposited on the substrate ;

The quantum well layer includes M periodically alternately arranged InGaAs well layers, AlGaAs well layer protection layers, AlGaAsP barrier layers and AlGaAs absorbing buffer layers, and the growth rate of the AlGaAs absorbing buffer layers is equal to the growth rate of the AlGaAsP barrier layers. 1/4~1/3 of the speed;

The first semiconductor layer includes a GaAs-buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, and an N-side Spacer layer deposited on the substrate in sequence. The second semiconductor layer includes a P-side Spacer layer, a P-type confinement layer, a P-type current spreading layer, a P-type transition layer, and a P-type ohmic contact layer deposited on the quantum well layer in sequence.

Compared with the prior art, the beneficial effects of the present application are as follows: First, the present application sets an AlGaAs well protective layer between the InGaAs well layer and the AlGaAsP barrier layer, and effectively prevents P atoms from invading when the AlGaAsP barrier layer is grown through the AlGaAs well protective layer. In the InGaAs well layer, the quality of the grown InGaAs well layer is guaranteed. At the same time, after the AlGaAsP barrier layer is grown, an AlGaAs absorption buffer layer is set between the AlGaAsP barrier layer of this period and the InGaAs well layer of the next period. At the same time, the growth rate of the AlGaAs absorbing buffer layer is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer, and its growth time is long, so that the AlGaAs absorbing buffer layer can effectively absorb the remaining pH in the cavity after growing the AlGaAsP barrier layer. _3. It can be used as a buffer layer before growing the InGaAs well layer of the next cycle, so that the cavity environment is more suitable when growing the InGaAs well layer of the next cycle. Secondly, the AlGaAs well layer protective layer and the AlGaAs absorbing buffer layer in the present invention, It can effectively grow high-quality InGaAs well layer, so that the separation of the well-barrier interface is relatively clear, and the emission wavelength of the quantum well is more concentrated. Since the AlGaAs well layer protection layer and the AlGaAs absorption buffer layer are both made of AlGaAs material, the AlGaAs well layer protection layer and The potential barrier of the AlGaAs absorbing buffer layer can be consistent with that of the AlGaAsP barrier layer, or even higher, which can effectively limit the overflow of electrons and greatly improve the luminous efficiency. At the same time, due to the improvement of the growth quality of the InGaAs well layer, the present invention The reliability of the provided epitaxial wafers has also been greatly improved.

Preferably, the thickness of the InGaAs well layer is in the range of 7 nm to 10 nm, the thickness of the AlGaAs well protection layer is in the range of 3 nm to 5 nm, the thickness of the AlGaAsP barrier layer is in the range of 10 nm to 30 nm, and the AlGaAs absorption buffer The thickness of the layer ranges from 10 nm to 15 nm.

Preferably, the growth rate of the AlGaAs absorbing buffer layer ranges from 2 Å/s to 3 Å/s, and the growth time of the AlGaAs absorbing buffer layer is not less than 30 s.

Preferably, the Al composition range in the AlGaAs well layer protection layer is 0.1-0.25, and the Al composition range in the AlGaAs absorption buffer layer is 0.1-0.25.

Preferably, the period M in which the AlGaAs well layer protection layer, the AlGaAsP barrier layer, the AlGaAs absorbing buffer layer and the InGaAs well layer are alternately arranged is in the range of: 3≤M≤10.

In the second aspect, the embodiments of the present invention also provide the following technical solutions, a method for preparing an infrared reverse polarity light-emitting diode epitaxial wafer, the preparation method comprising the following steps:

providing a substrate;

depositing a first semiconductor layer on the substrate;

M periods of InGaAs well layers, AlGaAs well layer protection layers, AlGaAsP barrier layers, and AlGaAs absorbing buffer layers are alternately deposited on the first semiconductor layer to form quantum well layers, wherein the growth rate of the AlGaAs absorbing buffer layers is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer;

depositing a second semiconductor layer on the AlGaAs absorbing buffer layer of the last cycle;

Wherein, a GaAs-buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, and an N-side Spacer layer are sequentially deposited on the substrate to form the first semiconductor layer. A P-side spacer layer, a P-type confinement layer, a P-type current spreading layer, a P-type transition layer, and a P-type ohmic contact layer are sequentially deposited on the AlGaAs absorption buffer layer in the last period to form the second semiconductor layer.

Preferably, the growth temperature range of the InGaAs well layer is 660°C to 670°C, the growth temperature of the AlGaAsP barrier layer is 10°C higher than the growth temperature of the InGaAs well layer, and the growth pressure range of the quantum well layer is It is 40mbar~60mbar.

In a third aspect, embodiments of the present invention provide the following technical solution, an LED comprising the above-mentioned infrared reverse polarity light emitting diode epitaxial wafer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.

FIG. 1 is a structural diagram of an infrared reverse polarity light-emitting diode epitaxial wafer provided by Embodiment 1 of the present invention;

FIG. 2 is a structural diagram of a quantum well layer provided in Embodiment 1 of the present invention;

FIG. 3 is a flowchart of a method for preparing an infrared reverse polarity light-emitting diode epitaxial wafer provided by Embodiment 2 of the present invention.

Explanation of reference signs:

The embodiments of the present invention will be further described below with reference to the accompanying drawings.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the embodiments of the present invention and should not be construed as limitations of the present invention.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical ", "horizontal", "top", "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present invention and Simplified descriptions, rather than indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and thus should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the embodiments of the present invention, terms such as "installation", "connection", "connection" and "fixation" should be interpreted in a broad sense unless otherwise clearly specified and limited. Disassembled connection, or integration; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the embodiments of the present invention according to specific situations.

Embodiment one

As shown in Figure 1, the first embodiment of the present invention provides an infrared reverse polarity light-emitting diode epitaxial wafer, including a substrate 1 and a first semiconductor layer deposited on the substrate 1 in sequence, a quantum well layer 8 and a second semiconductor layer;

As shown in Figure 2, the quantum well layer 8 includes M InGaAs well layers 81, AlGaAs well layer protection layers 82, AlGaAsP barrier layers 83 and AlGaAs absorbing buffer layers 84 arranged alternately periodically, and the AlGaAs absorbing buffer layers The growth rate of 84 is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer 83;

Specifically, the growth rate of the AlGaAs absorbing buffer layer 84 ranges from 2 Å/s to 3 Å/s, and the growth time of the AlGaAs absorbing buffer layer 84 is not less than 30 seconds. In this embodiment, the AlGaAs absorbing buffer layer 84 The growth rate is slow and the growth time is long. After the AlGaAsP barrier layer 83 of the previous cycle is grown, the AlGaAs absorbing buffer layer 84 is deposited and grown on the AlGaAsP barrier layer 83. The AlGaAs absorbing buffer layer 84 can effectively absorb The remaining PH ₃ in the cavity after growing the AlGaAsP barrier layer 83 prevents the PH ₃ in the AlGaAsP barrier layer 83 from entering into the InGaAs well layer 81 of the next period;

At the same time, the AlGaAs absorbing buffer layer 84 can be used as a buffer layer before growing the InGaAs well layer 81 of the next period, so that the cavity environment is more suitable when growing the InGaAs well layer 81 of the next period;

It is worth noting that the AlGaAs well protection layer 82 is located between the InGaAs well layer 81 and the AlGaAsP barrier layer 83 in the same period, and the AlGaAs well protection layer 82 effectively prevents P atoms from intruding into the InGaAs well layer 81 when the AlGaAsP barrier layer 83 is grown. In this method, the quality of the grown InGaAs well layer 81 is guaranteed, so the present invention isolates the mutual influence between the well barriers and As/P diffusion from the physical structure, so that the growth quality of the InGaAs well layer 81 is better, and the AlGaAsP The barrier layer 83 also plays a role of stress neutralization. The quantum well structure of the present invention is more stable, more conducive to the coincidence of electron-hole pairs, and greatly improves the reliability and photoelectric efficiency of epitaxy. The quantum well layer 8 of the present invention The AlGaAs well layer protective layer 82 and the AlGaAs absorbing buffer layer 84 can provide additional potential barriers, effectively restrict electron-hole pairs, increase recombination probability, and improve photoelectric efficiency.

In this embodiment, the InGaAs well layer 81 has a thickness ranging from 7 nm to 10 nm, the AlGaAs well protection layer 82 has a thickness ranging from 3 nm to 5 nm, and the AlGaAsP barrier layer 83 has a thickness ranging from 10 nm to 30 nm, The AlGaAs absorbing buffer layer 84 has a thickness ranging from 10 nm to 15 nm.

In this embodiment, the Al composition in the AlGaAs well protection layer 82 ranges from 0.1 to 0.25, and the Al composition in the AlGaAs absorbing buffer layer 84 ranges from 0.1 to 0.25.

In this embodiment, the period M of the alternate arrangement of the InGaAs well layer 81 , the AlGaAs well layer protection layer 82 , the AlGaAsP barrier layer 83 and the AlGaAs absorbing buffer layer 84 is in the range of 3≤M≤10.

In this embodiment, the first semiconductor layer includes a GaAs-buffer layer 2 deposited on the substrate 1 in sequence, an etching stop layer 3, an N-type ohmic contact layer 4, an N-type current spreading layer 5, an N-type Confinement layer 6, N-side Spacer layer 7, the second semiconductor layer includes P-side Spacer layer 9, P-type confinement layer 10, P-type current spreading layer 11, P-type transition layer deposited on the quantum well layer 8 in sequence Layer 12, P-type ohmic contact layer 13.

In order to facilitate subsequent photoelectric tests and facilitate understanding, several experimental groups and control groups are introduced in this application.

Wherein, the experimental group includes experimental group 1, experimental group 2, experimental group 3, experimental group 4, and experimental group 5, and the control group adopts the infrared reverse polarity light-emitting diode epitaxial wafer in the prior art, and its structure is roughly the same as that of embodiment 1. The same, but the difference is as follows: the quantum well layer 8 in the control group includes InGaAs well layers 81 and AlGaAsP barrier layers 83 arranged alternately in M periods;

The structure of Experimental Group 1 is roughly the same as that of Embodiment 1, but the differences are as follows: the quantum well layers in the infrared reverse polarity light-emitting diode epitaxial wafer in Experimental Group 1 include InGaAs well layers 81, AlGaAs well layers 81 and AlGaAs well layers alternately arranged in M periods. protection layer 82 and AlGaAsP barrier layer 83;

The structure of Experimental Group 2 is roughly the same as that of Embodiment 1, but the difference is as follows: the quantum well layer in the infrared reverse polarity light-emitting diode epitaxial wafer in Experimental Group 2 includes InGaAs well layers 81, AlGaAsP barrier layers alternately arranged in M periods 83. An AlGaAs absorbing buffer layer 84, and the growth rate of the AlGaAs absorbing buffer layer 84 is the same as that of the AlGaAsP barrier layer 83;

Experimental group three has roughly the same structure as that of embodiment one, but the differences are as follows: the quantum well layers in the infrared reverse polarity light-emitting diode epitaxial wafer in experimental group three include InGaAs well layers 81 and AlGaAs well layers alternately arranged in M periods. A protective layer 82, an AlGaAsP barrier layer 83, and an AlGaAs absorbing buffer layer 84, and the growth rate of the AlGaAs absorbing buffer layer 84 is the same as that of the AlGaAsP barrier layer 83;

The structure of Experimental Group 4 is substantially the same as that of Embodiment 1, but the difference is as follows: the quantum well layer in the infrared reverse polarity light-emitting diode epitaxial wafer in Experimental Group 4 includes InGaAs well layers 81, AlGaAs well layers 81 and AlGaAs well layers alternately arranged in M periods. A protective layer 82, an AlGaAsP barrier layer 83, and an AlGaAs absorbing buffer layer 84, and the growth rate of the AlGaAs absorbing buffer layer 84 is 1/6 of the growth rate of the AlGaAsP barrier layer 83;

Experimental group five has the same structure as that of embodiment one, and the quantum well layers in the infrared reverse polarity light-emitting diode epitaxial wafer in experimental group five include InGaAs well layers 81, AlGaAs well layer protective layers 82, The AlGaAsP barrier layer 83 and the AlGaAs absorption buffer layer 84 , and the growth rate of the AlGaAs absorption buffer layer 84 is 1/3 of the growth rate of the AlGaAsP barrier layer 83 .

The infrared reverse polarity light-emitting diode epitaxial wafers in the above-mentioned several experimental groups and the control group were prepared into chips with a size of 14mil, and photoelectric tests were carried out. The test results are shown in Table 1:

Table 1

As can be seen from Table 1, the infrared reverse polarity light-emitting diode epitaxial wafer disclosed in the experimental group five has the largest power, so its photoelectric efficiency is higher than that of the other experimental groups and the control group. The light decay is closer to 100%, and it has better anti-aging light decay ability.

It is worth noting that, in some other embodiments of the present invention, the following solution is also provided, an LED comprising the infrared reverse polarity light emitting diode epitaxial wafer as described in the first embodiment.

To sum up, the advantages of the first embodiment are: First, the present application sets the AlGaAs well protective layer 82 between the InGaAs well layer 81 and the AlGaAsP barrier layer 83, and the AlGaAs well protective layer 82 effectively prevents the growth of the AlGaAsP barrier layer. At 83, P atoms intrude into the InGaAs well layer 81, which ensures the quality of the grown InGaAs well layer 81. At the same time, after the AlGaAsP barrier layer 83 is grown, the AlGaAsP barrier layer 83 of this period and the InGaAs well layer of the next period An AlGaAs absorbing buffer layer 84 is arranged between the layers 81, and the growth rate of the AlGaAs absorbing buffer layer 84 is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer 83, and its growth time is long, so that the AlGaAs absorbing buffer layer 84 can Effectively absorbing the remaining PH ₃ in the cavity after growing the AlGaAsP barrier layer 83 can be used as a buffer layer before growing the next cycle of the InGaAs well layer 81, making the cavity environment more suitable when growing the next cycle of the InGaAs well layer 81, Secondly, the AlGaAs well layer protection layer 82 and the AlGaAs absorption buffer layer 84 in the present invention can effectively grow a high-quality InGaAs well layer 81, so that the separation of the well-barrier interface is relatively clear, and the emission wavelength of the quantum well is more concentrated. Both the well protection layer 82 and the AlGaAs absorption buffer layer 84 are made of AlGaAs material, and the potential barrier between the AlGaAs well protection layer 82 and the AlGaAs absorption buffer layer 84 can be consistent with that of the AlGaAsP barrier layer 83, or even higher, which can effectively The electron overflow is limited, and the luminous efficiency is greatly improved. At the same time, due to the improvement of the growth quality of the InGaAs well layer 81, the reliability of the epitaxial wafer provided by the present invention is also greatly improved.

Embodiment two

As shown in FIG. 3 , the second embodiment of the present invention provides a method for preparing an infrared reverse polarity light-emitting diode epitaxial wafer. The preparation method includes the following steps:

It is worth noting that in this embodiment, the epitaxial growth equipment is Aixtron-G4 equipment, the carrier gas is all H ₂ during the growth process, the pressure is kept at 50mbar, and the V/III ratio of the grown As-based material is kept above 40 , the V/III ratio of growing P-based materials is kept above 100.

S01, providing a substrate 1;

Specifically, in this embodiment, the substrate 1 uses a Si-doped GaAs substrate, wherein the GaAs substrate has the characteristics of mature preparation process, low price, easy cleaning and handling, and good stability at high temperature .

S02, depositing a first semiconductor layer on the substrate 1;

Among them, before depositing the first semiconductor layer on the substrate 1, the substrate 1 needs to be pretreated, that is, the required substrate 1 is put into MOCVD, the temperature is raised to 750°C, and H ₂ and AsH ₃ are introduced Baking at a high temperature is performed to clean the surface of the substrate 1 . After the substrate 1 is cleaned, the first semiconductor can be deposited on the substrate 1 .

Specifically, a GaAs-buffer layer 2, an etching stop layer 3, an N-type ohmic contact layer 4, an N-type current spreading layer 5, an N-type confinement layer 6, and an N-side Spacer layer 7 are sequentially deposited on the substrate 1 to form the first semiconductor layer;

Therefore, it is first necessary to deposit and grow the GaAs-buffer layer 2 on the substrate 1. The material of the GaAs-buffer layer 2 is GaAs, the growth temperature range is 640°C~690°C, the growth thickness range is 100nm~400nm, and the Si doping concentration range 1E18atoms/cm ³ ~2E18atoms/cm ³ ;

Preferably, the growth temperature of the GaAs-buffer layer 2 is preferably 660° C., the growth thickness is preferably 250 nm, and the Si doping concentration is preferably 1.5E18 atoms/cm ³ .

Afterwards, an etching stop layer 3 is deposited on the GaAs-buffer layer 2, the material of the etching stop layer 3 is GaInP, the growth temperature ranges from 640°C to 690°C, the growth thickness ranges from 150nm to 300nm, and the Si doping concentration ranges from 1E18atoms/cm ³ ~2E18atoms/cm ³ ;

Preferably, the growth temperature of the etch stop layer 3 is preferably 660° C., the growth thickness is preferably 220 nm, and the Si doping concentration is preferably 1.5E18 atoms/cm ³ .

Afterwards, an N-type ohmic contact layer 4 is deposited on the corrosion stop layer 3, the material of the N-type ohmic contact layer 4 is GaAs, the growth temperature ranges from 640°C to 690°C, the growth thickness ranges from 50nm to 90nm, and Si-doped The concentration range is 3E18atoms/cm ³ ~9E18atoms/cm ³ ;

Preferably, the growth temperature of the N-type ohmic contact layer 4 is preferably 660° C., the growth thickness is preferably 220 nm, and the Si doping concentration is preferably 6E18 atoms/cm ³ .

Afterwards, an N-type current spreading layer 5 is deposited on the N-type ohmic contact layer 4, the material of the N-type current spreading layer 5 is AlGaAs, the growth temperature ranges from 640°C to 690°C, and the growth thickness ranges from 7um to 9um. The doping concentration range is 2E18atoms/cm ³ ~5E18atoms/cm ³ ;

Preferably, the growth temperature of the N-type current spreading layer 5 is preferably 660°C, the growth thickness is preferably 8um, and the Si doping concentration is preferably 3.5E18atoms/cm ³ .

Afterwards, an N-type confinement layer 6 is deposited on the N-type current spreading layer 5. The material of the N-type confinement layer 6 is AlGaAs, the growth temperature range is 670°C~710°C, the growth thickness range is 200nm~600nm, and Si-doped The concentration range is 2E18atoms/cm ³ ~5E18atoms/cm ³ ;

Preferably, the growth temperature of the N-type confinement layer 6 is preferably 690° C., the growth thickness is preferably 400 nm, and the Si doping concentration is preferably 3.5E18 atoms/cm ³ .

Finally, an N-side Spacer layer 7 is deposited on the N-type confinement layer 6, the material of the N-side Spacer layer 7 is AlGaAs, the growth temperature ranges from 650°C to 690°C, the growth thickness ranges from 300nm to 600nm, and is not doped with Si. element;

Preferably, the growth temperature of the N-side Spacer layer 7 is preferably 670° C., and the growth thickness is preferably 450 nm.

S03, alternately depositing M periods of InGaAs well layers 81, AlGaAs well layer protection layers 82, AlGaAsP barrier layers 83, and AlGaAs absorption buffer layers 84 on the first semiconductor layer to form quantum well layers 8, wherein the The growth rate of the AlGaAs absorbing buffer layer 84 is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer 83;

Specifically, the material of the InGaAs well layer 81 is InGaAs, the material of the AlGaAsP barrier layer 83 is AlGaAsP, the thickness of the InGaAs well layer is 7nm~10nm, and the thickness of the AlGaAsP barrier layer 83 is 10nm~30nm. In particular, after the InGaAs well layer 81 is grown, it is necessary Growing an AlGaAs well protection layer 82, the material of the AlGaAs well protection layer 82 is AlGaAs, the Al composition is 10% to 25%, and the thickness is 4nm. The AlGaAs well protection layer 82 is used to protect the InGaAs well layer 81 from the AlGaAsP barrier layer The influence of PH ₃ in 83, after the AlGaAsP barrier layer 83 is grown, the AlGaAs absorption buffer layer 84 needs to be grown. The absorption buffer layer 84 requires a slower growth rate, the growth rate is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer 83, the growth rate is 2Å/s~3Å/s, and the growth time of the AlGaAsP barrier layer 83 is not less than 30S , consisting of an InGaAs well layer 81, an AlGaAs well layer protection layer 82, an AlGaAsP barrier layer 83, and an AlGaAs absorbing buffer layer 84 to form a deposition cycle, and the quantum well layer 8 includes 3 to 10 deposition cycles;

Wherein, the growth temperature of the InGaAs well layer 81 ranges from 660°C to 670°C, the growth temperature of the AlGaAsP barrier layer 83 is 10°C higher than the growth temperature of the InGaAs well layer 81, and the growth temperature of the quantum well layer 8 is The pressure range is 40mbar~60mbar.

It can be understood that the AlGaAs well layer protection layer 82 and the AlGaAs absorption buffer layer 84 in the present invention can effectively grow a high-quality InGaAs well layer 81, so that the separation of the well-barrier interface is relatively clear, and the emission wavelength of the quantum well is more concentrated. Since both the AlGaAs well protection layer 82 and the AlGaAs absorption buffer layer 84 are made of AlGaAs material, the potential barrier between the AlGaAs well protection layer 82 and the AlGaAs absorption buffer layer 84 can be consistent with that of the AlGaAsP barrier layer 83, or even higher , can effectively limit the electron overflow, greatly improve the luminous efficiency, and at the same time, due to the improvement of the growth quality of the InGaAs well layer 81, the reliability of the epitaxial wafer provided by the present invention is also greatly improved.

S04, depositing a second semiconductor layer on the AlGaAs absorbing buffer layer 84 in the last period;

Specifically, a P-side Spacer layer 9, a P-type confinement layer 10, a P-type current spreading layer 11, a P-type transition layer 12, and a P-type ohmic contact layer 13 are sequentially deposited on the AlGaAs absorbing buffer layer 84 in the last cycle to forming the second semiconductor layer;

Therefore, it is first necessary to deposit the P-side Spacer layer 9 on the AlGaAs absorbing buffer layer 84 in the last cycle, the material of the P-side Spacer layer 9 is AlGaAs, the growth temperature range is 650°C~690°C, and the growth thickness range is 300nm~ 600nm, no Si element doped;

Preferably, the growth temperature of the P-side Spacer layer 9 is preferably 670° C., and the growth thickness is preferably 450 nm.

Afterwards, a P-type confinement layer 10 is deposited on the P-side Spacer layer 9, the material of the P-type confinement layer 10 is AlGaAs, the growth temperature ranges from 670°C to 710°C, the growth thickness ranges from 200nm to 600nm, and the Si doping concentration is The range is 2E18atoms/cm ³ ~5E18atoms/cm ³ ;

Preferably, the growth temperature of the P-type confinement layer 10 is preferably 690° C., the growth thickness is preferably 400 nm, and the Si doping concentration is preferably 3.5E18 atoms/cm ³ .

After that, a P-type current spreading layer 11 is deposited on the P-type confinement layer 10, the material of the P-type current spreading layer 11 is AlGaAs, the growth temperature range is 640°C~690°C, and the growth thickness range is 0.4um~3um, Si The doping concentration range is 2E18atoms/cm ³ ~5E18atoms/cm ³ ;

Preferably, the growth temperature of the P-type current spreading layer 11 is preferably 670°C, the growth thickness is preferably 1.7um, and the Si doping concentration is preferably 3.5E18atoms/cm ³ .

Afterwards, a P-type transition layer 12 is deposited on the P-type current spreading layer 11, the material of the P-type transition layer 12 is AlGaAsP, the growth temperature range is 640°C~690°C, the growth thickness range is 10nm~20nm, Si-doped The concentration range is 2E18atoms/cm ³ ~5E18atoms/cm ³ , and the transition mode is that the flow rate of Al and As decreases uniformly to 0, and the flow rate of PH ₃ increases from 0 to 1000 uniformly, realizing the transition from AlGaAs to GaP;

Preferably, the growth temperature of the P-type transition layer 12 is preferably 670° C., the growth thickness is preferably 15 nm, and the Si doping concentration is preferably 3.5E18 atoms/cm ³ .

Afterwards, a P-type ohmic contact layer 13 is deposited on the P-type transition layer 12, the material of the P-type ohmic contact layer 13 is GaP, the growth temperature range is 540°C~590°C, and the growth thickness range is 30nm~50nm. The impurity concentration range is 5E19atoms/cm ³ ~2E20atoms/cm ³ ;

Preferably, the growth temperature of the P-type ohmic contact layer 13 is preferably 570° C., the growth thickness is preferably 40 nm, and the Si doping concentration is preferably 1.3E20 atoms/cm ³ .

Among them, the above epitaxial wafer production is completed, the three-group sources involved are TMGa, TMAl, TMIn, the five-group sources are AsH ₃ and PH ₃ , the N-type doping source is Si ₂ H ₆ , and the P-type doping source is CBr ₄ .

To sum up, in the present invention, an AlGaAs well protection layer 82 is provided between the InGaAs well layer 81 and the AlGaAsP barrier layer 83, and the AlGaAs well protection layer 82 effectively prevents P atoms from intruding into the InGaAs well layer 81 when the AlGaAsP barrier layer 83 is grown. The quality of the grown InGaAs well layer 81 is guaranteed, and at the same time, after the AlGaAsP barrier layer 83 is grown, an AlGaAs absorbing buffer layer 84 is provided between the AlGaAsP barrier layer 83 of this period and the InGaAs well layer 81 of the next period, At the same time, the growth rate of the AlGaAs absorption buffer layer 84 is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer 83, and its growth time is long, so that the AlGaAs absorption buffer layer 84 can effectively absorb and grow the AlGaAsP barrier layer 83 in the chamber. The remaining PH ₃ can be used as a buffer layer before growing the InGaAs well layer 81 of the next cycle, so that the chamber environment is more suitable for growing the InGaAs well layer 81 of the next cycle. Secondly, the AlGaAs well layer protective layer 82 in the present invention With the AlGaAs absorbing buffer layer 84, a high-quality InGaAs well layer 81 can be effectively grown, so that the separation of the well-barrier interface is relatively clear, and the emission wavelength of the quantum well is more concentrated. Using AlGaAs material, the potential barrier of the AlGaAs well layer protection layer 82 and the AlGaAs absorbing buffer layer 84 can be consistent with that of the AlGaAsP barrier layer 83, or even higher, which can effectively limit electron overflow and greatly improve luminous efficiency. Due to the improvement of the growth quality of the InGaAs well layer 81, the reliability of the epitaxial wafer provided by the present invention is also greatly improved.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (7)

1. An infrared reverse polarity light-emitting diode epitaxial wafer, characterized in that, comprises a substrate and a first semiconductor layer, a quantum well layer and a second semiconductor layer deposited on the substrate in sequence; The quantum well layer includes M periodically alternately arranged InGaAs well layers, AlGaAs well layer protection layers, AlGaAsP barrier layers and AlGaAs absorbing buffer layers, and the growth rate of the AlGaAs absorbing buffer layers is equal to the growth rate of the AlGaAsP barrier layers. 1/4~1/3 of the speed; The first semiconductor layer includes a GaAs-buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, and an N-side Spacer layer deposited on the substrate in sequence. The second semiconductor layer includes a P-side Spacer layer, a P-type confinement layer, a P-type current spreading layer, a P-type transition layer, and a P-type ohmic contact layer deposited on the quantum well layer in sequence; The growth rate of the AlGaAs absorbing buffer layer ranges from 2Å/s to 3Å/s, and the growth time of the AlGaAs absorbing buffer layer is not less than 30S. 2. The infrared reverse polarity light-emitting diode epitaxial wafer according to claim 1, characterized in that, the thickness range of the InGaAs well layer is 7nm~10nm, and the thickness range of the AlGaAs well layer protective layer is 3nm~5nm, The thickness range of the AlGaAsP barrier layer is 10nm-30nm, and the thickness range of the AlGaAs absorption buffer layer is 10nm-15nm. 3. The infrared reverse polarity light-emitting diode epitaxial wafer according to claim 1, characterized in that, the Al composition range in the AlGaAs well layer protective layer is 0.1-0.25, and the Al composition range in the AlGaAs absorbing buffer layer is 0.1~0.25. 4. The infrared reverse polarity light-emitting diode epitaxial wafer according to claim 1, characterized in that, the AlGaAs well layer protective layer, the AlGaAsP barrier layer, the AlGaAs absorbing buffer layer and the InGaAs well layer are alternately arranged The value range of the period M of the cloth is: 3≤M≤10. 5. A preparation method of the infrared reverse polarity light-emitting diode epitaxial wafer according to any one of claims 1-4, wherein the preparation method comprises the following steps: providing a substrate; depositing a first semiconductor layer on the substrate; M periods of InGaAs well layers, AlGaAs well layer protection layers, AlGaAsP barrier layers, and AlGaAs absorbing buffer layers are alternately deposited on the first semiconductor layer to form quantum well layers, wherein the growth rate of the AlGaAs absorbing buffer layers is 1/4~1/3 of the growth rate of the AlGaAsP barrier layer; depositing a second semiconductor layer on the AlGaAs absorbing buffer layer of the last cycle; Wherein, a GaAs-buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, and an N-side Spacer layer are sequentially deposited on the substrate to form the first semiconductor layer. A P-side Spacer layer, a P-type confinement layer, a P-type current spreading layer, a P-type transition layer, and a P-type ohmic contact layer are sequentially deposited on the AlGaAs absorbing buffer layer in the last cycle to form the second semiconductor layer; Wherein, the growth rate of the AlGaAs absorbing buffer layer ranges from 2 Å/s to 3 Å/s, and the growth time of the AlGaAs absorbing buffer layer is not less than 30 s. 6. The method for preparing an infrared reverse polarity light-emitting diode epitaxial wafer according to claim 5, wherein the growth temperature range of the InGaAs well layer is 660° C. to 670° C., and the growth temperature ratio of the AlGaAsP barrier layer is The growth temperature of the InGaAs well layer is 10°C higher, and the growth pressure range of the quantum well layer is 40mbar-60mbar. 7. An LED, characterized in that it comprises the infrared reverse polarity light emitting diode epitaxial wafer according to any one of claims 1-4.