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CN1163953C - Substrate type semiconductor device packaging method capable of preventing glue overflow - Google Patents

Substrate type semiconductor device packaging method capable of preventing glue overflow Download PDF

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Publication number
CN1163953C
CN1163953C CNB001345451A CN00134545A CN1163953C CN 1163953 C CN1163953 C CN 1163953C CN B001345451 A CNB001345451 A CN B001345451A CN 00134545 A CN00134545 A CN 00134545A CN 1163953 C CN1163953 C CN 1163953C
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substrate
semiconductor device
type semiconductor
molds
insulation layer
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CN1357910A (en
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ƽ
黄建屏
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A substrate type semiconductor device packaging method capable of preventing glue overflow is characterized in that an extended cavity part is formed on a specific position in an electric insulating layer on the surface of a substrate; the specific position is a position where the electrical insulating layer, the solid part of the mold and the cavity of the mold meet when the substrate-type semiconductor device is fixed at the specific position in the mold. In the manufacturing process of the packaging colloid, the colloid packaging material flowing into the hollow part can more quickly absorb the heat in the mould, so that the viscosity of the colloid packaging material is increased and the flow rate of the colloid packaging material is slowed down; therefore, the glue packaging material is not easy to overflow into the pressing gap between the electrical insulation layer and the mold to generate the glue overflow phenomenon.

Description

可防止溢胶的基板式半导体装置封装方法Substrate type semiconductor device packaging method capable of preventing glue overflow

本发明涉及一种半导体封装技术，特别是一种可防止溢胶的基板式半导体装置封装方法，其可用以封装一基板式半导体装置，但不会使制出的封装单元的露出表面上产生溢胶现象。The invention relates to a semiconductor packaging technology, in particular to a substrate-type semiconductor device packaging method capable of preventing glue overflow, which can be used to package a substrate-type semiconductor device, but does not cause overflow on the exposed surface of the manufactured packaging unit glue phenomenon.

基板式半导体装置为一种建构于基板(substrate)上的半导体装置，亦即以基板为底材来安置其中的半导体晶片。于置晶程序完成之后，一般须再进行一封装胶体制造过程(encapsulation process)，通过模铸方法(molding)来形成一封装胶体(molded compound，或称encapsulation body)，用以包覆半导体芯片，由此而保护半导体芯片不会受到外部环境的湿气或污染的影响而损坏。A substrate-type semiconductor device is a semiconductor device constructed on a substrate, that is, a semiconductor wafer disposed therein using the substrate as a base material. After the crystal placement process is completed, an encapsulation process is generally required to form a molded compound (or encapsulation body) by molding to coat the semiconductor chip. As a result, the semiconductor chip is protected against damage from moisture or contamination from the external environment.

然而已知的基板式半导体装置封装方法的一项问题在于封装胶体制造过程中所采用的胶质封装材料，一般为环氧树脂(epoxy resin)，易于溢流至封装胶体以外的露出表面上，甚至而溢流至外露的电性连接垫上，使得所制成的封装单元具有不佳的外观，并使得外露的电性连接垫具有不佳的电性连接效果。以下即配合附图的图1A至1C、图2A至2B、图3A至3B、及图4A至4C，分别简述四种不同型式的基板式半导体装置的封装过程中的溢胶问题。However, a problem with the known substrate-type semiconductor device packaging method is that the glue packaging material used in the manufacturing process of the packaging glue, generally epoxy resin (epoxy resin), is easy to overflow to the exposed surface other than the packaging glue, It even overflows onto the exposed electrical connection pads, so that the manufactured package unit has a poor appearance, and the exposed electrical connection pads have a poor electrical connection effect. 1A to 1C, FIGS. 2A to 2B, FIGS. 3A to 3B, and FIGS. 4A to 4C of the accompanying drawings briefly describe the adhesive overflow problem in the packaging process of four different types of substrate-type semiconductor devices.

图1A至1C显示一种已知单芯片焊线型基板式半导体装置封装方法。1A to 1C show a conventional single-chip wire-bonding substrate-type semiconductor device packaging method.

请首先参阅图1A，此种型式的半导体装置的组成构件包括：(a)一基板100，其具有一正面100a和一背面100b；(b)一半导体芯片110，其安置于基板100的正面100a上方；(c)一第一电性绝缘层121，其形成于基板100的正面100a上，用以作为一顶部焊垫罩幕(solder mask，S/M)；(d)一第二电性绝缘层122，其形成于基板100的背面100b上，用以作为一底部焊垫罩幕；以及(e)多个电性连接垫130，其设置于基板100的背面100b上，并通过第二电性绝缘层122而互相电性隔离。Please first refer to FIG. 1A, the components of this type of semiconductor device include: (a) a substrate 100, which has a front surface 100a and a back surface 100b; (b) a semiconductor chip 110, which is placed on the front surface 100a of the substrate 100 Above; (c) a first electrical insulating layer 121, which is formed on the front surface 100a of the substrate 100, used as a top solder mask (solder mask, S/M); (d) a second electrical Insulating layer 122, which is formed on the back surface 100b of the substrate 100, is used as a bottom pad mask; and (e) a plurality of electrical connection pads 130, which are arranged on the back surface 100b of the substrate 100, and pass through the second The electrical insulation layer 122 is electrically isolated from each other.

上述的尚未封装的半导体装置采用一特制的模具组140来进行封装胶体制造过程。此模具组140包含一下模具141和一上模具142；其中下模具141具有一平坦的上表面141a，而上模具142则具有一预定的模穴142a。The aforementioned unpackaged semiconductor device adopts a special mold set 140 for the encapsulant manufacturing process. The mold set 140 includes a lower mold 141 and an upper mold 142; wherein the lower mold 141 has a flat upper surface 141a, and the upper mold 142 has a predetermined cavity 142a.

请参阅图1B，接着即进行一封装胶体制造过程，其中将图1A所示的尚未封装的半导体装置安放于模具组140的一定位置上，亦即将底部的第二电性绝缘层122压置于下模具141的平坦表面141a上，并将上模具142压置于下模具141的上方，并使得半导体芯片110位于上模具142的模穴142a中。接着即可将一胶质封装材料，例如为环氧树脂，经由箭头M所示的通道而注入至模穴142a之中，由此而形成一封装胶体150，用以包覆半导体芯片110和基板100。Please refer to FIG. 1B , a packaging compound manufacturing process is then carried out, wherein the unpackaged semiconductor device shown in FIG. 1A is placed on a certain position of the mold set 140, that is, the second electrical insulating layer 122 at the bottom is pressed on on the flat surface 141 a of the lower mold 141 , and press the upper mold 142 above the lower mold 141 , and make the semiconductor chip 110 be located in the mold cavity 142 a of the upper mold 142 . Then, a colloidal packaging material, such as epoxy resin, can be injected into the mold cavity 142a through the channel indicated by the arrow M, thereby forming a packaging colloid 150 for covering the semiconductor chip 110 and the substrate. 100.

然而，由于第二电性绝缘层122与下模具141之间并无法达到气密性的压合，因此二者之间仍存在有一极狭小的缝隙(如图1B中的S所指的处)，使得一少量的封装材料会渗入至此缝隙S之中，亦即溢胶至第二电性绝缘层122的底部表面上。However, since the airtight lamination cannot be achieved between the second electrical insulating layer 122 and the lower mold 141, there is still a very narrow gap between the two (as indicated by S in FIG. 1B ). , so that a small amount of encapsulation material will seep into the gap S, that is, glue overflows to the bottom surface of the second electrically insulating layer 122 .

请接着参阅图1C，于封装胶体制造过程完成之后，即可将完成封装的半导体装置自模具组140中取出。但由于上述的溢胶问题，因此会有一些残留溢胶150a覆盖于第二电性绝缘层122的底部表面上，甚至而覆盖于电性连接垫130的露出表面上，使得所制成的封装单元具有不佳的外观，并同时使得电性连接垫130具有不佳的电性连接效果。Please refer to FIG. 1C , after the encapsulant manufacturing process is completed, the packaged semiconductor device can be taken out from the mold set 140 . However, due to the above-mentioned glue overflow problem, there will be some residual glue overflow 150a covering the bottom surface of the second electrical insulating layer 122, and even covering the exposed surface of the electrical connection pad 130, so that the package made The unit has a poor appearance, and at the same time makes the electrical connection pad 130 have a poor electrical connection effect.

上述的溢胶问题的一种解决方法为于封装胶体制造过程完成之后，接着即采用砂磨机或雷射装置来进行一溢胶清除程序(de-flashprocess)，由此将残留溢胶150a清除掉。One solution to the above-mentioned glue overflow problem is to use a sand mill or a laser device to perform a de-flash process after the encapsulation compound manufacturing process is completed, thereby removing the residual overflow glue 150a Lose.

然而此种解决方法的缺点在于其易于损伤基板的底部表面，使得所制成的封装单元仍具有不佳的外观。已知堆叠双芯片焊线型基板式半导体装置封装方法图2A至2B为剖面结构示意图，其中显示一已知堆叠双芯片焊线型基板式半导体装置封装方法；且此封装方法亦存在有前述的溢胶问题。However, the disadvantage of this solution is that it is easy to damage the bottom surface of the substrate, so that the finished packaging unit still has an unfavorable appearance. 2A to 2B are schematic cross-sectional structure diagrams, which show a known packaging method for stacked two-chip wire-bonded substrate-type semiconductor devices; and this packaging method also has the aforementioned Glue overflow problem.

如图2A所示，此种型式的半导体装置的组成构件包括：(a)一基板200，其具有一正面200a和一背面200b；(b)二个半导体芯片211、212，其以堆叠方式安置于基板200的正面200a上；以及(c)一电性绝缘层220，其形成于基板200的背面200b上，用以作为一底部焊垫罩幕。As shown in FIG. 2A, the components of this type of semiconductor device include: (a) a substrate 200, which has a front surface 200a and a back surface 200b; (b) two semiconductor chips 211, 212, which are arranged in a stacked manner on the front surface 200a of the substrate 200; and (c) an electrically insulating layer 220 formed on the back surface 200b of the substrate 200 for use as a bottom pad mask.

上述的尚未封装的半导体装置，采用与前述的图1A所示者相同的模具组来进行一封装胶体制造过程，因此于此将不对其作重复的说明。然而，由于此堆叠双芯片焊线型的基板式半导体装置的底部架构大致相似于前述的图1A所示的单芯片焊线型半导体装置，因此其亦存在有前述的溢胶问题。The aforementioned unpackaged semiconductor device adopts the same mold set as that shown in FIG. 1A to carry out an encapsulant manufacturing process, so it will not be repeated here. However, since the bottom structure of the stacked two-die wire-bond substrate-type semiconductor device is substantially similar to the aforementioned single-die wire-bond semiconductor device shown in FIG. 1A , it also has the above-mentioned adhesive overflow problem.

如图2B所示，封装胶体制造过程完成之后，即可形成一封装胶体250，用以包覆基板200和半导体芯片211、212。但由于上述的溢胶问题，底部的电性绝缘层220的露出表面的周围边缘上会存在一些残留溢胶250a。As shown in FIG. 2B , after the encapsulant manufacturing process is completed, an encapsulant 250 can be formed to cover the substrate 200 and the semiconductor chips 211 , 212 . However, due to the aforementioned glue overflow problem, there will be some residual glue overflow 250a on the peripheral edge of the exposed surface of the bottom electrical insulating layer 220 .

图3A至3B为剖面结构示意图，其中显示一已知倒置芯片型(flipchip)半导体装置封装方法；且此封装方法亦存在有前述的溢胶问题。3A to 3B are cross-sectional schematic diagrams, which show a known flipchip semiconductor device packaging method; and this packaging method also has the above-mentioned glue overflow problem.

如图3A所示，此种型式的半导体装置的组成构件包括：(a)一基板300，其具有一正面300a和一背面300b；(b)一半导体芯片310，其以一倒置的覆晶方式安置于基板300的正面300a上；以及(c)一电性绝缘层320，其形成于基板300的背面300b上，用以作为一底部焊垫罩幕。As shown in FIG. 3A , the components of this type of semiconductor device include: (a) a substrate 300 with a front surface 300a and a back surface 300b; (b) a semiconductor chip 310 in an inverted flip-chip manner disposed on the front surface 300a of the substrate 300; and (c) an electrically insulating layer 320 formed on the rear surface 300b of the substrate 300 for use as a bottom pad mask.

上述的尚未封装的半导体装置，采用与前述的图1A所示者相同的模具组来进行一封装胶体制造过程，因此于此将不对其作重复的说明。然而，由于此倒置芯片型的底部架构大致相似于前述的图1A所示的单芯片焊线型及图2A所示的堆叠双芯片焊线型，因此其亦有前述的溢胶问题。The aforementioned unpackaged semiconductor device adopts the same mold set as that shown in FIG. 1A to carry out an encapsulant manufacturing process, so it will not be repeated here. However, since the bottom structure of this inverted chip type is roughly similar to the aforementioned single-die wire-bond type shown in FIG. 1A and the stacked double-die wire-bond type shown in FIG. 2A , it also has the aforementioned adhesive overflow problem.

如图3B所示，封装胶体制造过程完成之后，即可形成一封装胶体350，用以包覆基板300和半导体芯片310。但由于上述的溢胶问题，底部的电性绝缘层320的露出表面的周围边缘上会存在一些残留溢胶350a。As shown in FIG. 3B , after the manufacturing process of the encapsulant is completed, an encapsulant 350 can be formed to cover the substrate 300 and the semiconductor chip 310 . However, due to the aforementioned glue overflow problem, there will be some residual glue overflow 350a on the peripheral edge of the exposed surface of the bottom electrical insulating layer 320 .

上述三种半导体装置的溢胶现象均发生于其基板的下方。然而，此种溢胶现象亦可能发生某些半导体装置的基板的上方，例如以下图4A至4C所述的球栅阵列型半导体装置。The glue overflow phenomenon of the above three kinds of semiconductor devices all occurs under the substrate. However, this glue overflow phenomenon may also occur above the substrate of some semiconductor devices, such as the ball grid array type semiconductor device described in FIGS. 4A to 4C below.

图4A至4C为剖面结构示意图，其中显示一已知球栅阵列型(BallGrid Array，BGA)半导体装置封装方法；且此封装方法亦存在有前述的溢胶问题。4A to 4C are cross-sectional schematic diagrams, which show a known ball grid array (BallGrid Array, BGA) semiconductor device packaging method; and this packaging method also has the aforementioned glue overflow problem.

请首先参阅图4A，此种型式的半导体装置的组成构件包括：(a)一基板400，其具有一正面400a和一背面400b；(b)一半导体芯片410，其安置于基板400的正面400a上；(c)一第一电性绝缘层421，其形成于基板400的正面400a上，用以作为一顶部焊垫罩幕；(d)一第二电性绝缘层422，其形成于基板400的背面400b上，用以作为一底部焊垫罩幕；以及(e)多个焊球垫(solder-ball pads)430，其形成于基板400的背面400b，并通过第二电性绝缘层422而互相电性隔离。Please first refer to FIG. 4A, the components of this type of semiconductor device include: (a) a substrate 400, which has a front surface 400a and a back surface 400b; (b) a semiconductor chip 410, which is placed on the front surface 400a of the substrate 400 (c) a first electrical insulation layer 421, which is formed on the front surface 400a of the substrate 400, used as a top pad mask; (d) a second electrical insulation layer 422, which is formed on the substrate and (e) a plurality of solder ball pads (solder-ball pads) 430, which are formed on the back surface 400b of the substrate 400 and pass through the second electrical insulating layer 422 and are electrically isolated from each other.

上述的尚未封装的球栅阵列型半导体装置采用一特制的模具组440来进行封装胶体制造过程。此模具组440包含一下模具441和一上模具442；其中下模具441具有一平坦的上表面441a，而上模具442则具有一预定的模穴442a和一平坦的下表面442b。The aforementioned non-packaged BGA semiconductor device adopts a special mold set 440 for the encapsulant manufacturing process. The mold set 440 includes a lower mold 441 and an upper mold 442; wherein the lower mold 441 has a flat upper surface 441a, and the upper mold 442 has a predetermined cavity 442a and a flat lower surface 442b.

请参阅图4B，接着即进行一封装胶体制造过程，其中将图4A所示的尚未封装的球栅阵列型半导体装置安置于模具组440的一定位置上，使得基板400的背面400b上的第二电性绝缘层422置放于下模具441的平坦表面441a上，并使得半导体芯片410位于上模具442的模穴442a中。接着即可将一胶质封装材料，例如为环氧树脂，经由箭头M所示的通道而注入至模穴442a之中，由此而形成一封装胶体450，用以包覆半导体芯片410和基板400。Please refer to FIG. 4B, and then carry out an encapsulant manufacturing process, wherein the ball grid array type semiconductor device shown in FIG. 4A is placed on a certain position of the mold set 440, so that the second The electrical insulating layer 422 is placed on the flat surface 441 a of the lower mold 441 , and makes the semiconductor chip 410 located in the mold cavity 442 a of the upper mold 442 . Then, a colloidal packaging material, such as epoxy resin, can be injected into the mold cavity 442a through the channel indicated by the arrow M, thereby forming a packaging colloid 450 for covering the semiconductor chip 410 and the substrate. 400.

然而，由于第一电性绝缘层421与上模具442的下表面442b之间并无法达到气密性的压合，因此二者之间仍存在有一极狭小的缝隙(如图4B中的S所指的处)，使得一少量的封装材料会渗入至此缝隙S之中，亦即溢胶至第一电性绝缘层421的表面上。However, since the first electrical insulating layer 421 and the lower surface 442b of the upper mold 442 cannot achieve airtight lamination, there is still a very narrow gap between the two (as indicated by S in FIG. 4B ). pointing), so that a small amount of encapsulation material will penetrate into the gap S, that is, glue overflows to the surface of the first electrical insulating layer 421 .

请接着参阅图4C，于封装胶体制造过程完成之后，即可将完成封装的球栅阵列型半导体装置自模具组440中取出。但由于上述的溢胶问题，因此会有一些残留溢胶450a覆盖于第一电性绝缘层421的表面上，使得所制成的封装单元具有不佳的外观。Please refer to FIG. 4C , after the encapsulant manufacturing process is completed, the packaged BGA semiconductor device can be taken out from the mold set 440 . However, due to the above-mentioned glue overflow problem, there will be some residual glue overflow 450 a covering the surface of the first electrical insulating layer 421 , so that the manufactured packaging unit has a poor appearance.

相关的专利技术例如包括美国专利第6,040,622号。此专利技术描述了一种多媒体电路卡(multi-media card，MMC)所用的基板式半导体装置的封装方法。然而此专利技术的缺点在于其中的封装胶体制造过程仍会产生前述的溢胶现象。Related patent technologies include, for example, US Patent No. 6,040,622. This patent technology describes a packaging method for a substrate-type semiconductor device used in a multimedia circuit card (multi-media card, MMC). However, the disadvantage of this patented technology is that the manufacturing process of the encapsulant still produces the above-mentioned glue overflow phenomenon.

鉴于以上所述已知技术的缺点，本发明的主要目的在于提供一种基板式半导体装置封装方法，其可防止前述的溢胶现象，以使得制成的封装单元具有干净的外观。In view of the disadvantages of the above-mentioned known technologies, the main purpose of the present invention is to provide a substrate-type semiconductor device packaging method, which can prevent the aforementioned glue overflow phenomenon, so that the finished packaging unit has a clean appearance.

本发明的另一目的在于提供一种基板式半导体装置封装方法，其可防止前述的溢胶现象，以使得外露的电性连接垫不会受残留溢胶所覆盖而影响其电性连接效果。根据以上所述的目的，本发明即提供了一种新颖的基板式半导体装置封装方法。Another object of the present invention is to provide a substrate-type semiconductor device packaging method, which can prevent the above-mentioned overflowing glue phenomenon, so that the exposed electrical connection pads will not be covered by residual overflowing glue and affect the electrical connection effect. According to the above objectives, the present invention provides a novel method for packaging semiconductor devices on substrates.

一种基板式半导体装置封装方法，其适用于封装一基板式半导体装置；该基板式半导体装置包括一基板、至少一半导体芯片安置于该基板、以及至少一电性绝缘层形成于该基板的一表面上；A method for packaging a substrate-type semiconductor device, which is suitable for packaging a substrate-type semiconductor device; the substrate-type semiconductor device includes a substrate, at least one semiconductor chip disposed on the substrate, and at least one electrically insulating layer formed on the substrate on the surface;

此基板式半导体装置封装方法包含以下步骤：The substrate type semiconductor device packaging method includes the following steps:

(1)预制一模具组，其具有一预定的模穴；(1) Prefabricate a mold group, which has a predetermined mold cavity;

(2)形成一延伸的空洞部分于该电性绝缘层中的一特定位置上；该特定位置为该基板式半导体装置于固定于该模具组中的一定位置时，该电性绝缘层、该模具组的实体部分、与该模具组的模穴三者之间的交会的处；且该空洞部分具有一预定的高度和宽度；(2) Forming an extended hollow portion at a specific position in the electrical insulating layer; the specific position is when the substrate-type semiconductor device is fixed in a certain position in the mold set, the electrical insulating layer, the the intersection between the solid portion of the mold set and the cavity of the mold set; and the cavity portion has a predetermined height and width;

(3)将该基板式半导体装置固定于该模具组的模穴中；其中该空洞部分便于该基板与该模具组的实体部分之间作用为一狭窄化的流体通道；以及(3) fixing the substrate-type semiconductor device in the mold cavity of the mold set; wherein the hollow portion facilitates a narrowed fluid passage between the substrate and the solid portion of the mold set; and

(4)将一胶质封装材料注入至该模具组的模穴之中，藉以形成一封装胶体，用以包覆该基板式半导体装置；其中该胶质封装材料于流入至该空洞部分所定义的狭窄化流体通道时，其流速将受到减缓而不易溢流至该电性绝缘层与该模具组之间的压合间隙之中，因此而防止溢胶现象。(4) Inject a gel encapsulation material into the mold cavity of the mold set to form an encapsulation compound for encapsulating the substrate type semiconductor device; wherein the encapsulation gel material flows into the cavity defined When the fluid channel is narrowed, its flow velocity will be slowed down so that it is not easy to overflow into the press-fitting gap between the electrical insulating layer and the mold set, thus preventing glue overflow.

一种基板式半导体装置封装方法，其适用于封装一基板式半导体装置；该基板式半导体装置包括一基板、至少一半导体芯片安置于该基板的顶部表面上、以及一电性绝缘层形成于该基板的底部表面上；A substrate-type semiconductor device packaging method, which is suitable for packaging a substrate-type semiconductor device; the substrate-type semiconductor device includes a substrate, at least one semiconductor chip is placed on the top surface of the substrate, and an electrical insulation layer is formed on the substrate on the bottom surface of the substrate;

此基板式半导体装置封装方法包含以下步骤：The substrate type semiconductor device packaging method includes the following steps:

(1)预制一模具组，其具有一预定的模穴；(1) Prefabricate a mold group, which has a predetermined mold cavity;

(2)形成一延伸的阶梯状空洞部分于该电性绝缘层的周围边缘上；且该阶梯状空洞部分具有一预定的高度和宽度；(2) forming an extended stepped cavity portion on the peripheral edge of the electrical insulating layer; and the stepped cavity portion has a predetermined height and width;

(3)将该基板式半导体装置固定于该模具组的模穴中；其中该阶梯状空洞部分便于该基板与该模具组之间作用为一狭窄化的流体通道；以及(3) fixing the substrate-type semiconductor device in the mold cavity of the mold set; wherein the stepped hollow portion facilitates a narrowed fluid passage between the substrate and the mold set; and

(4)将一胶质封装材料注入至该模具组的模穴之中，藉以形成一封装胶体，用以包覆该基板式半导体装置；其中该胶质封装材料于流入至该阶梯状空洞部分所定义的狭窄化流体通道时，其流速将受到减缓而不易溢流至该电性绝缘层与该模具组二者之间的压合间隙之中，因此而防止溢胶现象。(4) Inject a gel packaging material into the mold cavity of the mold set to form a packaging gel for covering the substrate type semiconductor device; wherein the gel packaging material flows into the stepped cavity When the fluid channel is narrowed, its flow velocity will be slowed down so that it is not easy to overflow into the pressing gap between the electrical insulating layer and the mold set, thus preventing glue overflow.

一种基板式半导体装置封装方法，其适用于封装一基板式半导体装置；该基板式半导体装置包括一基板、至少一电性绝缘层形成于该基板的顶部表面上、以及至少一半导体芯片安置于该电性绝缘层上；A substrate-type semiconductor device packaging method, which is suitable for packaging a substrate-type semiconductor device; the substrate-type semiconductor device includes a substrate, at least one electrically insulating layer is formed on the top surface of the substrate, and at least one semiconductor chip is placed on on the electrically insulating layer;

此基板式半导体装置封装方法包含以下步骤：The substrate type semiconductor device packaging method includes the following steps:

(1)预制一模具组，其具有一预定的模穴；(1) Prefabricate a mold group, which has a predetermined mold cavity;

(2)形成一延伸的沟槽状空洞部分于该电性绝缘层中的一特定位置上；该特定位置为该基板式半导体装置于固定于该模具组中的一定位置时，该电性绝缘层、该模具组的实体部分、与该模具组的模穴三者之间的交会的处；且该沟槽状空洞部分具有一预定的高度和宽度；(2) Forming an extended groove-shaped hollow part on a specific position in the electrical insulating layer; layer, the solid part of the mold set, and the mold cavity of the mold set; and the groove-shaped hollow portion has a predetermined height and width;

(3)将该基板式半导体装置固定于该模具组的模穴中；其中该沟槽状空洞部分便于该基板与该模具组的实体部分之间作用为一狭窄化的流体通道；以及(3) fixing the substrate-type semiconductor device in the mold cavity of the mold set; wherein the groove-shaped hollow portion facilitates a narrowed fluid passage between the substrate and the solid portion of the mold set; and

(4)将一胶质封装材料注入至该模具组的模穴之中，藉以形成一封装胶体，用以包覆该基板式半导体装置；其中该胶质封装材料于流入至该沟槽状空洞部分所定义的狭窄化流体通道时，其流速将受到减缓而不易溢流至该电性绝缘层与该模具组二者之间的压合间隙之中，因此而防止溢胶现象。(4) Inject a gel packaging material into the mold cavity of the mold set to form a packaging gel for covering the substrate type semiconductor device; wherein the gel packaging material flows into the groove-shaped cavity When the partially defined fluid channel is narrowed, its flow velocity will be slowed down so that it is not easy to overflow into the press-fitting gap between the electrical insulating layer and the mold set, thereby preventing glue overflow.

本发明的基板式半导体装置封装方法的特点在于形成一延伸的空洞部分于基板表面上的电性绝缘层中的一特定位置上；该特定位置即为该基板式半导体装置固定于模具中的一定位置时，其中的电性绝缘层、模具的实体部分、与模具的模穴三者之间的交会的处。The method for packaging a substrate-type semiconductor device of the present invention is characterized in that an extended cavity portion is formed at a specific position in the electrical insulating layer on the surface of the substrate; the specific position is the fixed position of the substrate-type semiconductor device in the mold The position is the intersection of the electrical insulating layer, the solid part of the mold, and the mold cavity of the mold.

于封装胶体制造过程中，由于此空洞部分即相当于一狭窄化的流体通道，使得流入至此空洞部分的胶质封装材料可更快速地吸收模具中的热量，而使得其黏度变大而减缓其流速；因此使得胶质封装材料不易进而溢流入电性绝缘层与模具之间的压合间隙之中，亦即不易于电性绝缘层的露出表面上产生溢胶现象。During the manufacturing process of the encapsulant, since the cavity is equivalent to a narrowed fluid channel, the colloidal encapsulation material flowing into the cavity can absorb the heat in the mold more quickly, making its viscosity larger and slowing down. The flow rate; therefore, it is difficult for the gel packaging material to overflow into the pressing gap between the electrical insulating layer and the mold, that is, it is not easy to produce glue overflow on the exposed surface of the electrical insulating layer.

本发明的实质技术内容及其实施例已用图解方式详细描述绘制于本说明书附图之中。这些图式的内容简述如下：The essential technical content of the present invention and its embodiments have been described in detail in diagrammatic form and drawn in the accompanying drawings of this specification. The contents of these diagrams are briefly described as follows:

图1A至1C(已知技术)为剖面结构示意图，其中显示一已知的单芯片焊线型基板式半导体装置封装方法；1A to 1C (known technology) are cross-sectional schematic diagrams, which show a known single-chip wire-bonding substrate-type semiconductor device packaging method;

图2A至2B(已知技术)为剖面结构示意图，其中显示一已知的堆叠双芯片焊线型基板式半导体装置封装方法；2A to 2B (known technology) are cross-sectional schematic diagrams, which show a known method of packaging semiconductor devices with stacked two-chip wire-bonded substrates;

图3A至3B(已知技术)为剖面结构示意图，其中显示一已知的倒置芯片型半导体装置封装方法；3A to 3B (known technology) are cross-sectional schematic diagrams, which show a known method of packaging an inverted chip type semiconductor device;

图4A至4C(已知技术)为剖面结构示意图，其中显示一已知的球栅阵列型半导体装置封装方法；4A to 4C (known technology) are cross-sectional schematic diagrams, which show a known ball grid array semiconductor device packaging method;

图5A至5C为剖面结构示意图，其中显示本发明的基板式半导体装置封装方法的第一实施例；5A to 5C are cross-sectional schematic diagrams, which show a first embodiment of the substrate-type semiconductor device packaging method of the present invention;

图6A至6B为剖面结构示意图，其中显示本发明的基板式半导体装置封装方法的第二实施例；6A to 6B are cross-sectional schematic diagrams, which show a second embodiment of the substrate-type semiconductor device packaging method of the present invention;

图7A至7B为剖面结构示意图，其中显示本发明的基板式半导体装置封装方法的第三实施例；7A to 7B are cross-sectional schematic diagrams, which show a third embodiment of the substrate-type semiconductor device packaging method of the present invention;

图8A至8C为剖面结构示意图，其中显示本发明的基板式半导体装置封装方法的第四实施例。8A to 8C are cross-sectional schematic diagrams showing a fourth embodiment of the substrate-based semiconductor device packaging method of the present invention.

附图标号说明Explanation of reference numbers

100  基板                      100a 基板100的顶部表面100 Substrate 100a Top surface of substrate 100

100b 基板100的底部表面         110  半导体芯片100b bottom surface of substrate 100 110 semiconductor chip

121  第一电性绝缘层(焊垫罩幕)121 The first electrical insulation layer (pad mask)

122  第二电性绝缘层(焊垫罩幕)122 Second electrical insulation layer (pad mask)

122a 阶梯状空洞部分            130  电性连接垫122a Ladder hollow part 130 Electrical connection pad

140  模具组                    141  下模具140 Die group 141 Lower mold

141a 下模具141的上表面         142  上模具141a upper surface of lower mold 141 142 upper mold

142a 模穴                      150  封装胶体142a Cavity 150 Encapsulation compound

150a 残留溢胶                  200  基板150a residual glue overflow 200 substrate

200a 基板200的顶部表面         200b 基板200的底部表面200a top surface of substrate 200 200b bottom surface of substrate 200

211  第一半导体芯片            212  第二半导体芯片211 The first semiconductor chip 212 The second semiconductor chip

220  电性绝缘层(焊垫罩幕)      220a 阶梯状空洞部分220 Electrical insulating layer (pad mask) 220a Ladder-shaped hollow part

250  封装胶体                  250a 残留溢胶250 Encapsulation Colloid 250a Residual Glue Overflow

300  基板                      300a 基板300的顶部表面300 Substrate 300a Top surface of substrate 300

300b 基板300的底部表面         310  半导体芯片300b bottom surface of substrate 300 310 semiconductor chip

320  电性绝缘层(焊垫罩幕)      320a 阶梯状空洞部分320 Electrical insulating layer (pad mask) 320a Ladder-shaped hollow part

350  封装胶体                  350a 残留溢胶350 Encapsulation Colloid 350a Residual Glue Overflow

400  基板                      400a 基板400的顶部表面400 Substrate 400a Top surface of substrate 400

400b 基板400的底部表面         410  半导体芯片400b bottom surface of substrate 400 410 semiconductor chip

421  第一电性绝缘层(焊垫罩幕)421 The first electrical insulation layer (pad mask)

421a 沟槽状空洞部分421a Trench-shaped cavity

422  第二电性绝缘层(焊垫罩幕)422 Second electrical insulation layer (pad mask)

430  焊球垫                    440  模具组430 Solder Ball Pad 440 Die Set

441  下模具                    441a 下模具441的上表面441 lower mold 441a upper surface of lower mold 441

442  上模具                    442a 模穴442 Upper mold 442a Cavity

442b 上模具442的下表面         450  封装胶体442b the lower surface of the upper mold 442 450 encapsulating colloid

450a 残留溢胶450a residual glue overflow

以下即配合附图的图5A至5C、图6A至6B、图7A至7B、和图8A至8C，分别详细描述说明本发明应用于封装各种不同型式的基板式半导体装置的实施例。5A to 5C, 6A to 6B, 7A to 7B, and 8A to 8C in conjunction with the accompanying drawings, respectively describe in detail the embodiments of the present invention applied to packaging various types of substrate-type semiconductor devices.

第一实施例(图5A至5C)以下即配合附图的图5A至5C，详细描述说明本发明的第一实施例。此实施例也是应用于封装一单晶片焊线型的基板式半导体装置，但可防止图1A至1C所示的已知技术中的溢胶问题。图5A至5C与图1A至1C中，相同的构件标示以相同的标号。First Embodiment ( FIGS. 5A to 5C ) The first embodiment of the present invention will be described in detail below, referring to FIGS. 5A to 5C of the accompanying drawings. This embodiment is also applied to packaging a single-chip wire-bonded substrate-type semiconductor device, but it can prevent the adhesive overflow problem in the prior art shown in FIGS. 1A to 1C . In FIGS. 5A to 5C and FIGS. 1A to 1C , the same components are marked with the same reference numerals.

请首先参阅图5A，此单芯片焊线型的基板式半导体装置的组成构件包括：(a)一基板100，其具有一正面100a和一背面100b；(b)一半导体芯片110，其安置于基板100的正面100a上方；(c)一第一电性绝缘层121，其形成于基板100的正面100a上，用以作为一顶部焊垫罩幕(solder mask，S/M)；(d)一第二电性绝缘层122，其形成于基板100的背面100b上，用以作为一底部焊垫罩幕；以及(e)多个电性连接垫130，其设置于基板100的背面100b上，并通过第二电性绝缘层122而互相电性隔离。Please first refer to FIG. 5A , the components of this single-chip wire-bonded substrate type semiconductor device include: (a) a substrate 100, which has a front surface 100a and a back surface 100b; (b) a semiconductor chip 110, which is placed on Above the front surface 100a of the substrate 100; (c) a first electrical insulation layer 121, which is formed on the front surface 100a of the substrate 100, used as a top solder pad mask (solder mask, S/M); (d) A second electrical insulating layer 122, which is formed on the back surface 100b of the substrate 100, used as a bottom pad mask; and (e) a plurality of electrical connection pads 130, which are disposed on the back surface 100b of the substrate 100 , and are electrically isolated from each other by the second electrical insulating layer 122 .

本发明的关键技术要点即在于形成一阶梯状空洞部分122a于底部的第二电性绝缘层122的周围边缘上，且使得此阶梯状空洞部分122a具有一预定的高度H和宽度W。基本上，此阶梯状空洞部分122a的高度H须大致为介于0.01mm与0.05mm之间，最佳为0.03mm，且宽度W须大致为介于0.4mm与1.2mm之间，但最佳为0.6mm。The key technical point of the present invention is to form a stepped hollow portion 122a on the peripheral edge of the second electrical insulating layer 122 at the bottom, and make the stepped hollow portion 122a have a predetermined height H and width W. Basically, the height H of the stepped hollow portion 122a must be roughly between 0.01mm and 0.05mm, preferably 0.03mm, and the width W must be roughly between 0.4mm and 1.2mm, but preferably is 0.6mm.

上述的尚未封装的半导体装置采用一特制的模具组140来进行封装胶体制造过程。此模具组140包含一下模具141和一上模具142；其中下模具141具有一平坦的上表面141a，而上模具142则具有一预定的模穴142a。请参阅图5B，接着即进行一封装胶体制造过程，其中将图5A所示的尚未封装的半导体装置安放于模具组140的一定位置上，亦即将底部的第二电性绝缘层122置放于下模具141的平坦表面141a上，并将上模具142压置于下模具141的上方，并使得半导体芯片110位于上模具142的模穴142a中。接着即可将一胶质封装材料，例如为环氧树脂，经由箭头M所指的通道而注入至模穴142a之中，由此而形成一封装胶体150，用以包覆半导体芯片110和基板100。The aforementioned unpackaged semiconductor device adopts a special mold set 140 for the encapsulant manufacturing process. The mold set 140 includes a lower mold 141 and an upper mold 142; wherein the lower mold 141 has a flat upper surface 141a, and the upper mold 142 has a predetermined cavity 142a. Please refer to FIG. 5B, and then proceed to a packaging compound manufacturing process, wherein the unpackaged semiconductor device shown in FIG. 5A is placed on a certain position of the mold set 140, that is, the second electrical insulating layer 122 at the bottom is placed on on the flat surface 141 a of the lower mold 141 , and press the upper mold 142 above the lower mold 141 , and make the semiconductor chip 110 be located in the mold cavity 142 a of the upper mold 142 . Then, a colloidal packaging material, such as epoxy resin, can be injected into the mold cavity 142a through the channel indicated by the arrow M, thereby forming a packaging colloid 150 for covering the semiconductor chip 110 and the substrate. 100.

于上述的封装胶体制造过程中，由于阶梯状空洞部分122a即相当于一狭窄化的流体通道，使得流入至此阶梯状空洞部分122a的胶质封装材料可更快速地吸收下模具141中的热量，而使得其黏度变大而减缓其流速；因此使得胶质封装材料不易进而溢流入第二电性绝缘层122与下模具141之间的压合间隙之中，亦即不易于第二电性绝缘层122和电性连接垫130上产生溢胶现象。In the above-mentioned encapsulation gel manufacturing process, since the stepped cavity portion 122a is equivalent to a narrowed fluid channel, the gel packaging material flowing into the stepped cavity portion 122a can absorb the heat in the lower mold 141 more quickly, And make its viscosity increase and slow down its flow rate; Therefore, it is difficult for the colloidal packaging material to overflow into the pressing gap between the second electrical insulation layer 122 and the lower mold 141, that is, it is not easy for the second electrical insulation Glue overflow occurs on the layer 122 and the electrical connection pad 130 .

请接着参阅图5C，于封装胶体制造过程完成之后，即可将完成封装的半导体装置自模具组140中取出。相比于图1A至1C所示的已知技术，本发明可使得底部的第二电性绝缘层122和电性连接垫130上不会存在有残留溢胶；因此可使得所制成的封装单元具有干净的外观，并同时使得电性连接垫130可确保其电性连接效果。Please refer to FIG. 5C , after the encapsulant manufacturing process is completed, the packaged semiconductor device can be taken out from the mold set 140 . Compared with the known technology shown in FIGS. 1A to 1C , the present invention can make the second electrical insulating layer 122 and the electrical connection pad 130 at the bottom no residual glue overflow; The unit has a clean appearance, and at the same time, the electrical connection pad 130 can ensure its electrical connection effect.

以下即配合附图的图6A至6B，详细描述说明本发明的第二实施例。此实施例也是应用于封装一堆叠双芯片焊线型的基板式半导体装置，但可防止图2A至2B所示的已知技术中的溢胶问题。图6A至6B与图2A至2B中，相同的构件标示以相同的标号。The second embodiment of the present invention will be described in detail below with reference to FIGS. 6A to 6B of the accompanying drawings. This embodiment is also applied to packaging a stacked two-chip wire-bonded substrate type semiconductor device, but it can prevent the adhesive overflow problem in the prior art shown in FIGS. 2A to 2B . In FIGS. 6A to 6B and FIGS. 2A to 2B , the same components are marked with the same reference numerals.

如图6A所示，此堆叠双芯片焊线型基板式半导体装置的组成构件包括：(a)一基板200，其具有一正面200a和一背面200b；(b)二个半导体芯片211、212，其以堆叠方式安置于基板200的正面200a上；以及(c)一电性绝缘层220，其形成于基板200的背面200b上，用以作为一底部焊垫罩幕。As shown in FIG. 6A , the components of the stacked two-chip wire-bonded substrate type semiconductor device include: (a) a substrate 200 having a front surface 200a and a back surface 200b; (b) two semiconductor chips 211, 212, They are stacked on the front surface 200a of the substrate 200; and (c) an electrically insulating layer 220 formed on the back surface 200b of the substrate 200 as a bottom pad mask.

本发明的关键技术要点即在于形成一阶梯状空洞部分220a于底部的电性绝缘层220的周围边缘上；且此阶梯状空洞部分220a具有一预定的高度H和宽度W。基本上，此阶梯状空洞部分220a的高度H须大致为介于0.01mm与0.05mm之间，最佳为0.03mm，且宽度W须大致为介于0.4mm与1.2mm之间，但最佳为0.6mm。The key technical point of the present invention is to form a stepped hollow portion 220a on the peripheral edge of the electrical insulating layer 220 at the bottom; and the stepped hollow portion 220a has a predetermined height H and width W. Basically, the height H of the stepped hollow portion 220a must be approximately between 0.01mm and 0.05mm, preferably 0.03mm, and the width W must be approximately between 0.4mm and 1.2mm, but most preferably is 0.6mm.

上述的尚未封装的半导体装置，采用与图5A至5C所示的实施例相同的模具组来进行一封装胶体制造过程，因此于此将不对其作重复的说明。于此封装胶体制造过程中，阶梯状空洞部分220a即相当于一狭窄化的流体通道；因此亦可达到与第一实施例相同的防溢胶效果。The unpackaged semiconductor device mentioned above adopts the same mold set as the embodiment shown in FIGS. 5A to 5C to carry out an encapsulant manufacturing process, so it will not be repeated here. During the manufacturing process of the encapsulant, the stepped hollow portion 220a is equivalent to a narrowed fluid channel; therefore, the same anti-overflow effect as that of the first embodiment can also be achieved.

如图6B所示，封装胶体制造过程完成之后，即可形成一封装胶体250，用以包覆基板200和半导体芯片211、212。但相比于图2A至2B所示的已知技术，本发明可使得底部的电性绝缘层220的露出表面上不会存在有溢胶现象。As shown in FIG. 6B , after the manufacturing process of the encapsulant is completed, an encapsulant 250 can be formed to cover the substrate 200 and the semiconductor chips 211 , 212 . However, compared with the prior art shown in FIGS. 2A to 2B , the present invention prevents glue overflow on the exposed surface of the bottom electrical insulating layer 220 .

以下即配合附图的图7A至7B，详细描述说明本发明的第三实施例。此实施例也是应用于封装一倒置芯片型半导体装置，但可防止图3A至3B所示的已知技术中的溢胶问题。图7A至7B与图3A至3B中，相同的构件标示以相同的标号。The following describes the third embodiment of the present invention in detail with reference to FIGS. 7A to 7B of the accompanying drawings. This embodiment is also applied to packaging an inverted chip type semiconductor device, but it can prevent the adhesive overflow problem in the prior art shown in FIGS. 3A to 3B . In FIGS. 7A to 7B and FIGS. 3A to 3B , the same components are marked with the same reference numerals.

如图7A所示，此倒置芯片型半导体装置的组成构件包括：(a)一基板300，其具有一正面300a和一背面300b；(b)一半导体芯片310，其以一倒置的覆晶方式安置于基板300的正面300a上；以及(c)一电性绝缘层320，其形成于基板300的背面300b上，用以作为一底部焊垫罩幕。As shown in Figure 7A, the components of this inverted chip type semiconductor device include: (a) a substrate 300, which has a front surface 300a and a back surface 300b; (b) a semiconductor chip 310, which is flip-chip in an inverted manner disposed on the front surface 300a of the substrate 300; and (c) an electrically insulating layer 320 formed on the rear surface 300b of the substrate 300 for use as a bottom pad mask.

本发明的关键技术要点即在于形成一阶梯状空洞部分320a于底部的电性绝缘层320的周围边缘上；且此阶梯状空洞部分320a具有一预定的高度H和宽度W。基本上，此阶梯状空洞部分320a的高度H须大致为介于0.01mm与0.05mm之间，最佳为0.03mm，且宽度W须大致为介于0.4mm与1.2mm之间，但最佳为0.6mm。The key technical point of the present invention is to form a stepped hollow portion 320a on the peripheral edge of the electrical insulation layer 320 at the bottom; and the stepped hollow portion 320a has a predetermined height H and width W. Basically, the height H of the stepped hollow portion 320a must be roughly between 0.01mm and 0.05mm, preferably 0.03mm, and the width W must be roughly between 0.4mm and 1.2mm, but preferably is 0.6mm.

上述的尚未封装的半导体装置，采用与图5A至5C所示的实施例相同的模具组来进行一封装胶体制造过程，因此于此将不对其作重复的说明。于此封装胶体制造过程中，阶梯状空洞部分320a即相当于一狭窄化的流体通道；因此亦可达到与第一实施例相同的防溢胶效果。The unpackaged semiconductor device mentioned above adopts the same mold set as the embodiment shown in FIGS. 5A to 5C to carry out an encapsulant manufacturing process, so it will not be repeated here. During the manufacturing process of the encapsulant, the stepped hollow portion 320a is equivalent to a narrowed fluid channel; therefore, the same anti-overflow effect as that of the first embodiment can also be achieved.

如图7B所示，封装胶体制造过程完成之后，即可形成一封装胶体350，用以包覆基板300和半导体芯片310。但相比于图3A至3B所示的已知技术，本发明可使得底部的电性绝缘层320的露出表面上不会存在有溢胶现象。As shown in FIG. 7B , after the manufacturing process of the encapsulant is completed, an encapsulant 350 can be formed to cover the substrate 300 and the semiconductor chip 310 . However, compared with the prior art shown in FIGS. 3A to 3B , the present invention prevents glue overflow on the exposed surface of the bottom electrical insulating layer 320 .

以下即配合附图的图8A至8C，详细描述说明本发明的第四实施例。此实施例也是应用于封装一球栅阵列型半导体装置，但可防止图4A至4C所示的已知技术中的溢胶问题。于图8A至8C与图4A至4C中，相同的构件标示以相同的标号。The fourth embodiment of the present invention is described in detail below with reference to FIGS. 8A to 8C of the accompanying drawings. This embodiment is also applied to packaging a BGA type semiconductor device, but it can prevent the adhesive overflow problem in the prior art shown in FIGS. 4A to 4C . In FIGS. 8A to 8C and FIGS. 4A to 4C , the same components are marked with the same reference numerals.

请首先参阅图8A，此球栅阵列型半导体装置的组成构件包括：(a)一基板400，其具有一正面400a和一背面400b；(b)一半导体芯片410，其安置于基板400的正面400a上；(c)一第一电性绝缘层421，其形成于基板400的正面400a上，用以作为一顶部焊垫罩幕；(d)一第二电性绝缘层422，其形成于基板400的背面400b上，用以作为一底部焊垫罩幕；以及(e)多个焊球垫(solder-ball pads)430，其形成于基板400的背面400b，并通过第二电性绝缘层422而互相电性隔离。Please first refer to FIG. 8A, the components of this ball grid array type semiconductor device include: (a) a substrate 400, which has a front surface 400a and a back surface 400b; (b) a semiconductor chip 410, which is placed on the front surface of the substrate 400 400a; (c) a first electrical insulating layer 421, which is formed on the front surface 400a of the substrate 400, used as a top pad mask; (d) a second electrical insulating layer 422, which is formed on and (e) a plurality of solder ball pads (solder-ball pads) 430, which are formed on the back surface 400b of the substrate 400 and are electrically insulated by the second Layer 422 is electrically isolated from each other.

上述的尚未封装的球栅阵列型半导体装置采用一特制的模具组440来进行封装胶体制造过程。此模具组440包含一下模具441和一上模具442；其中下模具441具有一平坦的上表面441a，而上模具442则具有一预定的模穴442a和一平坦的下表面442b。The aforementioned non-packaged BGA semiconductor device adopts a special mold set 440 for the encapsulant manufacturing process. The mold set 440 includes a lower mold 441 and an upper mold 442; wherein the lower mold 441 has a flat upper surface 441a, and the upper mold 442 has a predetermined cavity 442a and a flat lower surface 442b.

本发明的关键技术要点即在于形成一沟槽状空洞部分421a于第一电性绝缘层421中的一特定位置上；此特定位置亦即为将尚未封装的半导体装置固定于模具组440中的一定位置上时，第一电性绝缘层421、上模具442的下表面442b、与上模具442的模穴442a三者之间的交会的处。此沟槽状空洞部分421a具有一预定的高度H和宽度W。基本上，此沟槽状空洞部分421a的高度H须大致为介于0.01mm与0.05mm之间，最佳为0.03mm，且宽度W须大致为介于0.4mm与1.2mm之间，但最佳为0.6mm。The key technical gist of the present invention is to form a groove-shaped hollow portion 421a at a specific position in the first electrical insulating layer 421; In a certain position, the intersection of the first electrical insulation layer 421 , the lower surface 442 b of the upper mold 442 , and the mold cavity 442 a of the upper mold 442 . The groove-shaped hollow portion 421a has a predetermined height H and width W. As shown in FIG. Basically, the height H of the groove-shaped hollow portion 421a must be approximately between 0.01mm and 0.05mm, preferably 0.03mm, and the width W must be approximately between 0.4mm and 1.2mm, but most preferably The best is 0.6mm.

请接着参阅图8B，接着即进行一封装胶体制造过程，其中将图8A所示的尚未封装的半导体装置固定于模具组440的一定位置上，使得上模具442的下表面442b压置于第二电性绝缘层422上，并使得半导体芯片410置于上模具442的模穴442a中。接着即可将一胶质封装材料，例如为环氧树脂，经由箭头M所指的通道而注入至模穴442a之中，由此而形成一封装胶体450，用以包覆半导体芯片410和基板400。Please then refer to FIG. 8B , and then carry out an encapsulation compound manufacturing process, wherein the unencapsulated semiconductor device shown in FIG. 8A is fixed on a certain position of the mold set 440, so that the lower surface 442b of the upper mold 442 is pressed on the second on the electrical insulating layer 422 , and make the semiconductor chip 410 placed in the mold cavity 442 a of the upper mold 442 . Then, a colloidal packaging material, such as epoxy resin, can be injected into the mold cavity 442a through the channel indicated by the arrow M, thereby forming a packaging colloid 450 for covering the semiconductor chip 410 and the substrate. 400.

在上述的封装胶体制造过程中，沟槽状空洞部分421a即相当于一狭窄化的流体通道，使得流入至此沟槽状空洞部分421a的胶质封装材料可更快速地吸收上模具442中的热量，而使得其黏度变大而减缓其流速；因此使得注入的胶质封装材料不易进而溢流入第一电性绝缘层421与上模具442的下表面442b之间的压合间隙之中，亦即不易于第一电性绝缘层421的露出表面上产生溢胶现象。During the manufacturing process of the above-mentioned encapsulant, the groove-shaped cavity 421a is equivalent to a narrowed fluid channel, so that the gel encapsulation material flowing into the groove-shaped cavity 421a can absorb the heat in the upper mold 442 more quickly , so that its viscosity increases and its flow rate is slowed down; therefore, it is difficult for the injected colloidal packaging material to overflow into the pressing gap between the first electrical insulating layer 421 and the lower surface 442b of the upper mold 442, that is, It is not easy to produce glue overflow on the exposed surface of the first electrical insulation layer 421 .

请接着参阅图8C，于封装胶体制造过程完成之后，即可将完成封装的半导体装置自模具组440中取出。相比于图4A至4C所示的已知技术，本发明可使得基板顶部的第一电性绝缘层421的露出表面上不会存在有残留溢胶；因此可使得所制成的封装单元具有干净的外观。Please refer to FIG. 8C , after the encapsulant manufacturing process is completed, the packaged semiconductor device can be taken out from the mold set 440 . Compared with the known technology shown in FIGS. 4A to 4C , the present invention can make the exposed surface of the first electrical insulating layer 421 on the top of the substrate no residual glue; therefore, the manufactured package unit can have clean look.

在前面的数个实施例中，本发明系分别应用于四种不同型式的基板式半导体装置。广义而言，本发明所适用的半导体装置为包括一基板、至少一半导体芯片安置于该基板、以及至少一电性绝缘层形成于该基板的一表面上(可为顶部表面或底部表面)，藉以防止该电性绝缘层上存在溢胶现象。In the above several embodiments, the present invention is respectively applied to four different types of substrate-based semiconductor devices. Broadly speaking, the semiconductor device to which the present invention is applicable includes a substrate, at least one semiconductor chip disposed on the substrate, and at least one electrically insulating layer formed on a surface (which may be the top surface or the bottom surface) of the substrate, In order to prevent the glue overflow phenomenon on the electrical insulation layer.

本发明的特点在于形成一延伸的空洞部分于基板表面上的电性绝缘层中的一特定位置上；该特定位置即为该基板式半导体装置固定于模具中的一定位置时，其中的电性绝缘层、模具的实体部分、与模具的模穴三者之间的交会的处。于封装胶体制造过程中，由于此空洞部分即相当于一狭窄化的流体通道，使得流入至此空洞部分的胶质封装材料可更快速地吸收模具中的热量，而使得其黏度变大而减缓其流速；因此使得胶质封装材料不易进而溢流入电性绝缘层与模具之间的压合间隙之中，亦即不易于电性绝缘层的露出表面上产生溢胶现象。The feature of the present invention is to form an extended hollow portion at a specific position in the electrical insulating layer on the surface of the substrate; The intersection of the insulating layer, the solid part of the mold, and the cavity of the mold. During the manufacturing process of the encapsulant, since the cavity is equivalent to a narrowed fluid channel, the colloidal encapsulation material flowing into the cavity can absorb the heat in the mold more quickly, making its viscosity larger and slowing down. The flow rate; therefore, it is difficult for the gel packaging material to overflow into the pressing gap between the electrical insulating layer and the mold, that is, it is not easy to produce glue overflow on the exposed surface of the electrical insulating layer.

以上所述仅为本发明的较佳实施例而已，并非用以限定本发明的实质技术内容的范围。本发明的实质技术内容系广义地定义所述的权利要求中。任何他人所完成的技术实体或方法，若是与所述的权利要求所定义者为完全相同、或是为一种等效的变更，均将被视为涵盖于此权利要求范围之中。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the substantive technical content of the present invention. The essential technical content of the present invention is defined broadly in the following claims. Any technical entity or method accomplished by others, if it is exactly the same as that defined in the claims, or if it is an equivalent change, will be deemed to be covered by the scope of the claims.

Claims (12)

1. substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one semiconductor chip are placed in this substrate and at least one electrical insulation layer is formed on the surface of this substrate;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this hollow sectors fluid passage, and its flow velocity will be slowed down and be difficult for overflow to the pressing gap between this electrical insulation layer and this set of molds, therefore prevents the glue phenomenon of overflowing.
2. substrate-type semiconductor device packing method as claimed in claim 1, wherein in step (2), the height of the hollow sectors in this electrical insulation layer is between 0.01mm and 0.05mm, and width then is between 0.4mm and 1.2mm.
3. substrate-type semiconductor device packing method as claimed in claim 2, wherein the height of the hollow sectors in this electrical insulation layer is 0.03mm, width is 0.6mm.
4. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is a single-chip bonding wire type.
5. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is to pile up twin-core sheet bonding wire type.
6. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is that an inversion is chip-shaped.
7. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is a ball grid array type.
8. substrate-type semiconductor device packing method as claimed in claim 1, wherein the hollow sectors of this extension is one to be positioned at the stepped hollow sectors on the surrounding edge of this electrical insulation layer.
9. substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one electrical insulation layer are formed on the top surface of this substrate and at least one semiconductor chip is placed on this electrical insulation layer;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of channel form hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this channel form hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this channel form hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this channel form hollow sectors fluid passage, its flow velocity will be slowed down and will be difficult for overflow to this electrical insulation layer and this set of molds pressing gap between the two, therefore prevent the glue phenomenon of overflowing.
10. substrate-type semiconductor device packing method as claimed in claim 9, wherein in step (2), the height of this channel form hollow sectors is between 0.01mm and 0.05mm, and width then is between 0.4mm and 1.2mm.
11. substrate-type semiconductor device packing method as claimed in claim 10, wherein the height of this channel form hollow sectors is 0.03mm, and width is 0.6mm.
12. substrate-type semiconductor device packing method as claimed in claim 9, wherein this substrate-type semiconductor device is a ball grid array type.
CNB001345451A 2000-12-11 2000-12-11 Substrate type semiconductor device packaging method capable of preventing glue overflow Expired - Lifetime CN1163953C (en)

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CN100433304C (en) * 2004-09-07 2008-11-12 日月光半导体制造股份有限公司 Substrate strip suitable for transparent packaging
US7588999B2 (en) * 2005-10-28 2009-09-15 Semiconductor Components Industries, Llc Method of forming a leaded molded array package
KR101293024B1 (en) * 2011-11-11 2013-08-05 에스엔유 프리시젼 주식회사 Apparatus for Manufacturing Flat panel display
CN103367264B (en) * 2012-03-27 2016-08-31 南亚科技股份有限公司 A package carrier board capable of avoiding glue overflow

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