CN116387335A - An image sensor and its manufacturing method - Google Patents

Abstract

The invention provides an image sensor and a method for manufacturing the same, wherein the image sensor comprises: the pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas; the dielectric layer is arranged on the pixel array structure; the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction area, and the side wall of the light-transmitting structure, which is close to the center of the pixel array structure, is a slope structure; the micro lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the inclined direction of the slope structure; and a plurality of metal wirings disposed in the dielectric layer, the metal wirings being offset in a direction in which the slope structure is inclined. The invention provides an image sensor and a manufacturing method thereof, which can reduce the parasitic light response of the outer ring of a pixel array in the image sensor.

Description

An image sensor and its manufacturing method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to an image sensor and a manufacturing method thereof.

Background technique

In the image sensor, the electronic shutter image sensor uses electronic means to control the exposure time of the image sensor, the shutter speed is high and there is no flare phenomenon and shutter sound. In the global exposure electronic shutter image sensor, the global exposure of the charge domain and the parasitic light response (Parasitic Light Sensitivity, PLS) of the charge storage node are very important indicators. Among them, the parasitic light response is the stray light response and the photodiode response received by the charge storage node when there is no signal.

Since the image sensor lens has a chief optical axis angle (Chief Ray Angle, CRA), the incident light angles are different at different positions of the pixel array, and it is difficult to reduce the parasitic light response of the outer circle of the image sensor pixel array.

Contents of the invention

The object of the present invention is to provide an image sensor and its manufacturing method, which can reduce the spurious light response of the outer circle of the pixel array in the image sensor.

In order to solve the problems of the technologies described above, the present invention is achieved through the following technical solutions:

The invention provides an image sensor, comprising:

A pixel array structure, the pixel array includes a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas;

a medium layer disposed on the pixel array structure;

The light-transmitting structure passes through the medium layer and is connected to the photoelectric reaction area, and the sidewall of the light-transmitting structure close to the center of the pixel array structure is a slope structure;

a microlens disposed on the light-transmitting structure, the microlens covers the photoelectric reaction area, and the microlens is offset toward the direction in which the slope structure is inclined; and

The multi-layer metal wiring is arranged in the dielectric layer, and the metal wiring is shifted toward the inclined direction of the slope structure.

In an embodiment of the present invention, there is a main offset distance between the central axis of the microlens and the symmetry plane of the photoelectric reaction area, and a secondary offset distance between the metal wiring and the central axis of the storage area, Wherein the slave offset distance is 1/3-19/20 of the main offset distance.

In an embodiment of the present invention, among the multiple layers of the metal wiring, the metal wiring on the top layer is offset toward the direction in which the slope structure is inclined.

In an embodiment of the present invention, among the multi-layer metal wirings, the metal wirings on the top layer and the metal wirings on the second top layer are shifted toward the inclined direction of the slope structure.

In an embodiment of the present invention, the pixel array structure is provided with a gate, the gate is located between the photoelectric reaction area and the storage area, and the gate covers the storage area and part of the storage area. The photoelectric reaction zone.

In an embodiment of the present invention, the orthographic projection of the metal wiring on the pixel array structure is located in the storage region and on the gate structure.

In an embodiment of the present invention, the image sensor includes a color filter layer and a flat layer, the color filter layer is arranged on the light-transmitting structure, and the flat layer is arranged on the color filter layer and the flat layer between the microlenses.

In an embodiment of the present invention, the refractive index of the transparent structure is greater than the refractive index of the medium layer.

The invention provides a method for manufacturing an image sensor, comprising the following steps:

A pixel array structure is provided, the pixel array includes a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas;

forming a dielectric layer on the pixel array structure;

forming multilayer metal wiring in the dielectric layer;

Forming a light-transmitting structure on the photoelectric reaction area, the light-transmitting structure passing through the medium layer, and connecting with the photoelectric reaction area, the side wall of the light-transmitting structure close to the center of the pixel array structure is a slope structure, wherein the metal wiring is offset toward a direction in which the ramp structure is inclined; and

A micro-lens is formed on the light-transmitting structure, the micro-lens covers the photoelectric reaction area, and the micro-lens deviates toward the inclined direction of the slope structure.

In an embodiment of the present invention, the step of forming the light-transmitting structure includes:

Etching the dielectric layer to form a light-transmitting groove;

Etching the groove wall of the light-transmitting groove multiple times to form a stepped structure;

burying the step structure to form the slope structure in the light-transmitting groove; and

filling the light-transmitting groove to form the light-transmitting structure.

In an embodiment of the present invention, the step of embedding the stepped structure includes:

forming a buried layer in the light-transmitting trench and on the dielectric layer; and

Etching the buried layer to expose the photoelectric reaction area.

As mentioned above, the present invention provides an image sensor and its manufacturing method, which can increase the response intensity of the photoelectric reaction region in the image sensor and reduce the parasitic photoresponse of the charge storage node. And according to the image sensor and its manufacturing method provided by the present invention, the amount of incident light received by the pixel units at different positions in the pixel array can be improved, and the parasitic light response of the outer circle of the pixel array of the image sensor can be avoided, thereby improving the light output of the image sensor. Signal Processing Accuracy.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that are required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of the principal optical axis angle in an embodiment of the present invention.

Fig. 2 is a schematic diagram of the structure of the photoelectric reaction area and storage area in an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of forming a first metal wiring in an embodiment of the present invention.

FIG. 4 is a schematic diagram of a metal interconnection structure in an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of a light-transmitting groove in an embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a light-transmitting groove in another embodiment of the present invention.

FIG. 7 is a schematic diagram of wall surface distribution of dielectric layer etching in an embodiment of the present invention.

FIG. 8 is a schematic diagram of forming a first stepped structure in an embodiment of the present invention.

FIG. 9 is a schematic diagram of forming a second stepped structure in an embodiment of the present invention.

FIG. 10 is a schematic diagram of forming a first stepped structure in another embodiment of the present invention.

FIG. 11 is a schematic diagram of forming a second stepped structure in an embodiment of the present invention.

FIG. 12 is a schematic structural diagram of a buried layer in an embodiment of the present invention.

Fig. 13 is a schematic diagram of a second slope structure in an embodiment of the present invention.

FIG. 14 is a schematic diagram of a light-transmitting structure in an embodiment of the present invention.

FIG. 15 is a schematic structural diagram of an image sensor in an embodiment of the present invention.

FIG. 16 is a schematic top view of a microlens and a light-transmitting structure in an embodiment of the present invention.

FIG. 17 is a schematic structural diagram of an image sensor when the principal optical axis angle is 0 in an embodiment of the present invention.

FIG. 18 is a circuit diagram of a charge domain pixel in an embodiment of the present invention.

In the figure: 10, pixel array; 11, pixel unit; 20, lens; 100, substrate; 101, photoelectric reaction area; 102, storage area; 103, gate; 200, metal interconnection structure; 201, dielectric layer; 202, metal wiring; 2021, first metal wiring; 2022, second metal wiring; 2023, third metal wiring; 300, light-transmitting groove; 400, step structure; 401a, first photoresist layer; 401b, second Photoresist layer; 402a, third photoresist layer; 402b, fourth photoresist layer; 500, buried layer; 600, light-transmitting structure; 601, light-transmitting layer; 700, functional layer; 800, microlens.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Electronic shutter image sensors are classified into rolling shutter type and global exposure type image sensors. In the rolling electronic shutter image sensor, the exposure time of each row in the pixel array 10 is different, so there will be smear when shooting high-speed objects. The present invention provides a global exposure type electronic shutter image sensor, which completes the exposure of each row of the pixel array 10 at the same time, so as to solve the problem of smear when shooting high-speed objects. Moreover, the global exposure image sensor of this embodiment can be widely applied to vehicles, industries, road monitoring and high-speed cameras, and has a wide range of applications. In this embodiment, the image sensor may be a CMOS image sensor. Please refer to FIG. 1 , the CMOS image sensor includes a pixel array 10 and a lens assembly 20 . The pixel array 10 includes a plurality of pixel units 11 . The incident light passes through the lens assembly 20 and is focused on the pixel unit 11 . Wherein, the main optical axis angle is the maximum angle of light focused on the pixel unit 11 , as shown in FIG. 1 . As shown in FIG. 1 , different pixel units 11 have different incident light angles. The principal optical axis angle β of the lens assembly 20 is shown in FIG. 1 . According to the image sensor and its manufacturing method provided by the present invention, errors caused by different angles of incident light can be eliminated.

Referring to FIG. 2 , the present invention provides a manufacturing method of an image sensor. First, a substrate 100 is provided, and dopant ions are implanted into the substrate 100 to form a photoelectric reaction region 101 and a charge storage region 102 . Wherein, the substrate 100 is, for example, a silicon substrate forming a semiconductor structure. The substrate 100 may include a substrate and a silicon layer disposed on the substrate, such as silicon (Si), silicon carbide (SiC), sapphire (Al ₂ O ₃ ), gallium arsenide (GaAs), lithium aluminate (LiAlO ₂ ) and other semiconductor substrate materials, and a silicon layer is formed on the substrate. The present invention does not limit the material and thickness of the substrate 100 . In this embodiment, for example, P-type dopant, such as boron ions, can be implanted into the substrate 100 to form a P-type semiconductor. And then implant N-type dopant, such as phosphorous ions, into the substrate 100 to form a plurality of doped regions. In this embodiment, a plurality of photoelectric reaction regions 101 and a plurality of charge reaction regions 102 are arranged in the substrate 100 , and the photoelectric reaction regions 101 and the charge reaction regions 102 are distributed at intervals. Wherein, the ion doping concentrations of the photoelectric reaction region 101 and the charge reaction region 102 are different. The present invention does not limit the specific ion concentration of the photoelectric reaction region 101 and the charge reaction region 102 . The present invention does not limit the formation order of the photoelectric reaction region 101 and the plurality of charge reaction regions 102 . Wherein, the ion implantation depths of the photoelectric reaction region 101 and the charge reaction region 102 may be different, and the present invention does not limit the specific ion implantation depths of the photoelectric reaction region 101 and the charge reaction region 102 .

Referring to FIGS. 2 to 4 , in an embodiment of the present invention, a gate 103 is formed on a substrate 100 , and a metal interconnection structure 200 is formed on the substrate 100 . Wherein, a polysilicon layer is formed on the substrate 100 by chemical vapor deposition (Chemical Vapor Deposition, CVD), and the polysilicon layer is etched to form the gate 103 . In this embodiment, the gate 103 may cover part of the charge storage region 102 , or completely cover the charge storage region 102 . Moreover, the gate 103 covers part of the photoelectric reaction region 101 . Next, silicon oxide or tetraethyl orthosilicate (TEOS) is deposited on the substrate 100 by chemical vapor deposition or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), etc., to form a dielectric layer 201 . Next, the dielectric layer 201 is etched to form a wiring trench on the dielectric layer 201 , and the wiring trench is filled to form a metal wiring 202 . In this embodiment, the metal wiring 202 may be metal such as copper or aluminum. Wherein, the metal interconnection structure 200 includes a plurality of metal interconnection layers, and the metal interconnection layers include a dielectric layer 201 and a metal wiring 202 . The present invention does not limit the number of metal interconnection layers. In this embodiment, for example, three metal interconnection layers are used to illustrate the technical features of the present invention. As shown in FIG. 4 , the metal interconnection structure 200 includes a first metal wiring 2021 , a second metal wiring 2022 and a third metal wiring 2023 .

Referring to FIG. 4 , in an embodiment of the present invention, the orthographic projection of the metal wiring 202 on the substrate 100 is located in the charge storage region 102 . Wherein, the metal wiring 202 has a symmetrical metal wiring structure, as shown in FIG. 4 . In each metal wiring 202 , the metal wiring structure corresponding to the charge storage region 102 is a symmetrical structure. Wherein, the charge storage region 102 has a central axis a of the figure, and the first metal wiring 2021 is symmetrical about the central axis a of the figure. There is a first offset distance d ₁ between the symmetry axis b of the second metal wiring 2022 and the central axis a of the figure. There is a second offset distance d ₂ between the symmetry axis c of the third metal wiring 2023 and the central axis a of the figure. The present invention does not limit the offset direction of the second metal wiring 2022 and the third metal wiring 2023 . In the present invention, the third metal wiring 2023 is a metal top layer, and the second metal wiring is a metal subtop layer. In other embodiments of the present invention, when the number of metal interconnection layers is changed, the second top metal layer has a first from-offset distance d ₁ , and the top metal layer has a second from-offset distance d ₂ .

Referring to FIG. 5 to FIG. 7 , in an embodiment of the present invention, the dielectric layer 201 is etched to form a light-transmitting trench 300 . The light-transmitting trench 300 is connected to the photoelectric reaction area 101 . In this embodiment, a part of the dielectric layer 201 is etched by plasma gas or etching solution, and etched to the surface of the substrate 100 to form the light guiding groove 300 as shown in FIG. 5 . In another embodiment of the present invention, part of the dielectric layer 201 is removed by etching, and part of the dielectric layer 201 covering the photoelectric reaction region 201 is left to form the light guiding groove 300 as shown in FIG. 6 . The present invention does not limit the depth of the light guiding groove 300 . Wherein, there is a reserved distance d ₃ between the groove wall of the light guiding groove 300 and the first metal wiring 2021 . The reserved distance is greater than, for example, 0.1 μm, so as to reserve a processing allowance for subsequent processes. When forming the light-transmitting trench 300 , the gate 200 may be partially exposed in the light-transmitting trench 300 , or the gate 200 may be completely covered in the dielectric layer 201 , which is not limited in the present invention. Wherein, after the metal interconnection layer is divided by the light-transmitting groove 300, a plurality of metal interconnection layers are distributed in a linear array.

Referring to FIGS. 5 to 10 , in an embodiment of the present invention, the sidewalls of the light-transmitting trenches 300 are etched to form a plurality of stepped structures 400 . Wherein, the sidewall of the light-transmitting trench 300 close to the center point C of the pixel array 10 is etched. Specifically, as shown in FIG. 7 , taking the pixel unit 11 located at the four corners of the pixel array 10 as an example, in the pixel unit 11, the four side walls of the light-transmitting structure 600 are wall surface e ₁ , wall surface e ₂ , and wall surface e _{3 .} and wall e ₄ . Wherein, the wall surface e ₁ and the wall surface e ₂ are close to the center point C of the pixel array 10 , so in the etching step, the wall surface e ₁ and the wall surface e ₂ are etched to form the stepped structure 400 . The wall surface e ₃ and the wall surface e ₄ are far away from the center point C of the pixel array 10 , so they remain as vertical planes during the etching step. It should be noted that in the actual etching process, due to process errors and parameters, the wall e ₃ and the wall e ₄ may not be strictly vertical planes. Wherein, the center point C of the pixel array 10 is the graphic center of the entire pixel array 10 .

Please refer to FIG. 5, FIG. 7 to FIG. 9, in an embodiment of the present invention, in the step of forming the stepped structure 400, firstly, a first Photoresist layer 401a. In this embodiment, the first photoresist layer 401 a covers part of the dielectric layer 201 , the bottom wall and one side wall of the light-transmitting trench 300 . Wherein, the first photoresist layer 401 a covers the groove wall of the light-transmitting groove 300 away from the center C of the pixel array 10 . As shown in FIG. 7 and FIG. 8 , the first photoresist layer 401a covers the wall surface _e3 and the wall surface _e4 . In this embodiment, the first photoresist layer 401 a covers part of the first dielectric layer 201 , exposing the region where the stepped structure 400 is to be formed, as shown in FIG. 8 . Then, the exposed sidewall of the light-transmitting trench 300 is etched by plasma gas or etching solution to form the first stepped structure 400 . Next, the first photoresist layer 401a is removed, and the second photoresist layer 401b is formed on the bottom wall of the light transmission trench 300 , one side wall of the light transmission trench 300 , the step structure 400 and part of the dielectric layer 201 . Wherein, the second photoresist layer 401 a covers the sidewall of the light-transmitting groove 300 away from the center point C of the pixel array 10 . Wherein, the second photoresist layer 401 a covers part of the first dielectric layer 201 , exposing the area where the second stepped structure 400 is to be formed. Then, the exposed sidewall of the light-transmitting trench 300 is etched by plasma gas or etching solution to form a second stepped structure 400 . By analogy, by adjusting the coverage area of the photoresist, a plurality of stepped structures 400 can be formed on the sidewall of the light-transmitting trench 300 close to the center C of the pixel array 10 . In this embodiment, the width of the stepped structure 400 is, for example, 0.01 μm˜0.3 μm.

Please refer to FIG. 6 and FIG. 7, and FIG. 10 and FIG. 11, in another embodiment of the present invention, in the step of forming the step structure 400, firstly, on the groove wall of the light-transmitting groove 300 and part of the dielectric layer 201 is formed on the third photoresist layer 402a. In this embodiment, the third photoresist layer 402a covers the dielectric layer 201 and one sidewall of the light-transmitting trench 300 . Specifically, the third photoresist layer 402 a covers the sidewall of the light-transmitting groove 300 away from the center C of the pixel array 10 . Wherein, the third photoresist layer 402 a covering the walls of the light-transmitting trench 300 is connected to the bottom wall of the light-transmitting trench 300 . Then, the exposed sidewall of the light-transmitting trench 300 is etched by plasma gas or etching solution to form the first stepped structure 400 . After the first stepped structure 400 is formed, the light-transmitting groove 300 extends to the surface of the photoelectric reaction region 101 , and the light-transmitting groove 300 is connected to the photoelectric reaction region 101 . Then remove the third photoresist layer 402a, and form a fourth photoresist layer 402b on the dielectric layer 201, on the bottom wall of the light-transmitting groove 300, on one side wall of the light-transmitting groove 300, and on part of the stepped structure 400 . The fourth photoresist layer 402b covers part of the step surface of the step structure 400 , exposing the area where the next step structure 400 is to be formed. Then, the exposed sidewall of the light-transmitting trench 300 is etched by plasma gas or etching solution to form a second stepped structure 400 . By analogy, by adjusting the coverage area of the photoresist, a plurality of stepped structures 400 can be formed on the sidewall of the light-transmitting trench 300 close to the center C of the pixel array 10 . In this embodiment, the width of the stepped structure 400 is, for example, 0.01 μm˜0.3 μm.

Referring to FIG. 9 , FIG. 11 and FIG. 12 , in an embodiment of the present invention, after forming a plurality of stepped structures 400 , a buried layer 500 is formed on the dielectric layer 201 and in the light-transmitting trench 300 . In this embodiment, silicon oxide is deposited on the dielectric layer 201 and in the transparent trench 300 by chemical vapor deposition to form the buried layer 500 . Wherein, the buried layer 500 and the dielectric layer 201 can be made of the same material, such as silicon oxide. And the thickness of the buried layer 500 is greater than the maximum step height of the stepped structure 400 . In this embodiment, the buried layer 500 covers the dielectric layer 201 , the walls of the light-transmitting trench 300 , and the stepped structure 400 . In this embodiment, the stepped structure 400 is buried and leveled by depositing silicon oxide, and the silicon oxide is continuously deposited to form the first slope structure 501 as shown in FIG. 12 . The present invention does not limit the number of the stepped structures 400 . And in the present invention, the slope of the first slope structure 501 can be adjusted according to the number and width of the step structures 400 . Specifically, when the number of the step structures 400 is the same, the larger the width of the step structures 400 is, the larger the slope of the first slope structure 501 is. In the case that the step structures 400 have the same width, the more the step structures 400 are, the larger the slope of the first slope structure 501 is.

Referring to FIG. 12 and FIG. 13 , in an embodiment of the present invention, part of the buried layer 500 and part of the dielectric layer 201 are etched to form a second slope structure 502 . In this embodiment, part of the buried layer 500 and part of the dielectric layer 201 are removed by plasma gas or etching solution, so that the surface of the photoelectric reaction region 101 and the surface of the metal top layer are exposed. In this embodiment, part of the buried layer 500 and part of the dielectric layer 201 are removed to expose the surface of the third metal wiring 2023 . The second slope structure 502 is formed after the first slope structure 501 is etched. In this embodiment, the slope of the second slope structure 502 is greater than that of the first slope structure 501 . Wherein, the buried layer 502 and the dielectric layer 201 are made of the same material, and for the convenience of illustrating the shape of the first slope structure 501, the buried layer 502 and the dielectric layer 201 are displayed together, as shown in FIG. 12 . In this embodiment, after the second slope structure 502 is formed, the dielectric layer 201 covers the gate 200 . In other embodiments of the present invention, after the second slope structure 502 is formed, the dielectric layer 201 may cover part of the gate 200 , and another part of the gate 200 may be exposed in the light-transmitting trench 300 .

Referring to FIG. 13 and FIG. 14 , in an embodiment of the present invention, the light-transmitting groove 300 is filled to form a light-transmitting structure 600 . In this embodiment, a high refractive index material, such as silicon nitride, is deposited in the light-transmitting trench 300 by chemical vapor deposition to form the light-transmitting structure 600 . Wherein, in the step of forming the light-transmitting structure 600, after the light-transmitting groove 300 is filled, the high-refractive-index material can be continuously deposited so that the high-refractive-index material covers the dielectric layer 201 and the metal top layer to form the light-transmitting layer 601 . The present invention does not limit the thickness of the transparent layer 601 . Wherein, the refractive index difference between the light-transmitting structure 600 and the medium layer 201 is large. When the light is incident according to the main optical axis angle, the light will be totally reflected when it touches the slope surface of the second slope structure 502 . Another part of the light directly incident on the storage area 102 will be blocked by the metal wiring. Therefore, the light will not reach the storage area 102, avoiding excess signal volume in the storage area 102, thereby improving the signal accuracy of the image sensor.

14 to 16, in one embodiment of the present invention, after the light-transmitting structure 600 and the light-transmitting layer 601 are formed, a functional layer 700 is formed on the light-transmitting layer 601, and microlenses are arranged on the functional layer 700 800. In this embodiment, the functional layer 700 includes a color filter layer (Color Filter, CF) and a flat layer. Wherein the color filter layer is arranged on the transparent layer 601, in order to balance and stabilize the placement of the color filters, a dielectric material can be arranged between adjacent color filters. The flat layer is disposed on the color filter layer. Wherein the flat layer may be polyimide to stabilize the placement of the microlens 800 . The microlens 800 can be used to condense the light so that the incident light can pass through the light-transmitting structure 600 and reach the photoelectric reaction area 101 . In this embodiment, the incident light reaches the microlens 800 and is refracted. Wherein, when the incident light is incident at the principal optical axis angle β, the incident light is totally reflected when it touches the slope surface of the second slope structure 502 , and then returns to the light-transmitting structure 600 and reaches the photoelectric reaction area 101 .

Please refer to Fig. 7, Fig. 14 to Fig. 16, in one embodiment of the present invention, the central axis of the microlens 800 and the symmetry axis of the photoelectric reaction area 101 have a main transverse offset distance x and a main longitudinal offset distance y . In this embodiment, as shown in FIG. 16 , in the pixel array 10, the first linear arrangement direction of the pixel array 10 is taken as the X axis, and the second linear arrangement direction of the pixel array 10 is taken as the Y axis, wherein the first linear arrangement direction The arrangement direction and the second linear arrangement direction are perpendicular to each other. Comparing the positions of the central axes of the microlens 800 and the photoelectric reaction area 101 , the microlens 800 is offset by the main lateral offset distance x and the main vertical offset distance y relative to the photoelectric reaction area 101 , as shown in FIG. 16 . The offset microlens 800 can adapt to the incidence of light at a specific angle, and the microlens 800 can be translated toward a position away from the center of the pixel array 10 . Corresponding to the offset of the microlens 800 , the metal top layer and the metal sub-top layer may be offset, or only the metal top layer may be offset. Wherein, the offset direction of the metal top layer is consistent with the offset direction of the microlens. And in the X-axis direction and the Y-axis direction, the offset of the metal top layer or the metal sub-top layer is respectively related to the lateral main offset distance x and the longitudinal main offset distance y. Specifically, the offset of the metal top layer is, for example, 1/3˜19/20 of the offset of the microlens, and the offset of the metal subtop layer is, for example, 1/3˜19/20 of the offset of the microlens. Corresponding to the offset of the metal top layer and the metal sub-top layer, the wall surface of the light-transmitting trench 300 near the center of the pixel array 10 has a second slope structure 502 . Corresponding to the second slope structure 502 , the position of the light-transmitting structure 600 is shown in the dotted-line block diagram of FIG. 16 . Wherein, the light-transmitting structure 600 is arranged on the photoelectric reaction area 101 , and the wall connecting the light-transmitting structure 600 and the second slope structure 502 is a slope, as shown by the outer dotted line box in FIG. 16 . In this embodiment, the slopes of the light-transmitting structure 600 in the X-axis direction and the Y-axis direction may be different or the same. In addition, in different pixel units 11 , by changing the width of the stepped structure 400 , the gradient of the slope of the light-transmitting structure 600 can also be different.

Referring to FIG. 15 and FIG. 17 , in one embodiment of the present invention, when the main optical axis angle is 0, the offset of the microlens 800 is 0. Correspondingly, the first offset distance of the metal subtop layer is 0, and the second offset distance of the metal top layer is 0. The incident light is refracted through the microlens 800 , and then passes through the functional layer 700 , the transparent layer 601 , and the transparent structure 600 to reach the photoelectric reaction area 101 . Wherein, when the main optical axis angle is greater than 0, the lateral main offset distance of the microlens 800 is x, and the longitudinal main offset distance is y. When the incident light passes through the microlens 800 , part of the incident light is blocked by the metal top layer and reflected, and another part of the incident light passes through the dielectric layer 201 and reaches the storage area 102 , causing a parasitic light response in the storage area 102 . Therefore, in the present invention, when the lateral main offset distance of the microlens 800 is x, the vertical main offset distance is y. The metal top layer has a second from offset distance, and the metal subtop layer has a first from offset distance. Moreover, the second slope structure 502 is set on the dielectric layer 201 , as shown in FIG. 15 , the incident light is difficult to enter the dielectric layer 201 , and the parasitic optical response of the storage area 102 is avoided.

Please refer to FIG. 17 and FIG. 18 . In an embodiment of the present invention, FIG. 18 provides a circuit diagram of a globally exposed charge domain pixel. The charge domain pixel circuit diagram shown in FIG. 18 is based on the manufacturing method of the image sensor of the present invention. And the pixel circuit of the image sensor provided by the present invention can be laid out as shown in FIG. 18 . And as shown in FIG. 18 , the pixel circuit includes a first transfer transistor M1 , a second transfer transistor M2 , a global reset transistor M3 , a reset transistor M4 , a source follower transistor M5 and a selection transistor M6 , as well as a storage capacitor C and a photodiode PD. In this embodiment, the photodiode PD corresponds to the photoelectric reaction region 101 , and the storage capacitor C corresponds to the storage region 102 . And in the pixel circuit provided by the present invention, one end of the global reset transistor M3 is electrically connected to the power supply V _DD . The other end of the global reset transistor M3 is electrically connected to one end of the photodiode PD and one end of the first transfer transistor M1. The other end of the photodiode PD is grounded. In this embodiment, the other end of the first transmission tube M1 is electrically connected to one end of the second transmission tube M2 and one end of the storage capacitor C. The other end of the storage capacitor C is grounded. In this embodiment, the other end of the second transmission transistor M2 is electrically connected to one end of the reset transistor M4 and the driving end of the source follower transistor M5. Wherein, the other end of the reset transistor M4 is electrically connected to the power supply V _DD . In this embodiment, one end of the source follower transistor M5 is electrically connected to one end of the selection transistor M6, and the other end of the source follower transistor M5 is electrically connected to the power supply V _DD . The other end of the selection tube M6 is used as the output end of the pixel circuit. In this embodiment, the first transmission transistor M1, the second transmission transistor M2, the global reset transistor M3, the reset transistor M4, the source follower transistor M5 and the selection transistor M6 are Metal-Oxide-Semiconductor Field Effect Transistors (Metal-Oxide-Semiconductor Field Effect Transistors). Field-Effect Transistor, MOSFET).

The invention provides an image sensor and a manufacturing method thereof, wherein the image sensor includes a pixel array structure, a medium layer, a light-transmitting structure, microlenses and multilayer metal wiring. Wherein, the pixel array structure includes a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas. The medium layer is arranged on the pixel array structure. The light-transmitting structure passes through the medium layer and connects with the photoelectric reaction area, and the sidewall of the light-transmitting structure away from the center of the pixel array structure is a slope structure. The micro-lens is arranged on the light-transmitting structure, the micro-lens covers the photoelectric reaction area, and the micro-lens deviates toward the inclined direction of the slope structure. The multi-layer metal wiring is arranged in the dielectric layer, and the metal wiring is shifted toward the inclined direction of the slope structure. According to the image sensor provided by the present invention, the amount of incident light received by the pixel units at different positions in the pixel array can be improved, and the spurious light response of the outer circle of the pixel array of the image sensor can be avoided, thereby improving the optical signal processing accuracy of the image sensor.

The embodiments of the present invention disclosed above are only used to help explain the present invention. The examples do not exhaust all details nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the contents of this specification. This description selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (11)

1. An image sensor, comprising:

the pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, wherein the photoelectric reaction areas are adjacent to the storage areas;

the dielectric layer is arranged on the pixel array structure;

the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction area, and the side wall, close to the center of the pixel array structure, of the light-transmitting structure is of a slope structure;

the micro lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the direction of inclining the slope structure; and

and the metal wiring layers are arranged in the dielectric layers and are offset towards the direction of inclination of the slope structure.

2. The image sensor of claim 1, wherein a main offset distance is provided between a central axis of the microlens and a symmetry plane of the photoelectric reaction region, and a sub offset distance is provided between the metal wiring and a central axis of the storage region, wherein the sub offset distance is 1/3 to 19/20 of the main offset distance.

3. An image sensor according to claim 1, wherein in the plurality of layers of the metal wiring, the metal wiring on the top layer is offset in a direction in which the slope structure is inclined.

4. An image sensor according to claim 3, wherein in the plurality of layers of the metal wiring, the metal wiring on the top layer and the metal wiring on the sub-top layer are offset in a direction inclined toward the slope structure.

5. An image sensor according to claim 1, wherein a gate is provided on the pixel array structure, the gate is located between the photo-reactive region and the storage region, and the gate covers the storage region and a portion of the photo-reactive region.

6. An image sensor as in claim 5, wherein an orthographic projection of said metal wiring on said pixel array structure is located within said storage area and on said gate structure.

7. The image sensor of claim 1, wherein the image sensor comprises a color filter layer disposed on the light transmissive structure and a planarization layer disposed between the color filter layer and the microlenses.

8. An image sensor as in claim 1, wherein the light transmissive structure has a refractive index greater than a refractive index of the dielectric layer.

9. A method of manufacturing an image sensor, comprising the steps of:

providing a pixel array structure, wherein the pixel array comprises a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas;

forming a dielectric layer on the pixel array structure;

forming a plurality of layers of metal wiring in the dielectric layer;

forming a light-transmitting structure on the photoelectric reaction region, wherein the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction region, the side wall, close to the center of the pixel array structure, of the light-transmitting structure is a slope structure, and the metal wiring is offset towards the direction of inclination of the slope structure; and

and forming a micro lens on the light-transmitting structure, wherein the micro lens covers the photoelectric reaction area, and the micro lens is offset towards the inclined direction of the slope structure.

10. The method of manufacturing an image sensor of claim 9, wherein the step of forming the light transmissive structure comprises:

etching the dielectric layer to form a light-transmitting groove;

etching the groove wall of the light-transmitting groove for multiple times to form a step structure;

burying the step structure, and forming the slope structure in the light-transmitting groove; and

and filling the light-transmitting groove to form the light-transmitting structure.

11. The method of manufacturing an image sensor of claim 10, wherein the step of burying the step structure comprises:

forming a buried layer in the light-transmitting groove and on the dielectric layer; and

and etching the buried layer to expose the photoelectric reaction area.

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