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CN116318055B - An on-chip clock generator - Google Patents

An on-chip clock generator

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Publication number
CN116318055B
CN116318055B CN202310098046.0A CN202310098046A CN116318055B CN 116318055 B CN116318055 B CN 116318055B CN 202310098046 A CN202310098046 A CN 202310098046A CN 116318055 B CN116318055 B CN 116318055B
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China
Prior art keywords
field effect
effect transistor
type field
respectively connected
resistor
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Application number
CN202310098046.0A
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Chinese (zh)
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CN116318055A (en
Inventor
邹博冈
姜玉才
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Ziguang Tongxin Microelectronics Co Ltd
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Ziguang Tongxin Microelectronics Co Ltd
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Priority to CN202310098046.0A priority Critical patent/CN116318055B/en
Publication of CN116318055A publication Critical patent/CN116318055A/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

本申请提供了一种片内时钟发生器，应用于集成电路技术领域，所述片内始终发生器包括电容、P型场效应晶体管、N型场效应晶体管、温度系数可调偏置电流电路、比较器、逻辑整形电路、D触发器、逻辑延时电路、窄脉宽发生器、第一反相器、第二反相器和第三反相器，通过偏置电流电路输出电流，对电容的充电速度、电流温度以及电流大小进行控制，消除片内时钟发生器的输出频率偏差，提高时钟频率的输出精度。

This application provides an on-chip clock generator, applied in the field of integrated circuit technology. The on-chip clock generator includes a capacitor, a P-type field-effect transistor, an N-type field-effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter, and a third inverter. The bias current circuit outputs current to control the charging speed, current temperature, and current magnitude of the capacitor, thereby eliminating the output frequency deviation of the on-chip clock generator and improving the output accuracy of the clock frequency.

Description

On-chip clock generator
Technical Field
The application relates to the technical field of integrated circuits, in particular to an on-chip clock generator.
Background
The on-chip clock generator has the advantages of small volume, low power consumption and the like because the on-chip clock generator does not need to generate clock oscillation period like an off-chip crystal oscillator and needs discrete inductance and capacitance, and is widely applied to a chip system of which the on-chip SOC needs a clock.
In the existing on-chip clock generator, charging current is generated through an adjustable current source, and the generated charging current charges a capacitor. When the charging voltage reaches the reference voltage set by the comparator, the capacitor is discharged through the logic gate, sawtooth waves are generated on the capacitor, the charging and discharging boundary value is determined through adjusting the reference voltage of the comparator, the RC time constant of the capacitor is charged, the charging slope is determined, and the clock frequency is finally determined by the two items. However, the clock frequency generated by the existing on-chip clock generator has great deviation, and the requirement of high precision cannot be met.
Disclosure of Invention
In view of this, the embodiment of the application provides an on-chip clock generator, which aims to eliminate the output frequency deviation of the on-chip clock generator and improve the output precision of the clock frequency.
The embodiment of the application provides an on-chip clock generator, which comprises a capacitor, a P-type field effect transistor, an N-type field effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D trigger, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter, wherein the first inverter is connected with the first inverter;
the temperature coefficient adjustable bias current circuit is respectively connected with the P-type field effect transistor and the comparator;
The P-type field effect transistor is respectively connected with the temperature coefficient adjustable bias current circuit, the N-type field effect transistor, the capacitor and the comparator;
The N-type field effect transistor is respectively connected with the P-type field effect transistor, the comparator and the capacitor, and the N-type field effect transistor is grounded;
The capacitor is respectively connected with the P-type field effect transistor, the N-type field effect transistor and the comparator, and is grounded;
The comparator is respectively connected with the temperature coefficient adjustable bias current circuit, the P-type field effect transistor, the N-type field effect transistor, the capacitor, the logic shaping circuit and the reference voltage;
The logic shaping circuit is respectively connected with the comparator and the first inverter;
The first inverter is respectively connected with the logic shaping circuit, the D trigger and the third inverter;
the third inverter is respectively connected with the first inverter and the D trigger, and outputs a clock CLK signal;
the D trigger is respectively connected with the first inverter, the second inverter, an enabling signal, the narrow pulse width generator and the logic delay circuit;
The second inverter is respectively connected with the D trigger and the enabling signal;
The logic delay circuit is respectively connected with the D trigger and the narrow pulse width generator;
The narrow pulse width generator is respectively connected with the logic delay circuit and the D trigger.
Optionally, the temperature coefficient adjustable bias current circuit comprises an external current source, a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a sixth P-type field effect transistor, a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port and a second output port.
Optionally, the third resistor is a variable resistor.
Optionally, the connection relationship of the temperature coefficient adjustable bias current circuit is:
The first P-type field effect transistor is respectively connected with the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the first resistor and a power supply;
The second P-type field effect transistor is respectively connected with the first P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor, the first resistor and a power supply;
The third P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the ninth P-type field effect transistor and the power supply;
The fourth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The fifth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The sixth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor, a power supply and a first output port;
The seventh P-type field effect transistor is respectively connected with the first P-type field effect transistor, the eighth P-type field effect transistor and the first resistor;
The eighth P-type field effect transistor is respectively connected with the second P-type field effect transistor, the seventh P-type field effect transistor, the ninth P-type field effect transistor, the first resistor and the second output port;
the ninth P-type field effect transistor is respectively connected with the third P-type field effect transistor, the eighth P-type field effect transistor, the second resistor, the first N-type field effect transistor and the third N-type field effect transistor;
The first resistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor and the external power supply;
the second resistor is respectively connected with the ninth P-type field effect transistor, the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The first N-type field effect transistor is respectively connected with the second resistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The second N-type field effect transistor is respectively connected with the first N-type field effect transistor, the third N-type field effect transistor, the fourth N-type field effect transistor and the second resistor, and the second N-type field effect transistor is grounded;
The third N-type field effect transistor is respectively connected with the second resistor, the first N-type field effect transistor, the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor;
the fourth N-type field effect transistor is respectively connected with the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor, the second resistor, the bipolar transistor and the third resistor, and the fourth N-type field effect transistor is grounded;
The fifth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor;
The sixth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the fifth N-type field effect transistor, the bipolar transistor and the third resistor;
The bipolar transistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and the third resistor, and the bipolar transistor is grounded;
The third resistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor, and the third resistor is grounded.
Optionally, the temperature coefficient adjustable bias current circuit is used for outputting two paths of bias currents.
Optionally, the logic shaping circuit is configured to adjust a waveform of the pulse signal.
Optionally, the logic delay circuit is used for performing demonstration transmission on the pulse signal.
The embodiment of the application provides an on-chip clock generator. The on-chip generator comprises a capacitor, a P-type field effect transistor, an N-type field effect transistor, a bias current circuit, a comparator, a logic shaping circuit, a D trigger, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter, wherein the bias current circuit outputs current to control the charging speed, the current temperature and the current of the capacitor, eliminate the output frequency deviation of the on-chip clock generator and improve the output precision of the clock frequency.
Drawings
In order to more clearly illustrate this embodiment or the technical solutions of the prior art, the drawings that are required for the description of the embodiment or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of an on-chip clock generator according to an embodiment of the present application;
fig. 2 is a schematic circuit diagram of a temperature coefficient adjustable bias current circuit according to an embodiment of the present application.
Detailed Description
It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of an on-chip clock generator according to an embodiment of the present application, including:
In fig. 1, MP1 is a P-type field effect transistor, C is a capacitor, IBIAS1 and IBIAS2 are two paths of bias currents output by a temperature coefficient adjustable bias current circuit, MN1 is an N-type field effect transistor, CMP is a comparator, VREF is a reference voltage, INV1 is a first inverter, INV2 is a second inverter, INV3 is a third inverter, EN is an enable signal, and CLK is a clock CLK signal.
The on-chip clock generator comprises a capacitor, a P-type field effect transistor, an N-type field effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D trigger, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter;
the temperature coefficient adjustable bias current circuit is respectively connected with the P-type field effect transistor and the comparator;
The P-type field effect transistor is respectively connected with the temperature coefficient adjustable bias current circuit, the N-type field effect transistor, the capacitor and the comparator;
The N-type field effect transistor is respectively connected with the P-type field effect transistor, the comparator and the capacitor, and the N-type field effect transistor is grounded;
The capacitor is respectively connected with the P-type field effect transistor, the N-type field effect transistor and the comparator, and is grounded;
The comparator is respectively connected with the temperature coefficient adjustable bias current circuit, the P-type field effect transistor, the N-type field effect transistor, the capacitor, the logic shaping circuit and the reference voltage;
The logic shaping circuit is respectively connected with the comparator and the first inverter;
The first inverter is respectively connected with the logic shaping circuit, the D trigger and the third inverter;
the third inverter is respectively connected with the first inverter and the D trigger, and outputs a clock CLK signal;
the D trigger is respectively connected with the first inverter, the second inverter, an enabling signal, the narrow pulse width generator and the logic delay circuit;
The second inverter is respectively connected with the D trigger and the enabling signal;
The logic delay circuit is respectively connected with the D trigger and the narrow pulse width generator;
The narrow pulse width generator is respectively connected with the logic delay circuit and the D trigger.
Specifically, the two outputs of the temperature coefficient adjustable bias current circuit are respectively connected with the source electrode of the P-type field effect transistor and the comparator, the drain electrode of the P-type field effect transistor is simultaneously connected with the drain electrode of the N-type field effect transistor and the positive end input of the comparator, the grid electrode of the P-type field effect transistor is simultaneously connected with the grid electrode of the N-type field effect transistor and the Q end output of the D trigger, the source electrode of the N-type field effect transistor is grounded, the upper end of the capacitor is connected with the drain electrode of the N-type field effect transistor, the lower end of the capacitor is grounded, the negative end of the comparator is connected with the reference voltage, the output end of the comparator is connected with the input of the logic shaping circuit, the output of the logic shaping circuit is connected with the input of the first inverter, the output of the first inverter is simultaneously connected with the input of the third inverter and the SETN end of the D trigger, the output of the third inverter is a clock signal, the input of the second inverter is simultaneously connected with the trigger signal and the Q end of the D trigger, the output of the D trigger is connected with the pulse width of the pulse width regulator, the delay circuit is used for demonstrating that the pulse width of the pulse width regulator is adjusted, the pulse width regulator is used for demonstrating circuit is used for demonstrating the pulse width adjustment, and the pulse width regulator is used for demonstrating circuit is used for carrying out the pulse width adjustment.
When the on-chip clock generator works, the initial state EN is set to 1 from 0, at the moment, the CLK pin is output to be 0, the CLK is connected with the SETN pin of the D trigger through the INV3 to be 1, and the RESETN is changed from 0 to 1. The output of the Q end of the D trigger keeps unchanged to 0, at the moment, MP1 is conducted, MN1 is cut off, and current IBIAS1 generated by the temperature coefficient adjustable bias current circuit charges a capacitor C through MP 1. This is the charging cycle. When the voltage level of charging C reaches a given bias voltage VREF, the output of the comparator CMP becomes 1, the output CLK becomes 1 from 0 after passing through the logic shaping circuit and INV1 and INV2, and at this time SETN becomes 0, and since RESETN is still 1 in the logic delay circuit, the delay determines the discharge time. At this time, the Q output becomes 1, so that MN1 is turned on, MP1 is turned off, capacitor C discharges through MN1 to ground, SETN becomes 1 from 0 when the voltage level on capacitor C is smaller than VREF, and Q output becomes 0 after RESETN jumps from 1 to 0 when the delay is completed, and the charging cycle is restarted. Since the presence RESETN of the narrow pulse generator goes to 1, Q maintains the output 0 unchanged, and the same applies to the next cycle.
The on-chip clock generator provided by the embodiment of the application can maintain the accuracy of output current under different voltages through the temperature coefficient adjustable bias current circuit, meanwhile, the charging time of the output INIAS on the capacitor under different temperatures becomes controllable due to the adjustable temperature coefficient of the bias current circuit, the time deviation of capacitor charging is solved, the temperature coefficient adjustable bias current circuit can increase the current on the capacitor at high temperature, the capacitor charging speed is increased, the delay generated by the high temperature is compensated, in addition, the temperature coefficient adjustable bias current circuit outputs IBIAS2 as the bias current of the comparator, and the mobility of the transistor is reduced to cause deviation due to the fact that the comparator CMP is composed of field effect transistors at high temperature, the current is increased at high temperature through IBIAS2, the carrier concentration is improved to compensate the deviation generated by the speed slowing at high temperature, the output frequency deviation of the on-chip clock generator is effectively eliminated, and the output precision of clock frequency is improved.
In addition, the embodiment of the application provides a preferable temperature coefficient adjustable bias current circuit. Referring to fig. 2, fig. 2 is a schematic circuit diagram of a temperature coefficient adjustable bias current circuit according to an embodiment of the present application.
In fig. 2, VDD is a power supply, I1 is an external current source, I2, I3 and I4 represent current flows in the circuit, MP1 is a first P-type field effect transistor, MP2 is a second P-type field effect transistor, MP3 is a third P-type field effect transistor, MP4 is a fourth P-type field effect transistor, MP5 is a fifth P-type field effect transistor, MP6 is a sixth P-type field effect transistor, MP7 is a seventh P-type field effect transistor, MP8 is an eighth P-type field effect transistor, MP9 is a ninth P-type field effect transistor, MN1 is a first N-type field effect transistor, MN2 is a second N-type field effect transistor, MN3 is a third N-type field effect transistor, MN4 is a fourth N-type field effect transistor, MN5 is a fifth N-type field effect transistor, MN6 is a sixth N-type field effect transistor, ibs 1 is a current output from a first output port, IBISA is a second output port is a third resistor, R1 is a third resistor, R3 is a bipolar resistor.
The temperature coefficient adjustable bias current circuit comprises an external current source, a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a sixth P-type field effect transistor, a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port and a second output port. Preferably, the third resistor is a variable resistor.
The connection relation of the temperature coefficient adjustable bias current circuit is as follows:
The first P-type field effect transistor is respectively connected with the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the first resistor and a power supply;
The second P-type field effect transistor is respectively connected with the first P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor, the first resistor and a power supply;
The third P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the ninth P-type field effect transistor and the power supply;
The fourth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The fifth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The sixth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor, a power supply and a first output port;
The seventh P-type field effect transistor is respectively connected with the first P-type field effect transistor, the eighth P-type field effect transistor and the first resistor;
The eighth P-type field effect transistor is respectively connected with the second P-type field effect transistor, the seventh P-type field effect transistor, the ninth P-type field effect transistor, the first resistor and the second output port;
the ninth P-type field effect transistor is respectively connected with the third P-type field effect transistor, the eighth P-type field effect transistor, the second resistor, the first N-type field effect transistor and the third N-type field effect transistor;
The first resistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor and the external power supply;
the second resistor is respectively connected with the ninth P-type field effect transistor, the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The first N-type field effect transistor is respectively connected with the second resistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The second N-type field effect transistor is respectively connected with the first N-type field effect transistor, the third N-type field effect transistor, the fourth N-type field effect transistor and the second resistor, and the second N-type field effect transistor is grounded;
The third N-type field effect transistor is respectively connected with the second resistor, the first N-type field effect transistor, the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor;
the fourth N-type field effect transistor is respectively connected with the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor, the second resistor, the bipolar transistor and the third resistor, and the fourth N-type field effect transistor is grounded;
The fifth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor;
The sixth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the fifth N-type field effect transistor, the bipolar transistor and the third resistor;
The bipolar transistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and the third resistor, and the bipolar transistor is grounded;
The third resistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor, and the third resistor is grounded.
The source electrode of the first P-type field effect transistor is connected with the external current source, the drain electrode of the first P-type field effect transistor is connected with the source electrode of the seventh P-type field effect transistor, the drain electrode of the first P-type field effect transistor is connected with the source electrode of the ninth P-type field effect transistor, the source electrode of the fourth P-type field effect transistor is connected with the external current source, the drain electrode of the second P-type field effect transistor is connected with the source electrode of the eighth P-type field effect transistor, the source electrode of the third P-type field effect transistor is connected with the source electrode of the fifth P-type field effect transistor, the drain electrode of the third P-type field effect transistor is connected with the source electrode of the second P-type field effect transistor, the source electrode of the fourth P-type field effect transistor is connected with the external current source, the drain electrode of the fourth P-type field effect transistor is connected with the drain electrode of the fifth P-type field effect transistor, the drain electrode of the fifth P-type field effect transistor is connected with the fifth P-type field effect transistor, and the fifth P-type field effect transistor is connected with the drain electrode of the fifth P-type field effect transistor is connected with the fifth P-type field transistor is connected with the fifth P-electrode is connected with the P-field electrode of the P-type P is simultaneously, the drain electrode of the sixth P-type field effect transistor is connected with the first output port, the drain electrode of the seventh P-type field effect transistor is connected with the upper end of the first resistor, the gate electrode of the seventh P-type field effect transistor is simultaneously connected with the gate electrode of the eighth P-type field effect transistor and the lower end of the first resistor, the drain electrode of the eighth P-type field effect transistor is connected with the second output port, the drain electrode of the ninth P-type field effect transistor is simultaneously connected with the upper end of the second resistor and the gate electrode of the first N-type field effect transistor, the drain electrode of the ninth P-type field effect transistor is simultaneously connected with the gate electrode of the fifth P-type field effect transistor, the drain electrode of the ninth P-type field effect transistor is simultaneously connected with the lower end of the second resistor and the gate electrode of the second N-type field effect transistor, the source electrode of the first N-type field effect transistor is simultaneously connected with the drain electrode of the fifth N-type field effect transistor, the drain electrode of the fifth P-type field effect transistor is simultaneously connected with the drain electrode of the fifth N-type field effect transistor, the drain electrode of the fifth P-type field effect transistor is simultaneously connected with the fourth N-type field effect transistor is simultaneously connected with the drain electrode of the fifth N-type field effect transistor is connected with the fifth N-effect transistor is simultaneously connected with the fifth N-type field effect transistor is of the fifth N-type is connected with the fifth N-type N is of the fifth N-type field effect transistor is simultaneously, the source electrode of the fifth N-type field effect transistor is connected with the collector electrode of the bipolar transistor, the grid electrode of the fifth N-type field effect transistor is connected with the grid electrode of the sixth N-type field effect transistor, the drain electrode of the fifth N-type field effect transistor is connected with the drain electrode of the sixth N-type field effect transistor, the source electrode of the sixth N-type field effect transistor is simultaneously connected with the base electrode of the bipolar transistor and the upper end of the third resistor, the upper end of the third resistor is simultaneously connected with the base electrode of the bipolar transistor and the source electrode of the sixth N-type field effect transistor, the lower end of the third resistor is grounded, and the emitter electrode of the bipolar transistor is grounded.
In the above-mentioned temperature coefficient adjustable bias current circuit, the current I1 is fed through other external circuits, usually a reference bandgap, and is an unregulated positive temperature coefficient current, and the positive temperature coefficient of the output IBIAS2 is greater than IBIAS1 after the current mirror formed by MP1, MP2, MP7, and MP8 is amplified by M1 times, and is fed to the comparator circuit in fig. 2 as its current bias, when the device carrier mobility decreases at high temperature, the comparator speed decreases, but the IBIAS2 current increases to compensate the speed loss caused by mobility decrease. The current of MP5 is composed of two parts, i.e. current I2 after mirror image amplification of current mirror composed of MN1, MN2, MN3 and MN4 and current I3 generated by base-collector voltage VBE of NPN1 on variable resistor R3, i.e. i4=i2+i3, I2=m2+i1+vbe/R3 can be obtained by replacing I2 and I3 respectively, I2 can be seen as positive temperature coefficient current by formula, I3 is negative temperature coefficient current, positive temperature coefficient can be increased by increasing size of M2 and increasing R3, so that slope of I4 along with temperature rise is more, or only reducing R3, so that slope of I4 along with temperature rise is more. The current I4 with adjustable temperature coefficient is amplified by M3 times to output IBIAS1 through a current mirror composed of MP5 and MP 6. IBIAS1 is the bias current for charging the capacitor in fig. 2.
The bias current circuit with adjustable temperature coefficient provided by the embodiment of the invention can effectively control the slope of current along with temperature change, further effectively eliminate the output frequency deviation of the on-chip clock generator and improve the output precision of clock frequency.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing description of the exemplary embodiments of the application is merely illustrative of the application and is not intended to limit the scope of the application.

Claims (7)

1. The on-chip clock generator is characterized by comprising a capacitor, a P-type field effect transistor, an N-type field effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D trigger, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter;
the temperature coefficient adjustable bias current circuit is respectively connected with the P-type field effect transistor and the comparator;
The P-type field effect transistor is respectively connected with the temperature coefficient adjustable bias current circuit, the N-type field effect transistor, the capacitor and the comparator;
The N-type field effect transistor is respectively connected with the P-type field effect transistor, the comparator and the capacitor, and the N-type field effect transistor is grounded;
The capacitor is respectively connected with the P-type field effect transistor, the N-type field effect transistor and the comparator, and is grounded;
The comparator is respectively connected with the temperature coefficient adjustable bias current circuit, the P-type field effect transistor, the N-type field effect transistor, the capacitor, the logic shaping circuit and the reference voltage;
The logic shaping circuit is respectively connected with the comparator and the first inverter;
The first inverter is respectively connected with the logic shaping circuit, the D trigger and the third inverter;
the third inverter is respectively connected with the first inverter and the D trigger, and outputs a clock CLK signal;
the D trigger is respectively connected with the first inverter, the second inverter, an enabling signal, the narrow pulse width generator and the logic delay circuit;
The second inverter is respectively connected with the D trigger and the enabling signal;
The logic delay circuit is respectively connected with the D trigger and the narrow pulse width generator;
The narrow pulse width generator is respectively connected with the logic delay circuit and the D trigger.
2. The on-chip clock generator of claim 1, wherein the temperature coefficient adjustable bias current circuit comprises an external current source, a first PFET, a second PFET, a third PFET, a fourth PFET, a fifth PFET, a sixth PFET, a seventh PFET, an eighth PFET, a ninth PFET, a first NFET, a second NFET, a third NFET, a fourth NFET, a fifth NFET, a sixth NFET, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port, and a second output port.
3. The on-chip clock generator of claim 2, wherein the third resistor is a variable resistor.
4. The on-chip clock generator of claim 2, wherein the temperature coefficient adjustable bias current circuit is connected in the following relationship:
The first P-type field effect transistor is respectively connected with the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the first resistor and a power supply;
The second P-type field effect transistor is respectively connected with the first P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor, the first resistor and a power supply;
The third P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the ninth P-type field effect transistor and the power supply;
The fourth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The fifth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor and a power supply;
The sixth P-type field effect transistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the third P-type field effect transistor, the fourth P-type field effect transistor, the fifth P-type field effect transistor, the third N-type field effect transistor, the sixth N-type field effect transistor, a power supply and a first output port;
The seventh P-type field effect transistor is respectively connected with the first P-type field effect transistor, the eighth P-type field effect transistor and the first resistor;
The eighth P-type field effect transistor is respectively connected with the second P-type field effect transistor, the seventh P-type field effect transistor, the ninth P-type field effect transistor, the first resistor and the second output port;
the ninth P-type field effect transistor is respectively connected with the third P-type field effect transistor, the eighth P-type field effect transistor, the second resistor, the first N-type field effect transistor and the third N-type field effect transistor;
the first resistor is respectively connected with the first P-type field effect transistor, the second P-type field effect transistor, the seventh P-type field effect transistor, the eighth P-type field effect transistor and the external current source;
the second resistor is respectively connected with the ninth P-type field effect transistor, the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The first N-type field effect transistor is respectively connected with the second resistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor;
The second N-type field effect transistor is respectively connected with the first N-type field effect transistor, the third N-type field effect transistor, the fourth N-type field effect transistor and the second resistor, and the second N-type field effect transistor is grounded;
The third N-type field effect transistor is respectively connected with the second resistor, the first N-type field effect transistor, the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor;
the fourth N-type field effect transistor is respectively connected with the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor, the second resistor, the bipolar transistor and the third resistor, and the fourth N-type field effect transistor is grounded;
The fifth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor;
The sixth N-type field effect transistor is respectively connected with the fourth P-type field effect transistor, the fifth P-type field effect transistor, the sixth P-type field effect transistor, the third N-type field effect transistor, the fifth N-type field effect transistor, the bipolar transistor and the third resistor;
The bipolar transistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the fifth N-type field effect transistor, the sixth N-type field effect transistor and the third resistor, and the bipolar transistor is grounded;
The third resistor is respectively connected with the second N-type field effect transistor, the fourth N-type field effect transistor, the sixth N-type field effect transistor and the bipolar transistor, and the third resistor is grounded.
5. The on-chip clock generator of claim 1, wherein the temperature coefficient adjustable bias current circuit is configured to output two bias currents.
6. The on-chip clock generator of claim 1, wherein the logic shaping circuit is configured to adjust a pulse signal waveform.
7. The on-chip clock generator of claim 1, wherein the logic delay circuit is configured to transmit a pulse signal for demonstration.
CN202310098046.0A 2023-01-20 2023-01-20 An on-chip clock generator Active CN116318055B (en)

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CN108933581A (en) * 2018-06-22 2018-12-04 上海艾为电子技术股份有限公司 A kind of pierce circuit
CN109286370A (en) * 2018-09-03 2019-01-29 宁波芯涌微电子有限公司 Clock oscillator and control method thereof

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US6911861B2 (en) * 2003-08-07 2005-06-28 Texas Instruments Incorporated Current biasing circuit with temperature compensation and related methods of compensating output current
CN107809223B (en) * 2016-09-08 2023-06-09 恩智浦美国有限公司 Low temperature coefficient clock signal generator
CN111697947B (en) * 2020-06-17 2021-08-31 长沙锐逸微电子有限公司 High-precision wide-range relaxation oscillator insensitive to temperature

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CN108933581A (en) * 2018-06-22 2018-12-04 上海艾为电子技术股份有限公司 A kind of pierce circuit
CN109286370A (en) * 2018-09-03 2019-01-29 宁波芯涌微电子有限公司 Clock oscillator and control method thereof

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