CN116314032A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region; forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure; removing the buffer layer on the NMOS device region; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region. The technical scheme of the invention can improve the performance of one of the NMOS device and the PMOS device, avoid reducing the performance of the other device, and simultaneously avoid increasing the manufacturing cost of the chip.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Currently, Stress Memorization Technology (SMT, Stress Memorization Technology) is usually used to improve the electron mobility of NMOS devices and the hole mobility of PMOS devices. Taking the improvement of the electron mobility of NMOS devices as an example, the steps include: after the sidewall and source-drain ion implantation process is completed, a silicon nitride layer with high tensile stress is deposited on the NMOS device region and the PMOS device region, and annealed at a high temperature The process transfers the tensile stress to the source, drain and gate of the NMOS device to improve the electron mobility of the NMOS device, and finally removes the silicon nitride layer. However, the tensile stress in the silicon nitride layer will also be transmitted to the source, drain and gate of the PMOS device, which will reduce the hole mobility of the PMOS device, thereby affecting the performance of the PMOS device.

Among them, in order to transfer more tensile stress to the NMOS device region and further improve the electron mobility of the NMOS device, a thicker silicon nitride layer will be deposited; but at the same time, it will cause tensile stress in the thicker silicon nitride layer Passed to the PMOS device area, thereby affecting the performance of the PMOS device. Therefore, in order to improve the performance of NMOS devices and avoid reducing the performance of PMOS devices, after depositing a thicker silicon nitride layer and before the high-temperature annealing process, an additional photolithography and etching process is added to remove the PMOS devices. The silicon nitride layer on the region, only the silicon nitride layer on the NMOS device region remains. However, this method will add an additional photolithography and etching process, which will increase the cost of chip manufacturing.

Therefore, how to improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device while avoiding increasing the cost of chip manufacturing is an urgent problem to be solved.

Contents of the invention

The object of the present invention is to provide a semiconductor device and its manufacturing method, so that while improving the performance of one of the NMOS device and the PMOS device and avoiding reducing the performance of the other device, it can also avoid increasing the chip manufacturing cost.

To achieve the above object, the invention provides a method for manufacturing a semiconductor device, comprising:

A substrate is provided, the substrate includes an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region;

forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

Form a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; the stress layer is a compressive stress layer , the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

Optionally, when the stress layer is a tensile stress layer, before forming the stress layer on the buffer layer, the manufacturing method of the semiconductor device further includes:

Forming a first source region and a first drain region in the substrate on both sides of the gate structure of the NMOS device region, forming the first source region and the first drain region and forming the first drain region The buffer layer adopts the same patterned photoresist layer as a mask;

When the stress layer is a compressive stress layer, before forming the stress layer on the buffer layer, the manufacturing method of the semiconductor device further includes:

Forming a second source region and a second drain region in the substrate on both sides of the gate structure of the PMOS device region, forming the second source region and the second drain region and forming the second drain region The buffer layer uses the same patterned photoresist layer as a mask.

Optionally, when the stress layer is a tensile stress layer;

The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, and the first buffer layer covers the gate structure;

removing the first buffer layer on the NMOS device region;

forming a second buffer layer on the substrate and the gate structure in the NMOS device region and on the first buffer layer in the PMOS device region;

Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

removing part of the thickness of the buffer layer on the NMOS device region.

Optionally, before or after removing the first buffer layer on the NMOS device region, or before or after removing a partial thickness of the buffer layer on the NMOS device region, the manufacturing method of the semiconductor device Also includes:

forming a first source region and a first drain region in the substrate on both sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed in the same manner as The same patterned photoresist layer is used as a mask to remove the first buffer layer on the NMOS device region or to remove a part of the thickness of the buffer layer on the NMOS device region.

Optionally, after removing the first buffer layer on the NMOS device region or after removing a partial thickness of the buffer layer on the NMOS device region, the manufacturing method of the semiconductor device further includes:

A second source region and a second drain region are formed in the substrate on both sides of the gate structure in the PMOS device region.

Optionally, when the stress layer is a compressive stress layer;

The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, and the first buffer layer covers the gate structure;

removing the first buffer layer on the PMOS device region;

forming a second buffer layer on the substrate and the gate structure of the PMOS device region and on the first buffer layer of the NMOS device region;

Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

removing a partial thickness of the buffer layer on the PMOS device region.

Optionally, before or after removing the first buffer layer on the PMOS device region, or before or after removing a partial thickness of the buffer layer on the PMOS device region, the manufacturing method of the semiconductor device Also includes:

forming a second source region and a second drain region in the substrate on both sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed in the same manner as The same patterned photoresist layer is used as a mask to remove the first buffer layer on the PMOS device region or to remove a partial thickness of the buffer layer on the PMOS device region.

Optionally, after removing the first buffer layer on the PMOS device region or after removing a partial thickness of the buffer layer on the PMOS device region, the manufacturing method of the semiconductor device further includes:

A first source region and a first drain region are formed in the substrate on both sides of the gate structure in the NMOS device region.

Optionally, the manufacturing method of the semiconductor device further includes:

perform the annealing process;

The stress layer is removed.

The present invention also provides a semiconductor device, comprising:

a substrate, the substrate includes an NMOS device region and a PMOS device region, and a gate structure is formed on the substrate of the NMOS device region and the PMOS device region;

a buffer layer formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

A stress layer is formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; the stress layer is a compressive stress layer layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

Optionally, the material of the stress layer includes silicon nitride, and the material of the buffer layer includes silicon oxide.

Optionally, the semiconductor device also includes:

a first source region and a first drain region formed in the substrate on both sides of the gate structure in the NMOS device region;

A second source region and a second drain region are formed in the substrate on both sides of the gate structure in the PMOS device region.

Optionally, a P well is formed in the substrate of the NMOS device region, and the first source region and the first drain region are formed on the top of the P well; the substrate of the PMOS device region An N well is formed in the center, and the second source region and the second drain region are formed on top of the N well.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

1. The manufacturing method of the semiconductor device of the present invention, by forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; removing the buffer layer on the NMOS device region; forming The stress layer is on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer The thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region, so that while improving the performance of one of the NMOS device and the PMOS device and avoiding reducing the performance of the other device, it is also Increases in chip manufacturing costs can be avoided.

2. The semiconductor device of the present invention includes: a buffer layer formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer is formed on the on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the NMOS The thickness of the buffer layer on the device region is greater than the thickness of the buffer layer on the PMOS device region, so that while improving the performance of one of the NMOS device and the PMOS device and avoiding reducing the performance of the other device, it is also possible to avoid adding chips manufacturing cost.

Description of drawings

1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

2a to 2i are device schematic diagrams of an embodiment of the manufacturing method of the semiconductor device shown in FIG. 1;

3 a to 3 g are device schematic diagrams of another embodiment of the manufacturing method of the semiconductor device shown in FIG. 1 .

Wherein, the reference numerals of accompanying drawings 1 to 3g are explained as follows:

11-substrate; 111-P well; 112-N well; 113-trench isolation structure; 114-lightly doped source region; 115-lightly doped drain region; 116-first source region; 117-first Drain region; 118-second source region; 119-second drain region; 12-gate structure; 13-side wall; 14-buffer layer; 141-first buffer layer; 142-second buffer layer; 151 - the first patterned photoresist layer; 152 - the second patterned photoresist layer; 16 - the stress layer.

Detailed ways

In order to make the purpose, advantages and features of the present invention clearer, the semiconductor device and its manufacturing method proposed by the present invention will be further described in detail below. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 1, it can be seen from FIG. 1 that the method for manufacturing a semiconductor device includes:

Step S1, providing a substrate, the substrate includes an NMOS device region and a PMOS device region, and a gate structure is formed on the substrate of the NMOS device region and the PMOS device region;

Step S2, forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

Step S3, forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; the stress layer is When compressing the stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

Referring to FIGS. 2a to 2i and FIGS. 3a to 3g, the manufacturing method of the semiconductor device provided by this embodiment will be described in detail below.

According to step S1, referring to FIG. 2a, a substrate 11 is provided, and the substrate 11 includes an NMOS device region A1 and a PMOS device region A2, and both the NMOS device region A1 and the PMOS device region A2 are formed on the substrate 11. There are gate structures 12 and sidewalls 13 formed on the sidewalls of the gate structures 12 .

The gate structure 12 includes a gate oxide layer and a gate layer from bottom to top.

A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to realize mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with or slightly higher than the top surface of the substrate 11 .

A P well 111 is formed in the substrate 11 of the NMOS device region A1, an N well 112 is formed in the substrate 11 of the PMOS device region A2, and the bottom surfaces of the P well 111 and the N well 112 may be lower than the bottom surface of the trench isolation structure 113 .

Moreover, in the NMOS device region A1, a lightly doped source region 114 and a lightly doped drain region 115 are formed on the top of the P well 111 on both sides of the gate structure 12; in the PMOS device region A2, the gate A lightly doped source region 114 and a lightly doped drain region 115 are also formed on top of the N well 112 on both sides of the pole structure 12 . Moreover, in the NMOS device region A1 and the PMOS device region A2 , both the lightly doped source region 114 and the lightly doped drain region 115 extend below the gate structure 12 .

According to step S2 , a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 , and the buffer layer 14 covers the gate structure 12 and the sidewall 13 . Wherein, the buffer layer 14 plays the role of buffering and protecting the device, and can also play a blocking role.

Preferably, the buffer layer 14 is made of silicon oxide. It should be noted that the material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, fluoride silicon glass, phosphosilicate glass and borophosphosilicate glass.

According to step S3 , as shown in FIG. 2i and FIG. 3g , a stress layer 16 is formed on the buffer layer 14 . When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; when the stress layer 16 is a compressive stress layer, the The thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.

When the stress layer 16 is a tensile stress layer, before forming the stress layer 16 on the buffer layer 14, the manufacturing method of the semiconductor device further includes: forming a first source region 116 and a first drain Region 117 is in the substrate 11 on both sides of the gate structure 12 in the NMOS device region A1, forming the first source region 116 and the first drain region 117 and forming the buffer layer 14 using The same patterned photoresist layer is a mask; when the stress layer 16 is a compressive stress layer, before forming the stress layer 16 on the buffer layer 14, the manufacturing method of the semiconductor device also includes: Forming a second source region 118 and a second drain region 119 in the substrate 11 on both sides of the gate structure 12 in the PMOS device region A2, forming the second source region 118 and the second The drain region 119 and the buffer layer 14 are formed using the same patterned photoresist layer as a mask. Therefore, there is no need to add additional photomask and photolithography steps, thereby reducing the cost of the stress memory process.

Wherein, in one embodiment, when the stress layer 16 is a tensile stress layer, in the step S2, the buffer layer 14 is formed on the substrate of the NMOS device region A1 and the PMOS device region A2 The step on 11 may include: first, as shown in FIG. 2b, forming a first buffer layer 141 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the first buffer layer 141 covers The gate structure 12 and the spacer 13; then, as shown in FIG. 2d, a first patterned photoresist layer 151 is formed, and the first patterned photoresist layer 151 covers the PMOS device the first buffer layer 141 in the region A2 and expose the first buffer layer 141 in the NMOS device region A1, and perform an etching process using the first patterned photoresist layer 151 as a mask to remove the The first buffer layer 141 on the NMOS device region A1; then, as shown in FIG. 2e, remove the first patterned photoresist layer 151; then, as shown in FIG. 2h, form a second buffer layer 142 on the On the substrate 11, the gate structure 12 and the spacer 13 of the NMOS device region A1 and on the first buffer layer 141 of the PMOS device region A2, at this time, on the NMOS device region A1 The second buffer layer 142 is used as the buffer layer 14 on the NMOS device area A1, and the first buffer layer 141 and the second buffer layer 142 on the PMOS device area A2 are jointly used as the buffer layer 14 on the PMOS device area A2. The buffer layer 14 is such that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1.

Moreover, before or after removing the first buffer layer 141 on the NMOS device region A1 (as shown in FIG. 2c ), the manufacturing method of the semiconductor device may further include: performing an ion implantation process to form a first source region 116 and the first drain region 117 are located in the substrate 11 on the side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12 . Wherein, as shown in FIG. 2c and FIG. 2d, forming the first source region 116 and the first drain region 117 and removing the first buffer layer 141 on the NMOS device region A1 use the same patterned light. The resist layer (ie, the first patterned photoresist layer 151 ) is a mask.

Alternatively, when the stress layer 16 is a tensile stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 may include : First, as shown in FIG. 3a, a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the side wall 13; then, as shown in FIG. the buffer layer 14 of the NMOS device region A1, and perform an etching process using the first patterned photoresist layer 151 as a mask to remove part of the thickness of the buffer layer 14 on the NMOS device region A1, so as to Make the buffer layer 14 on the PMOS device region A2 thicker than the buffer layer 14 on the NMOS device region A1; then, as shown in FIG. 3 d , remove the first patterned photoresist layer 151 .

In addition, before or after removing part of the thickness of the buffer layer on the NMOS device region (as shown in FIG. 3b ), the manufacturing method of the semiconductor device further includes: performing an ion implantation process to form a first source region 116 and the first drain region 117 are located in the substrate 11 on the side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12 . Wherein, as shown in FIG. 3b and FIG. 3c, the first source region 116 and the first drain region 117 are formed in the same pattern as the buffer layer 14 that removes part of the thickness on the NMOS device region A1 The patterned photoresist layer (that is, the first patterned photoresist layer 151) is used as a mask.

It can be seen from the above steps that when the stress layer 16 is a tensile stress layer, due to the formation of the first source region 116 and the first drain region 117 and the removal of the first buffer layer on the NMOS device region A1 141 or removing the partial thickness of the buffer layer 14 on the NMOS device region A1 using the first patterned photoresist layer 151 as a mask, that is, using the same photomask, so that there is no need to add additional light Mask and photolithography steps, thereby reducing the stress memory process cost.

In addition, when the buffer layer 14 is made of silicon oxide, hydrofluoric acid etching can be used to remove the first buffer layer 141 and a part of the thickness of the buffer layer 14 on the NMOS device region A1.

After removing the first buffer layer 141 on the NMOS device region A1 and before forming the second buffer layer 142, or after removing part of the thickness of the buffer layer 14 on the NMOS device region A1, The manufacturing method of the semiconductor device may further include: first, as shown in FIG. 2f and FIG. 3e, forming a second patterned photoresist layer 152, the second patterned photoresist layer 152 covers the NMOS device region A1 and expose the PMOS device region A2; then, as shown in FIG. 2f and FIG. The electrode region 118 and the second drain region 119 are located in the substrate 11 on the side of the side wall 13 of the PMOS device region A2 away from the gate structure 12; then, as shown in FIG. 2g and FIG. 3f, remove The second patterned photoresist layer 152 .

In another embodiment (not shown), when the stress layer 16 is a compressive stress layer, in the step S2, the buffer layer 14 is formed in the NMOS device region A1 and the PMOS device region The steps on the substrate 11 of A2 include: first, forming a first buffer layer 141 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the first buffer layer 141 covers the gate pole structure 12 and the sidewall 13; then, a first patterned photoresist layer 151 is formed, and the first patterned photoresist layer 151 covers the first buffer layer 141 of the NMOS device region A1 and Exposing the first buffer layer 141 of the PMOS device region A2, and performing an etching process using the first patterned photoresist layer 151 as a mask to remove the first buffer layer on the PMOS device region A2 layer 141; then, remove the first patterned photoresist layer 151; then, form a second buffer layer 142 on the substrate 11, the gate structure 12 and the PMOS device region A2 On the sidewall 13 and on the first buffer layer 141 of the NMOS device region A1, at this time, the second buffer layer 142 on the PMOS device region A2 serves as the buffer layer 14 on the PMOS device region A2, The first buffer layer 141 and the second buffer layer 142 on the NMOS device region A1 together serve as the buffer layer 14 on the NMOS device region A1, so that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than The thickness of the buffer layer 14 on the PMOS device region A2.

Moreover, before or after removing the first buffer layer 141 on the PMOS device region A2, the manufacturing method of the semiconductor device further includes: performing an ion implantation process to form the second source region 118 and the second drain region 119 In the substrate 11 on the side of the side wall 13 of the PMOS device region A2 away from the gate structure 12 . Wherein, forming the second source region 118 and the second drain region 119 and removing the first buffer layer 141 on the PMOS device region A2 adopt the same patterned photoresist layer (that is, the first The patterned photoresist layer 151) is a mask.

Alternatively, when the stress layer 16 is a compressive stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 includes: First, a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13; then, a second A patterned photoresist layer 151, the first patterned photoresist layer 151 covers the buffer layer 14 of the NMOS device region A1 and exposes the buffer layer 14 of the PMOS device region A2, and The first patterned photoresist layer 151 is used as a mask to perform an etching process to remove part of the thickness of the buffer layer 14 on the PMOS device region A2, so that the thickness of the buffer layer 14 on the NMOS device region A1 greater than the thickness of the buffer layer 14 on the PMOS device region A2; then, removing the first patterned photoresist layer 151 .

In addition, before or after removing part of the thickness of the buffer layer 14 on the PMOS device region A2, the manufacturing method of the semiconductor device further includes: performing an ion implantation process to form a second source region 118 and a second drain The electrode region 119 is located in the substrate 11 on the side of the side wall 13 of the PMOS device region A2 away from the gate structure 12 . Wherein, the same patterned photoresist layer is used to form the second source region 118 and the second drain region 119 and to remove part of the thickness of the buffer layer 14 on the PMOS device region A2 (that is, the The first patterned photoresist layer 151) is used as a mask.

It can be known from the above steps that when the stress layer 16 is a compressive stress layer, due to the formation of the second source region 118 and the second drain region 119 and the removal of the first buffer layer on the PMOS device region A2 141 or the step of removing the partial thickness of the buffer layer 14 on the PMOS device region A2 uses the first patterned photoresist layer 151 as a mask, that is, the same photomask is used, so that there is no need to additionally increase the photoresist layer 151. Mask and photolithography steps, thereby reducing the stress memory process cost.

In addition, when the material of the buffer layer 14 is silicon oxide, hydrofluoric acid etching can be used to remove the first buffer layer 141 and a part of the thickness of the buffer layer 14 on the PMOS device region A2.

After removing the first buffer layer 141 on the PMOS device region A2 and before forming the second buffer layer 142, or, after removing part of the thickness of the buffer layer 14 on the PMOS device region A2, The manufacturing method of the semiconductor device further includes: first, forming a second patterned photoresist layer 152, the second patterned photoresist layer 152 covers the PMOS device region A2 and exposes the NMOS device region A1; then, perform an ion implantation process using the second patterned photoresist layer 152 as a mask to form the first source region 116 and the first drain region 117 in the NMOS device region A1 The spacer 13 is located in the substrate 11 on the side away from the gate structure 12 ; then, the second patterned photoresist layer 152 is removed.

It should be noted that this embodiment does not show the schematic diagram of devices corresponding to the steps S2 to S3 when the stress layer 16 is a compressive stress layer, and the step S2 when the stress layer 16 is a tensile stress layer Compared with the schematic diagram of the device corresponding to the step S3 (ie, Fig. 2b ~ Fig. 2i and Fig. 3a ~ Fig. 3g), the main difference between the schematic diagram of the device when the stress layer 16 is a compressive stress layer is that the first pattern The exposed regions of the patterned photoresist layer 151 and the second patterned photoresist layer 152 are different, so that the buffer layer 14 on the NMOS device region A1 and the PMOS device region A2 can meet different requirements. Different requirements for tensile or compressive stress.

The first source region 116 and the first drain region 117 may extend below the spacer 13, and the first source region 116 and the first drain region 117 are formed on the P The top of the well 111 , and the bottom surfaces of the first source region 116 and the first drain region 117 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115 .

The second source region 118 and the second drain region 119 are formed on the top of the N well 112, and the second source region 118 and the second drain region 119 may extend to the side wall 13 , and the bottom surfaces of the second source region 118 and the second drain region 119 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115 .

In the NMOS device region A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N type; in the PMOS device region A2, ion doping of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 All types are P-type.

Preferably, the thickness of the first buffer layer 141 is

Preferably, the thickness of the second buffer layer 142 is

Preferably, the stress layer 16 is made of silicon nitride, and the stress layer 16 has high tensile stress or high pressure stress by adjusting the parameters when forming the stress layer 16 .

The manufacturing method of the semiconductor device may further include: first, performing an annealing process to introduce tensile stress in the stress layer 16 to the gate structure 12 of the NMOS device region A1, the first source region 116 , the first drain region 117 and the substrate 11, or introduce the compressive stress in the stress layer 16 into the gate structure 12 of the PMOS device region A2, the second source region 118 , the second drain region 119 and the substrate 11 ; then, the stress layer 16 is removed.

In the manufacturing method of the semiconductor device of the present invention, when the stress layer 16 is a tensile stress layer, a buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16 , and the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1, so that after the high-temperature annealing process is performed, the stress layer 16 on the NMOS device region A1 More tensile stress can pass through the thinner buffer layer 14 and then be smoothly transmitted to the gate structure 12 of the NMOS device region A1, the first source region 116, and the first drain region 117 and in the substrate 11, and make it difficult for the tensile stress in the stress layer 16 on the PMOS device region A2 to pass through the thicker buffer layer 14 to the gate of the PMOS device region A2 electrode structure 12, the second source region 118, the second drain region 119 and the substrate 11, so that more tensile stress can be transmitted without increasing the thickness of the stress layer 16 In the NMOS device region A1, and the thickness of the stress layer 16 is not increased, the buffer layer 14 on the PMOS device region A2 has a sufficient blocking effect on the tensile stress, so as to avoid lifting the stress layer 16 The influence of the tensile stress in the PMOS device region A2, and the buffer layer 14 on the NMOS device region A1 can also play a role in protecting the device. Therefore, it is possible to avoid reducing the hole mobility of the PMOS device while further improving the electron mobility of the NMOS device, thereby avoiding reducing the performance of the PMOS device while improving the performance of the NMOS device.

And when the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after performing the high temperature annealing process, the More compressive stress in the stress layer 16 on the PMOS device region A2 can pass through the thinner buffer layer 14 and then be smoothly transferred to the gate structure 12 of the PMOS device region A2, the second source electrode region 118, the second drain region 119 and the substrate 11, and make it difficult for the compressive stress in the stress layer 16 on the NMOS device region A1 to pass through the thicker buffer layer 14 and transferred to the gate structure 12 of the NMOS device region A1, the first source region 116, the first drain region 117 and the substrate 11, so that there is no need to increase the stress layer The thickness of 16 can make more compressive stress be transmitted to the PMOS device region A2, and the thickness of the stress layer 16 is not increased so that the buffer layer 14 on the NMOS device region A1 has sufficient compressive stress. The blocking effect of the NMOS device region A1 can be avoided by increasing the compressive stress in the stress layer 16, and the buffer layer 14 on the PMOS device region A2 can also protect the device. Therefore, the electron mobility of the NMOS device can be avoided while the hole mobility of the PMOS device is further improved, so that the performance of the NMOS device can be avoided while the performance of the PMOS device is improved.

Moreover, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device region A2 has a sufficient blocking effect on the tensile stress, after forming the stress layer 16 and performing annealing Before the process, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the PMOS device region A2, thereby avoiding increasing the chip manufacturing cost; when the stress layer 16 is a compressive stress layer, because the NMOS device The buffer layer 14 on the region A1 has a sufficient blocking effect on the compressive stress, so that after the stress layer 16 is formed and before the annealing process is performed, there is no need to introduce additional photolithography and etching steps to remove the NMOS device region The stress layer 16 on A1, so as to avoid increasing the chip manufacturing cost.

Moreover, due to the material of the stress layer 16 (for example, silicon nitride), the material of the buffer layer 14 (for example, silicon oxide), and the materials of the gate structure 12 and the substrate 11 (for example, respectively The lattice constants of polycrystalline silicon and single crystal silicon) do not match each other, and the lattice spacing is greatly different. If more tensile stress is transmitted to the NMOS device region A1 by increasing the thickness of the stress layer 16 or more If the compressive stress is transmitted to the PMOS device region A2, it is more likely to cause damage to the gate structure 12 and the substrate 11, which in turn may cause excessive leakage current of the device, and even cause the device to fail to work. Therefore, the present invention does not increase the thickness of the stress layer 16 so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, so that the device can be avoided. The leakage current is too large.

In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including an NMOS device region and a PMOS device region, the substrate of the NMOS device region and the PMOS device region A gate structure is formed on each; a buffer layer is formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer is formed on the buffer layer; When the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the buffer layer on the NMOS device region The layer thickness is greater than the buffer layer thickness on the PMOS device region. The manufacturing method of the semiconductor device provided by the present invention can avoid increasing the chip manufacturing cost while improving the performance of one of the NMOS device and the PMOS device and avoiding reducing the performance of the other device.

An embodiment of the present invention provides a semiconductor device, including: a substrate, the substrate includes an NMOS device region and a PMOS device region, and a gate is formed on the substrate of the NMOS device region and the PMOS device region structure; a buffer layer, formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer, formed on the buffer layer; the stress layer When it is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the NMOS device region. The thickness of the buffer layer on the PMOS device region.

The semiconductor device provided by this embodiment will be described in detail below with reference to FIG. 2i and FIG. 3g.

The substrate 11 includes an NMOS device region A1 and a PMOS device region A2, and gate structures 12 and sidewalls 13 are formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the sidewalls 13 is formed on the sidewall of the gate structure 12 .

The gate structure 12 includes a gate oxide layer and a gate layer from bottom to top.

A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to realize mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with or slightly higher than the top surface of the substrate 11 .

A P well 111 is formed in the substrate 11 of the NMOS device region A1, an N well 112 is formed in the substrate 11 of the PMOS device region A2, and the bottom surfaces of the P well 111 and the N well 112 may be lower than the bottom surface of the trench isolation structure 113 .

Moreover, in the NMOS device region A1, a lightly doped source region 114 and a lightly doped drain region 115 are formed on the top of the P well 111 on both sides of the gate structure 12; in the PMOS device region A2, the gate A lightly doped source region 114 and a lightly doped drain region 115 are also formed on top of the N well 112 on both sides of the pole structure 12 . Moreover, in the NMOS device region A1 and the PMOS device region A2 , both the lightly doped source region 114 and the lightly doped drain region 115 extend below the gate structure 12 .

The semiconductor device also includes:

The first source region 116 and the first drain region 117 are formed in the substrate 11 on the side of the side wall 13 of the NMOS device region A1 away from the gate structure 12, and the first source region 116 and the first drain region 117 may extend below the sidewall 13;

The second source region 118 and the second drain region 119 are formed in the substrate 11 on the side of the side wall 13 of the PMOS device region A2 away from the gate structure 12, the second source region 118 and the second drain region 119 may extend below the sidewall 13 .

Wherein, the first source region 116 and the first drain region 117 are formed on the top of the P well 111, and the bottom surfaces of the first source region 116 and the first drain region 117 are lower on the bottom surface of the lightly doped source region 114 and the lightly doped drain region 115; the second source region 118 and the second drain region 119 are formed on the top of the N well 112, and the The bottom surfaces of the second source region 118 and the second drain region 119 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115 .

In the NMOS device region A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N type; in the PMOS device region A2, ion doping of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 All types are P-type.

The buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 , and the buffer layer 14 covers the gate structure 12 and the sidewall 13 . Wherein, the buffer layer 14 plays the role of buffering and protecting the device, and can also play a blocking role.

Preferably, the buffer layer 14 is made of silicon oxide. It should be noted that the material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, fluoride silicon glass, phosphosilicate glass and borophosphosilicate glass.

The stress layer 16 is formed on the buffer layer 14 .

When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; when the stress layer 16 is a compressive stress layer, the The thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.

When the stress layer 16 is a tensile stress layer, in the embodiment shown in FIG. 2i, the buffer layer 14 on the PMOS device region A2 includes a first buffer layer 141 and a second buffer layer 142, the The buffer layer 14 on the NMOS device region A1 only includes the second buffer layer 142, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; in FIG. 3g In the illustrated embodiment, part of the thickness of the buffer layer 14 on the NMOS device region A1 is removed, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1 .

When the stress layer 16 is a compressive stress layer, the buffer layer 14 on the NMOS device region A1 includes a first buffer layer 141 and a second buffer layer 142, and the buffer layer on the PMOS device region A2 14 includes only the second buffer layer 142, so that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2; or, part of the thickness on the PMOS device region A2 The buffer layer 14 is removed, so that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.

Preferably, the thickness of the first buffer layer 141 is

Preferably, the thickness of the second buffer layer 142 is

Preferably, the stress layer 16 is made of silicon nitride, and the stress layer 16 has high tensile stress or high pressure stress by adjusting the parameters when forming the stress layer 16 .

It should be noted that the stress layer 16 is a stress layer after an annealing process, so that the tensile stress in the stress layer 16 can be introduced into the gate structure 12 of the NMOS device region A1, the first In the source region 116, the first drain region 117 and the substrate 11, or to introduce the compressive stress in the stress layer 16 to the gate structure 12, the second source region 118 , the second drain region 119 and the substrate 11 ; and, after performing an annealing process, the stress layer 16 may be removed. In the semiconductor device of the present invention, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16, and the The thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1, so that after the high-temperature annealing process is performed, more of the stress layer 16 on the NMOS device region A1 Tensile stress can pass through the thinner buffer layer 14 and then be smoothly transferred to the gate structure 12 of the NMOS device region A1, the first source region 116, the first drain region 117 and the substrate 11, and make it difficult for the tensile stress in the stress layer 16 on the PMOS device region A2 to pass through the thicker buffer layer 14 to the gate structure 12 of the PMOS device region A2 , the second source region 118, the second drain region 119 and the substrate 11, so that more tensile stress can be transmitted to the NMOS device without increasing the thickness of the stress layer 16 In the area A1, and the thickness of the stress layer 16 is not increased, the buffer layer 14 on the PMOS device area A2 has a sufficient blocking effect on the tensile stress, so as to avoid raising the tension in the stress layer 16. Stress affects the PMOS device region A2, and the buffer layer 14 on the NMOS device region A1 can also play a role in protecting the device. Therefore, it is possible to avoid reducing the hole mobility of the PMOS device while further improving the electron mobility of the NMOS device, thereby avoiding reducing the performance of the PMOS device while improving the performance of the NMOS device.

And when the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after performing the high temperature annealing process, the More compressive stress in the stress layer 16 on the PMOS device region A2 can pass through the thinner buffer layer 14 and then be smoothly transferred to the gate structure 12 of the PMOS device region A2, the second source electrode region 118, the second drain region 119 and the substrate 11, and make it difficult for the compressive stress in the stress layer 16 on the NMOS device region A1 to pass through the thicker buffer layer 14 and transferred to the gate structure 12 of the NMOS device region A1, the first source region 116, the first drain region 117 and the substrate 11, so that there is no need to increase the stress layer The thickness of 16 can make more compressive stress be transmitted to the PMOS device region A2, and the thickness of the stress layer 16 is not increased so that the buffer layer 14 on the NMOS device region A1 has sufficient compressive stress. The blocking effect of the NMOS device region A1 can be avoided by increasing the compressive stress in the stress layer 16, and the buffer layer 14 on the PMOS device region A2 can also protect the device. Therefore, the electron mobility of the NMOS device can be avoided while the hole mobility of the PMOS device is further improved, so that the performance of the NMOS device can be avoided while the performance of the PMOS device is improved.

Moreover, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device region A2 has a sufficient blocking effect on the tensile stress, the NMOS device region A1 and the PMOS device region The stress layer 16 on A2 is retained, indicating that before performing the annealing process, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the PMOS device region A2, thereby avoiding increasing chip manufacturing costs; when When the stress layer 16 is a compressive stress layer, since the buffer layer 14 on the NMOS device region A1 has a sufficient blocking effect on the compressive stress, the buffer layer 14 on the NMOS device region A1 and the PMOS device region A2 The stress layer 16 is retained, which means that before performing the annealing process, it is not necessary to introduce additional photolithography and etching steps to remove the stress layer 16 on the NMOS device region A1, thereby avoiding increasing chip manufacturing costs.

Moreover, due to the material of the stress layer 16 (for example, silicon nitride), the material of the buffer layer 14 (for example, silicon oxide), and the materials of the gate structure 12 and the substrate 11 (for example, respectively The lattice constants of polycrystalline silicon and single crystal silicon) do not match each other, and the lattice spacing is greatly different. If more tensile stress is transmitted to the NMOS device region A1 by increasing the thickness of the stress layer 16 or more If the compressive stress is transmitted to the PMOS device region A2, it is more likely to cause damage to the gate structure 12 and the substrate 11, which in turn may cause excessive leakage current of the device, and even cause the device to fail to work. Therefore, the present invention does not increase the thickness of the stress layer 16 so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, so that the device can be avoided. The leakage current is too large.

In summary, the present invention provides a semiconductor device, including: a substrate, the substrate includes an NMOS device region and a PMOS device region, and gates are formed on the substrates of the NMOS device region and the PMOS device region. a pole structure; a buffer layer, formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer, formed on the buffer layer; the stress When the layer is a tensile stress layer, the buffer layer thickness on the PMOS device region is greater than the buffer layer thickness on the NMOS device region; when the stress layer is a compressive stress layer, the buffer layer thickness on the NMOS device region is greater than The thickness of the buffer layer on the PMOS device region. The semiconductor device provided by the present invention can avoid increasing the cost of chip manufacturing while improving the performance of one of the NMOS device and the PMOS device and avoiding reducing the performance of the other device.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;

forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;

forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a tensile stress layer, the method for manufacturing a semiconductor device further comprises, before forming the stress layer on the buffer layer:

forming a first source region and a first drain region in the substrate at two sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed by using the same patterned photoresist layer as a mask;

When the stress layer is a compressive stress layer, the method for manufacturing the semiconductor device further includes, before forming the stress layer on the buffer layer:

and forming a second source region and a second drain region in the substrate at two sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed by using the same patterned photoresist layer as a mask for forming the buffer layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a tensile stress layer;

the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:

forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;

removing the first buffer layer on the NMOS device region;

forming a second buffer layer on the substrate and the gate structure of the NMOS device region and on the first buffer layer of the PMOS device region;

alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;

And removing part of the buffer layer with the thickness on the NMOS device region.

4. The method of manufacturing a semiconductor device of claim 3, wherein the method of manufacturing a semiconductor device further comprises, before or after removing the first buffer layer on the NMOS device region, or before or after removing a portion of the thickness of the buffer layer on the NMOS device region:

and forming a first source region and a first drain region in the substrate at two sides of the grid structure of the NMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the first source region and the first drain region and removing a first buffer layer on the NMOS device region or removing part of the buffer layer with the thickness on the NMOS device region.

5. The method of manufacturing a semiconductor device according to claim 3, wherein after removing the first buffer layer over the NMOS device region or after removing a portion of the thickness of the buffer layer over the NMOS device region, the method of manufacturing a semiconductor device further comprises:

and forming a second source electrode region and a second drain electrode region in the substrate at two sides of the grid structure of the PMOS device region.

6. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a compressive stress layer;

the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:

forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;

removing the first buffer layer on the PMOS device region;

forming a second buffer layer on the substrate and the gate structure of the PMOS device region and the first buffer layer of the NMOS device region;

alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;

and removing part of the buffer layer with the thickness on the PMOS device region.

7. The method of manufacturing a semiconductor device according to claim 6, wherein before or after removing the first buffer layer on the PMOS device region, or before or after removing a portion of the thickness of the buffer layer on the PMOS device region, the method of manufacturing a semiconductor device further comprises:

And forming a second source region and a second drain region in the substrate at two sides of the grid structure of the PMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the second source region and the second drain region and removing the first buffer layer on the PMOS device region or removing part of the buffer layer with the thickness on the PMOS device region.

8. The method of manufacturing a semiconductor device according to claim 6, wherein after removing the first buffer layer over the PMOS device region or after removing a portion of the thickness of the buffer layer over the PMOS device region, the method of manufacturing a semiconductor device further comprises:

and forming a first source electrode region and a first drain electrode region in the substrate at two sides of the grid structure of the NMOS device region.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device further comprises:

performing an annealing process;

and removing the stress layer.

10. A semiconductor device, comprising:

the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;

The buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure;

a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.

11. The semiconductor device of claim 10, wherein a material of the stress layer comprises silicon nitride and a material of the buffer layer comprises silicon oxide.

12. The semiconductor device according to claim 10, wherein the semiconductor device further comprises:

the first source electrode region and the first drain electrode region are formed in the substrate at two sides of the grid structure of the NMOS device region;

and the second source electrode region and the second drain electrode region are formed in the substrate at two sides of the grid structure of the PMOS device region.

13. The semiconductor device of claim 12, wherein a P-well is formed in a substrate of the NMOS device region, the first source region and the first drain region being formed on top of the P-well; an N-well is formed in the substrate of the PMOS device region, and the second source region and the second drain region are formed on top of the N-well.

Images