CN116301874A - Code compiling method, electronic device and storage medium - Google Patents

Abstract

The embodiment of the application discloses a code compiling method, electronic equipment and a storage medium. The method comprises the following steps: acquiring N code blocks, wherein each code block comprises a state identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2; determining the running sequence of the N code blocks according to the state identifier packaged in each code block; and generating a pipeline according to the running sequence of the N code blocks and the N code blocks. The embodiment of the application is beneficial to improving the production line generation efficiency.

Description

Code compiling method, electronic device and storage medium

technical field

The present application relates to the technical field of computer software, in particular to a code compiling method, electronic equipment and a storage medium.

Background technique

With the development of science and technology and the improvement of the computing power of processors, the requirements for computing speed are getting higher and higher. At present, the pipeline processing mode is a relatively general acceleration method. A common pipeline implementation method uses a double buffer (double buffer) mechanism to achieve parallelism between different task flows, but the double buffer mechanism is difficult to apply to complex task flows. With the increase in the number of tasks in the pipeline, the relationship between multiple tasks is also more complicated. At this time, the analysis of the code is becoming more and more cumbersome and complicated, and it will become difficult to determine the implementation of the pipeline based on the code analysis. Therefore, how to efficiently and quickly construct a multi-task pipeline is a technical problem to be solved urgently.

Contents of the invention

Embodiments of the present application provide a code compiling method, electronic equipment, and a storage medium. By setting state flags in code blocks, the construction efficiency of the pipeline is improved.

In the first aspect, the embodiment of the present application provides a code compilation method, including:

Obtaining N code blocks, wherein each of the code blocks contains a status identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2;

Determine the running order of the N code blocks according to the state identifier encapsulated in each of the code blocks;

A pipeline is generated according to the running sequence of the N code blocks and the N code blocks.

In one embodiment of the present application, the status identifier is used to indicate the task status of the task implemented by the code block, and the N code blocks are determined according to the status identifier encapsulated in each of the code blocks sequence of operations, including:

Determine the dependencies between the N code blocks according to the task states indicated by the state identifiers in the N code blocks;

The running order of the N code blocks is determined according to the dependencies among the N code blocks.

In one embodiment of the present application, the task states of the tasks implemented by the N code blocks include data loading tasks, data computing tasks, and data storage tasks;

In one pipeline, the code block for implementing the data loading task, the code block for the data operation task, and the code block for the data storage task are executed sequentially.

In one embodiment of the present application, the pipeline further includes a code block;

The synchronization code block is included between any two adjacent code blocks in the pipeline;

The synchronization code block is used to indicate that after the i-th code block in the pipeline is executed, the i+1th code block is run, wherein, i is a positive integer greater than or equal to 1, and i is less than or equal to N .

In one embodiment of the present application, each of the code blocks also includes a position identifier, which is used to identify the starting position of the code block in the original code; the acquisition of N code blocks includes:

The code between the jth location identifier and the j+1th location identifier in the original code, and the jth location identifier, as the jth code block, and the value of j is from 1 to N integer.

In one embodiment of the present application, before obtaining the N code blocks, the method further includes:

Obtain the value of the preset flag bit;

When it is determined that the value of the preset flag bit is a preset value, an operation of acquiring N code blocks is performed.

In one embodiment of the present application, the number of the pipelines is at least two, and the method also includes:

According to the state identification of each code block in at least two pipelines, determine the code blocks in different task states in different pipelines as a parallel code block group, and multiple code blocks in the parallel code block group can be executed in parallel within the same time unit .

In one embodiment of the present application, according to the state identification of each code block in at least two pipelines, the code blocks in different task states in different pipelines are determined as parallel code block groups, including:

When the kth code block in the first pipeline is executed, the k-1th code block in the second pipeline is executed in parallel, and the task status of the k-1th code block is the same as that of the first pipeline different task status;

Wherein, the first pipeline is any one of the at least two pipelines, the second pipeline is the next-level pipeline of the first pipeline in the at least two pipelines, and k is greater than or A positive integer equal to 2, and k is less than or equal to N.

In one embodiment of the present application, the method also includes:

Allocating memory for the parallel code block group, wherein the size of the memory is the product of the number of code blocks in the parallel code group and the size of a preset storage space.

In one embodiment of the present application, the method also includes:

Compiling the original code formed by the N code blocks into object code.

In the second aspect, the embodiment of the present application provides a pipeline generation device, including:

An acquisition unit, configured to acquire N code blocks, wherein each of the code blocks contains a status identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2;

A processing unit, configured to determine the running order of the N code blocks according to the state identifier encapsulated in each of the code blocks;

A pipeline is generated according to the running sequence of the N code blocks and the N code blocks.

In one embodiment of the present application, the status identifier is used to indicate the task status of the task implemented by the code block, and according to the status identifier encapsulated in each of the code blocks, determine the status of the N code blocks In terms of running sequence, the processing unit is specifically used for:

Determine the dependencies between the N code blocks according to the task states indicated by the state identifiers in the N code blocks;

The running order of the N code blocks is determined according to the dependencies among the N code blocks.

In one embodiment of the present application, the task states of the tasks implemented by the N code blocks include data loading tasks, data computing tasks, and data storage tasks;

In one pipeline, the code block for implementing the data loading task, the code block for the data operation task, and the code block for the data storage task are executed sequentially.

In one embodiment of the present application, the pipeline further includes a code block;

The synchronization code block is included between any two adjacent code blocks in the pipeline;

The synchronization code block is used to indicate that after the i-th code block in the pipeline is executed, the i+1th code block is run, wherein, i is a positive integer greater than or equal to 1, and i is less than or equal to N .

In one embodiment of the present application, each code block also includes a position identifier, which is used to identify the starting position of the code block in the original code; in terms of obtaining N code blocks, the Get unit, specifically for:

The code between the jth location identifier and the j+1th location identifier in the original code, and the jth location identifier, as the jth code block, and the value of j is from 1 to N integer.

In one embodiment of the present application, before acquiring the N code blocks, the acquisition unit is also used to acquire the value of the preset flag bit; the processing unit is also used to determine the value of the preset flag bit When the value is a preset value, perform the operation of obtaining N code blocks.

In one embodiment of the present application, the number of the pipelines is at least two, and the processing unit is further configured to:

According to the state identification of each code block in at least two pipelines, determine the code blocks in different task states in different pipelines as a parallel code block group, and multiple code blocks in the parallel code block group can be executed in parallel within the same time unit .

In one embodiment of the present application, in terms of determining code blocks in different task states in different pipelines as parallel code block groups according to the state identification of each code block in at least two pipelines, the processing unit is specifically used to :

When the kth code block in the first pipeline is executed, the k-1th code block in the second pipeline is executed in parallel, and the task status of the k-1th code block is the same as that of the first pipeline different task status;

Wherein, the first pipeline is any one of the at least two pipelines, the second pipeline is the next-level pipeline of the first pipeline in the at least two pipelines, and k is greater than or A positive integer equal to 2, and k is less than or equal to N.

In one embodiment of the present application, the processing unit is further configured to allocate memory for the parallel code block group, wherein the size of the memory is equal to the number of code blocks in the parallel code group and the preset storage space The product of sizes.

In one embodiment of the present application, the processing unit is further configured to compile the original code formed by the N code blocks into an object code.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, the processor is connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory , so that the electronic device executes the method described in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program causes a computer to execute the method as described in the first aspect.

In a fifth aspect, an embodiment of the present application provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer is operable to enable the computer to execute the computer program described in the first aspect. Methods.

Implementing the embodiment of the present application has the following beneficial effects:

It can be seen that in the embodiment of the present application, the code block is provided with a state flag, and the running order of the code blocks of each task can be determined directly according to the state flag, without analyzing the function of the code and the data between each code block The flow direction determines the running order of the code blocks of each task, so as to realize the fast and efficient construction of the pipeline. Furthermore, since each code block is encapsulated with a state identifier, for complex task flow scenarios, the present application can generate corresponding pipelines for each task flow according to the above implementation method, and the way of generating pipelines is not It will be limited by hardware resources (such as the number of storage partitions), so that it can support complex task flow scenarios.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1 is a schematic diagram of an implementation process of a double buffering mechanism provided in an embodiment of the present application;

Fig. 2 is a schematic flow chart of a code compiling method provided by the embodiment of the present application;

FIG. 3 is a schematic diagram of an acquisition code block provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of a composition pipeline provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of another composition pipeline provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of another composition pipeline provided by the embodiment of the present application;

FIG. 7 is a block diagram of functional units of a pipeline generating device provided in an embodiment of the present application;

FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, result, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

In order to efficiently perform different tasks and make full use of hardware computing resources, interdependent tasks are often formed into a pipeline, so that tasks that do not have interdependence in different pipelines can be executed in parallel, thereby improving task execution efficiency. . For different processing scenarios, task pipelines can be generated and implemented in many different ways. The purpose of the present disclosure is to provide a multi-stage pipeline generation method, device and related products for complex task flows.

A common pipeline implementation method is to use storage partitions. The data in different storage blocks can be sent to the computing unit in turn for calculation. However, this implementation method can only support simple task flows with at most two pipelines, which is difficult to apply to Scenarios with complex task flows. For example, FIG. 1 shows the process of implementing a task pipeline by adopting a double buffer mechanism (double buffer). The implementation process of the current double buffer mechanism will be introduced below in conjunction with FIG. 1 .

As shown in FIG. 1 , in order to reduce the waiting time of the computing unit, the storage space of the unified cache can be divided into two parts, for example, the unified cache can be divided into a first cache and a second cache. When the operation unit reads and calculates the data in the first cache, the storage unit can write the next piece of data into the second cache in parallel. When the operation unit switches to read and calculate the data in the second cache, the storage unit can write out the calculation results stored in the first cache to the storage unit in parallel, or the storage unit can write the next copy in parallel Data is written into the first cache. Thus, the data access task and the computing task of the computing unit can be executed in parallel, thereby effectively alleviating the idle problem of the computing unit, improving the utilization rate of the computing unit, and improving the execution efficiency of the task. However, the implementation of the double buffering mechanism for each task is to find the code content of each task by parsing the underlying code, and then implement the task based on the code content. For example, for the calculation task of a computing unit in a pipeline, it is necessary to analyze the underlying code to find the code content that can realize the calculation task, and realize the calculation task by executing the code content. However, as the number of tasks in the pipeline increases, the parsing of the code becomes more and more cumbersome and complex. Therefore, how to efficiently construct a pipeline that supports multiple tasks is a technical problem that needs to be solved urgently.

Referring to FIG. 2 , FIG. 2 is a schematic flowchart of a code compiling method provided by an embodiment of the present application. The method can be implemented by a compiler running on a processor (such as a general-purpose processor, CPU, etc.). The method may include the following steps:

201: Obtain N code blocks, where N is an integer greater than or equal to 2.

Among them, the function of each code block is to realize a task, so the execution of a code block mentioned in this application is essentially the execution of a task, and the two are essentially the same without distinction. In addition, different code blocks have different functions, that is, different code blocks are used to implement different types of tasks. In this application, the tasks implemented by N code blocks are mainly illustrated as data loading tasks (data_load), data computing tasks (data_computer) and data storage tasks (data_store). In practical applications, there may also be other The status of the task will not be described in detail.

The application can first obtain the original code, and obtain N code blocks based on the analysis of the original code. Exemplarily, at least one code block identifier, i.e. a position identifier, is preset in the original code; in this way, when parsing the original code, the code between the position identifier and the next location identifier can be used as a code block to obtain N code block.

Specifically, the position identifier can be placed in each code block, and the position identifier is used to identify the starting position of the code block in the original code. Therefore, for the N code blocks, N position identifiers are set in the original code. When parsing the original code, the code between the jth location identifier and the j+1th location identifier, and the jth location identifier are used as the jth code block, and the value of j is an integer from 1 to N.

Optionally, in this application, the code block corresponding to each task is encapsulated through the block-level scope to obtain the original code. The location identifier mentioned in this application can be represented by a block-level identifier, for example, with IR.block. Then, in the process of parsing the original code, if the with IR.block logo is recognized, the with IR.block and the code between the with IR.block and the next with IR.block can be used as a code block to Get N code blocks. Wherein, the IR in the location identifier represents the code level of the original code. In a practicable manner, the code levels of the original code include, but are not limited to, high-level Python codes, low-level Python codes, and lower-level object codes. The object codes may be codes formed in a C-like language ( such as CUDAC). Wherein, the low-level Python code may be a code formed based on a tensor computing primitive constructed in the Python language, for example, TCP (Tensor Computer Primitive) or TIK (Tensor Iterator Kernel).

For example, for the three tasks to be achieved in this application, with tcp.block can be used as a location identifier, as shown in Figure 3, the first with tcp.block and the first with tcp.block can be combined with The code between the second with tcp.block is the first code block, the second with tcp.block, and the code between the second with tcp.block and the third with tcp.block are the second A code block, the code between the third withtcp.block and the end of the code is the third code block.

202: Determine the running order of the N code blocks according to the state identifier encapsulated in each code block.

Wherein, each code block includes a status identifier for determining the running order of the code block.

Exemplarily, the status identifier in each code block may be used to indicate the task status of the task implemented by the code block. Optionally, the status identifier may be represented by the function of each code block itself, that is, the function of each code block itself indicates the task status of the task realized by each code block.

For example, as shown in Figure 3, for the first code block used to implement the data loading task, its state identifier can be "stage_scope=load", therefore, after parsing out the state identifier of the code block is "tage_scope= load", it is determined that the task implemented by the code is a data loading task. For the second code block used to realize the data operation task, its state identifier can be "stage_scope=computer", therefore, when the state identifier of the code block is parsed as "stage_scope=computer", then determine the code The implemented task is a data operation task. For the third code block used to implement the data storage task, its state identifier can be "stage_scope=store", therefore, when the state identifier of the code block is parsed as "stage_scope=store", the code is determined The implemented tasks are data storage tasks. Through the above steps, the present application can respectively obtain three code blocks for realizing the data loading task, the data operation task and the data storage task respectively. Afterwards, the application can determine the running sequence of the three code blocks according to the dependencies among the tasks implemented by the three code blocks.

Further, according to the task status indicated by the status identifiers in the N codes, the dependencies of the N code blocks are determined. The so-called dependency is the flow of data between each code block. Therefore, the running order among the N code blocks can be determined according to the dependencies among the N code blocks.

For example, for data loading tasks, data computing tasks, and data storage tasks, the dependencies are that data computing tasks depend on data loading tasks, and data storage tasks depend on data computing tasks. Therefore, the code blocks corresponding to these three tasks The dependencies among them are: the code block for realizing the data operation task depends on the code block for realizing the data loading task, and the code block for realizing the data storage task depends on the code block for realizing the data operation task. Therefore, in the pipeline, it is necessary to sequentially execute the code block for implementing the data loading task, the code block for implementing the data operation task, and the code block for implementing the data storage task. It should be clear that the data loaded by the data loading task here is the input data of the data operation task, and the data written by the data storage task is the output data of the data operation task. Therefore, there is a data dependency between the three tasks . Otherwise, in other scenarios, data dependencies do not necessarily exist among the above three tasks.

In a possible implementation manner, the running order of the code block may be directly encapsulated in each code block, for example, the state identifier of each code block may be directly set as the running order of the code block. For example, for the code block used to implement the data loading task, its status flag can be set to "1", so that after the code block is obtained, the code block can be directly determined based on the status flag "1". The running order of the code blocks is the first one. It is no longer necessary to determine the dependencies of the N code blocks according to the task status of the tasks implemented by each code block, and then determine the running order of the N code blocks according to the dependencies, thereby improving the pipeline. construction efficiency.

203: Generate a pipeline according to the running order of the N code blocks and the N code blocks.

Exemplarily, according to the running sequence of the N code blocks, the N code blocks are automatically combined to generate a pipeline.

For example, for the three code blocks of the present application, the three code blocks can be composed into a pipeline as shown in FIG. 4 according to the running order of the three code blocks.

It can be seen that, in the embodiment of the present application, the code block is provided with a state flag, and the running order of the code blocks of each task can be determined directly according to the state flag, without analyzing the function of the code and the relationship between each code block. The data flow direction determines the running order of the code blocks of each task, so as to realize the fast and efficient construction of the pipeline. Furthermore, since each code block is encapsulated with a state identifier, for complex task flow scenarios, the present application can generate corresponding pipelines for each task flow according to the above implementation method, and the way of generating pipelines is not It will be limited by hardware resources (such as the number of storage partitions), so that it can support complex task flow scenarios.

In one embodiment of the present application, a synchronization code block is included between any two adjacent code blocks in the pipeline, and the synchronization code block is used to indicate that after running the i-th code block in the pipeline, Run the i+1th code block, where i is a positive integer greater than or equal to 1, and i is less than or equal to N. Although the N code blocks are combined according to the running order, the running time of some code blocks may be relatively long. In order to completely ensure the sequential execution of the N code blocks, insert between two adjacent code blocks A synchronous code block, so that for the two adjacent code blocks, the next code block will only be executed after the previous code block is executed. From the perspective of task execution, each synchronization code block is used to implement a synchronization task, which is equivalent to inserting a synchronization task between two adjacent tasks implemented by any two adjacent code blocks. Two adjacent tasks in the pipeline will only execute the next task after the previous task is executed, so as to realize the sequential execution of N tasks in the pipeline. Inserting a synchronization code block between any two adjacent code blocks in the pipeline can generate a pipeline with the synchronization code block inserted as shown in FIG. 5 .

In an embodiment of the present application, the number of the generated pipelines is at least two, that is, the N code blocks can be composed into two or more pipelines. For each pipeline, it is combined according to the running order of the N code blocks, and will not be described again. For example, for the three code blocks of this application, the three pipelines shown in Figure 6 can be formed according to the order between the code blocks, and any two adjacent code blocks in each pipeline Synchronous code blocks are inserted between each pipeline to ensure that the three code blocks in each pipeline are executed sequentially.

As shown in FIG. 2 or FIG. 6 , the aforementioned pipeline may refer to a serial pipeline formed by timelines. The pipelines of the present application may also include parallel pipelines formed based on different task states. Further, the present application can determine the code blocks in different task states in different pipelines as a parallel code block group according to the state identification of each code block in the at least two pipelines, then the multiple code blocks in the parallel code block group Executed in parallel within the same time unit, the group of parallel code blocks can form a parallel pipeline.

Specifically, the at least two pipelines may have priorities. For example, for the pipelines formed in FIG. 6 , the top pipeline has the highest priority, and the other pipelines have lower priorities in turn. In this application, the priorities of at least two pipelines may be determined based on different iteration periods. For example, the at least two pipelines may be different iteration cycles in the same loop. From the perspective of the timeline, the priority of the pipeline executed earlier is higher than that of the pipeline executed later, and the iteration period of the pipeline executed earlier is smaller than that of the pipeline executed later iteration cycle. As shown in FIG. 6 , one cycle may include three iteration cycles, wherein the three iteration cycles correspond to the three pipelines in FIG. 6 according to their priorities. In this application, in order to improve the parallelism of tasks between different pipelines and improve the execution efficiency of tasks, code blocks in different task states in different pipelines can be determined as parallel code block groups, and then multiple parallel code block groups in the parallel code block groups The code blocks are executed in parallel in the same time unit, so that the task pipeline of the tasks implemented by different code blocks can be realized, and the operation efficiency and hardware utilization rate can be improved.

Since the N code blocks are respectively used to implement different serial tasks, and two adjacent tasks call different hardware resources respectively (for example, two adjacent tasks call two different resources for storage and calculation respectively), therefore, For the at least two pipelines, the way to form a code block group can be:

When the kth code block in the first pipeline is executed, the k-1th code block in the second pipeline is executed in parallel, that is, the kth code block in the first pipeline and the kth code block in the second pipeline The k-1th code block is used as a code block group; wherein, the first pipeline is any one of at least two pipelines, and the second pipeline is the next-level pipeline of the first pipeline in at least two pipelines, k The value of is an integer from 2 to N.

Specifically, hardware resources are limited, and generally two tasks with the same task status will not be executed simultaneously within a time unit. Therefore, for a task with a task status, within a time unit, the corresponding hardware resources to perform the task. Exemplarily, for the three tasks of this application, in the first time unit, storage resources can be allocated for the data loading task of the first pipeline, so as to execute the first code block of the first pipeline; Within two time units, since the first code block of the first pipeline has been executed, computing resources can be allocated to the data operation tasks of the first pipeline, and because storage resources are idle, the first pipeline can be allocated The second code block and the first code block of the second pipeline serve as a code block group, so the storage resources and computing resources can be used to execute the two code blocks in the code block group in parallel within the second time unit. By analogy, in the third time unit, the third code block in the first pipeline, the second code block in the second pipeline, and the first code block in the third pipeline can be used as a In the code block group, three code blocks in the code block group can be executed in parallel by using storage resources and computing resources in the third time unit. Therefore, in the case that multiple pipelines contain N code blocks, in the Nth time unit, the N code blocks can be regarded as a code block group, so that N code blocks can be executed in parallel to realize N tasks of parallel execution.

Furthermore, the present application is also used to insert synchronization tasks between different pipelines to ensure that code blocks can be executed in parallel. That is to say, a synchronous code block is inserted between adjacent code blocks between each iteration cycle to realize synchronous tasks. For example, a synchronization code block is inserted between the code block for completing the data storage task in the first iteration cycle and the code block for completing the data loading task in the second iteration cycle, so as to realize the synchronization task.

In an embodiment of the present application, the method may further include allocating memory for the code block group.

Optionally, the size of the memory is the product of the number of code blocks in the parallel code block group and the size of the preset storage space, and the size of the memory may also be equal to the maximum number of code blocks that can be accommodated in the parallel code block group. Wherein, the preset space size is related to the size of the data to be processed. It can be understood that for each code block group, within the same time unit, all code blocks in the code block group need to be executed in parallel, and each code block needs to have a corresponding memory to cache the running result of the code block. Therefore, according to the number of code blocks in the code block group, memory is allocated for all code blocks at one time, without allocating memory for each code block separately, which can improve memory allocation efficiency.

For example, if the data to be processed is two-dimensional data, the size of the two-dimensional data can be represented by m times n, where m is used to represent the size of the data to be processed in the first dimension, and n is used to represent the data to be processed Size in the second dimension. If the original code needs to complete the processing of the data to be processed, m iteration cycles are required, and each iteration cycle processes the data to be processed with a data size of n. At least three code blocks of a pipeline along the timeline in FIG. 6 are executed in each iteration cycle, that is, data loading tasks, data calculation tasks, and data storage tasks are completed in sequence in each iteration cycle. For the data processing of each iterative cycle, a preset storage space needs to be allocated to complete the processing process of the data to be processed with a data size of n. In the embodiment of the present application, in order to support the implementation of multi-level pipelines, memory can be allocated for the entire parallel code block group at one time, wherein the size of the memory can be equal to the number N in the parallel code block multiplied by the number required in a single iteration cycle The preset storage space size n. As shown in Figure 6, the size of this memory may be 3n.

In an embodiment of the present application, an automatic pipeline generation mode and a normal mode may be included, wherein the automatic pipeline mode refers to automatically generating a pipeline according to the state identification in a code block, such as the method steps shown above. Normal mode refers to the way to generate pipelines according to the traditional code analysis method. In order to support switching between the above two modes, the implementation of the present disclosure may also set a preset flag bit for implementing the mode switching in the original code. Specifically, in the process of parsing the original code, when it is determined that the value of the preset flag is a preset value, it is determined to enable the automatic pipeline generation mode, and when it is determined that the value of the preset flag is not a preset value , it is determined to enable the normal mode, where the preset value can be 1 or other values.

In this embodiment, the flag bit is set in advance. When the value of the preset flag bit is read as the preset value, it is determined that the automatic pipeline generation mode needs to be enabled. At this time, N code blocks will be acquired, and N A code block forms a pipeline in the manner shown in Figure 2 or Figure 6. Specifically, if it is determined to enable the automatic pipeline generation mode, the above memory allocation operation may be automatically completed. If the value of the preset flag bit is not the default value, it is determined to enable the normal mode. At this time, there is no need to obtain N code blocks, and the pipeline is generated directly according to the writing sequence of the original code and according to the traditional code analysis method.

In one embodiment of the present application, the above method may also include:

The original code formed by the N code blocks is compiled into an object code, where the object code can be a code expressed in a C-like language (such as CudaC). In the embodiment of the present application, through the above-mentioned automatic pipeline optimization of the original code, the pipeline-optimized original code can be compiled to generate the target code. Furthermore, the present application can also compile the object code into binary instructions executable by the hardware platform. The hardware platform includes, but is not limited to, a processing unit and a storage unit, wherein the processing unit and the storage unit can complete corresponding operations in a pipeline manner as shown in FIG. 6 .

Referring to FIG. 7 , FIG. 7 is a block diagram of functional units of a pipeline generation device provided by an embodiment of the present application. The pipeline generation device 700 includes:

An acquisition unit 701, configured to acquire N code blocks, wherein each of the code blocks contains a status identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2;

A processing unit 702, configured to determine the running order of the N code blocks according to the status identifier encapsulated in each of the code blocks;

A pipeline is generated according to the running sequence of the N code blocks and the N code blocks.

In one embodiment of the present application, the status identifier is used to indicate the task status of the task implemented by the code block, and according to the status identifier encapsulated in each of the code blocks, determine the status of the N code blocks In terms of running sequence, the processing unit 702 is specifically used to:

Determine the dependencies between the N code blocks according to the task states indicated by the state identifiers in the N code blocks;

The running order of the N code blocks is determined according to the dependencies among the N code blocks.

In one embodiment of the present application, the task states of the tasks implemented by the N code blocks include data loading tasks, data computing tasks, and data storage tasks;

In one pipeline, the code block for implementing the data loading task, the code block for the data operation task, and the code block for the data storage task are executed sequentially.

In one embodiment of the present application, the pipeline further includes a code block;

The synchronization code block is included between any two adjacent code blocks in the pipeline;

The synchronization code block is used to indicate that after the i-th code block in the pipeline is executed, the i+1th code block is run, wherein, i is a positive integer greater than or equal to 1, and i is less than or equal to N .

In one embodiment of the present application, each code block also includes a position identifier, which is used to identify the starting position of the code block in the original code; in terms of obtaining N code blocks, the The acquiring unit 702 is specifically used for:

The code between the jth location identifier and the j+1th location identifier in the original code, and the jth location identifier, as the jth code block, and the value of j is from 1 to N integer.

In one embodiment of the present application, before acquiring N code blocks, the acquiring unit 701 is also used to acquire the value of the preset flag bit; the processing unit 702 is also used to determine the preset flag bit When the value of is a preset value, the operation of obtaining N code blocks is performed.

In one embodiment of the present application, the number of the pipelines is at least two, and the processing unit 702 is further configured to:

According to the state identification of each code block in at least two pipelines, determine the code blocks in different task states in different pipelines as a parallel code block group, and multiple code blocks in the parallel code block group can be executed in parallel within the same time unit .

In one embodiment of the present application, the processing unit 702 specifically uses At:

When the kth code block in the first pipeline is executed, the k-1th code block in the second pipeline is executed in parallel, and the task status of the k-1th code block is the same as that of the first pipeline different task status;

Wherein, the first pipeline is any one of the at least two pipelines, the second pipeline is the next-level pipeline of the first pipeline in the at least two pipelines, and k is greater than or A positive integer equal to 2, and k is less than or equal to N.

In one embodiment of the present application, the processing unit 702 is further configured to allocate memory for the parallel code block group, where the size of the memory is the number of code blocks in the parallel code group and the preset storage The product of the size of the space.

In one embodiment of the present application, the processing unit 702 is further configured to compile the original code formed by the N code blocks into an object code.

Referring to FIG. 8 , FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 8 , an electronic device 800 includes a transceiver 801 , a processor 802 and a memory 803 . They are connected through a bus 804 . The memory 803 is used to store computer programs and data, and can transmit the data stored in the memory 803 to the processor 802 .

The processor 802 is used to read the computer program in the memory 803 to perform the following operations:

Obtaining N code blocks, wherein each of the code blocks contains a status identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2;

Determine the running order of the N code blocks according to the state identifier encapsulated in each of the code blocks;

A pipeline is generated according to the running sequence of the N code blocks and the N code blocks.

For the specific functions of the processor 802, reference may be made to the specific functions of the above-mentioned processing unit 702 and the obtaining unit 701, and will not be described again.

The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement any code compilation method as described in the above-mentioned method embodiments some or all of the steps.

The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable the computer to execute the method described in the above method embodiments Some or all of the steps of any one method of code compilation.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Depending on the application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the application.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented not only in the form of hardware, but also in the form of software program modules.

The integrated units may be stored in a computer-readable memory if implemented in the form of a software program module and sold or used as an independent product. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory. Several instructions are included to make a computer device (which may be a personal computer, server or network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash disk , Read-only memory (English: Read-Only Memory, abbreviated: ROM), random access device (English: Random Access Memory, abbreviated: RAM), magnetic disk or optical disk, etc.

The embodiments of the present application have been introduced in detail above, and specific examples have been used in this paper to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; meanwhile, for Those skilled in the art will have changes in specific implementation methods and application scopes based on the ideas of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims (11)

1. A code compiling method, comprising:

acquiring N code blocks, wherein each code block comprises a state identifier for determining the running sequence of the code block, and N is an integer greater than or equal to 2;

Determining the running sequence of the N code blocks according to the state identifier packaged in each code block;

and generating a pipeline according to the running sequence of the N code blocks and the N code blocks.

2. The method of claim 1, wherein the status identifiers are used to indicate task status of tasks implemented by the code blocks, and wherein determining the running order of the N code blocks according to the status identifiers encapsulated in each code block comprises:

determining the dependency relationship among the N code blocks according to the task state indicated by the state identification in the N code blocks;

and determining the running sequence of the N code blocks according to the dependency relationship among the N code blocks.

3. The method according to claim 1 or 2, wherein the task states of the tasks implemented by the N code blocks include a data loading task, a data operation task and a data storage task;

in one pipeline, the code blocks implementing the data loading task, the code blocks of the data operation task, and the code blocks of the data storage task are sequentially executed.

4. A method according to any one of claims 1-3, wherein each of said code blocks further comprises a location identifier for identifying the starting location of the code block in the original code; the acquiring N code blocks includes:

And taking a code between a j-th position identifier and a j+1th position identifier in the original code and the j-th position identifier as a j-th code block, wherein the j value is an integer from 1 to N.

5. The method of any of claims 1-4, wherein the number of pipelines is at least two, the method further comprising:

according to the state identification of each code block in at least two pipelines, code blocks in different task states in different pipelines are determined to be parallel code block groups, and a plurality of code blocks in the parallel code block groups can be executed in parallel in the same time unit.

6. The method of claim 5, wherein determining code blocks in different task states in different pipelines as parallel code block groups based on the state identification of each code block in at least two pipelines, comprises:

executing a kth code block in a first pipeline in parallel with a kth-1 code block in a second pipeline, the task state of the kth-1 code block being different from the task state of the first pipeline;

the first pipeline is any one of the at least two pipelines, the second pipeline is a next stage pipeline of the first pipeline of the at least two pipelines, k is a positive integer greater than or equal to 2, and k is less than or equal to N.

7. The method according to claim 5 or 6, characterized in that the method further comprises:

and allocating a memory for the parallel code block group, wherein the size of the memory is the product of the number of the code blocks in the parallel code block group and the size of a preset storage space.

8. The method according to any one of claims 1-7, further comprising:

acquiring the value of a preset marker bit;

and when the value of the preset flag bit is determined to be a preset value, entering an automatic pipeline generation mode to automatically generate a pipeline according to the state identification packaged in each code block.

9. The method according to any one of claims 1-8, further comprising:

and compiling the original codes formed by the N code blocks into target codes.

10. An electronic device, comprising: a processor and a memory, the processor being connected to the memory, the memory being for storing a computer program, the processor being for executing the computer program stored in the memory to cause the electronic device to perform the method of any one of claims 1-9.

11. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, which is executed by a processor to implement the method of any one of claims 1-9.

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