CN116306825A - Hardware acceleration circuit, data processing acceleration method, chip and accelerator - Google Patents

Abstract

The application relates to a hardware acceleration circuit, a data processing acceleration method, a chip and an accelerator. The hardware acceleration circuit includes: an exponential function module, used to obtain multiple exponential function values of multiple data elements in the data set; an adder, used to obtain the addition operation results of the multiple exponential function values; a first processing circuit, It is used to perform preset processing on the addition result, so as to process the addition result into at least first data and second data; a second processing circuit is used to at least perform processing on the first data and second data preset processing, to obtain the reciprocal of the addition result; a third processing circuit, configured to perform preset processing on the exponential function value of the i-th data element among the plurality of data elements and the reciprocal, to obtain The specific function value of the ith data element. The solution provided by the present application can reduce the calculation amount of data processing, thereby improving the acquisition speed of nonlinear function values.

Description

Hardware acceleration circuit, data processing acceleration method, chip and accelerator

technical field

The present application relates to the technical field of artificial intelligence, and in particular to a hardware acceleration circuit, a data processing acceleration method, a chip and an accelerator.

Background technique

Nonlinear functions introduce nonlinear characteristics into artificial neural networks, which play a very important role in learning and understanding complex scenes for artificial neural networks. Non-linear functions include, but are not limited to: softmax (Softmax) function, Sigmoid function, and the like.

Take the Softmax function as an example, which is widely used in deep learning. In the related art, the function value of the Softmax function can be calculated by a general computing unit, such as a central processing unit (CPU) or a graphics processing unit (GPU). However, when the processing of the neural network is executed by hardware circuits such as a deep learning accelerator (Deep Learning Accelerator, DLA for short) or a neural network processor (Neural Network Processing Unit, NPU for short), if the Softmax function layer is located in the neural network The middle layer of the network will cause job migration (jobmigration) overhead between DLA/NPU and CPU/GPU, making the solution of using CPU/GPU to determine the nonlinear function value inefficient, resulting in increased system bandwidth and higher power consumption .

Contents of the invention

In order to solve or partly solve the problems existing in related technologies, the application provides a hardware acceleration circuit, data processing acceleration method, chip and accelerator, which can reduce the amount of data processing calculations, thereby improving the acquisition speed of nonlinear function values.

The present application provides a hardware acceleration circuit on the one hand, and the hardware acceleration circuit includes:

Exponential function module, is used for obtaining multiple exponential function values of multiple data elements in the data set;

an adder, configured to obtain an addition result of the plurality of exponential function values;

The first processing circuit is configured to perform preset processing on the addition result, so as to process the addition result into at least first data and second data, wherein the length of the addition result is N1 bits, so The length of the first data is N2 bits, the length of the second data is N3 bits, and both N2 and N3 are smaller than N1;

A second processing circuit, configured to perform preset processing on at least the first data and the second data, so as to obtain the reciprocal of the addition result;

The third processing circuit is configured to perform preset processing on the exponential function value and the reciprocal of the i-th data element among the plurality of data elements, so as to obtain the specific function value of the i-th data element.

Another aspect of the present application provides an artificial intelligence chip, including the above-mentioned hardware acceleration circuit.

Another aspect of the present application provides a data processing acceleration method, which is applied to an artificial intelligence accelerator, and the method includes:

Obtain multiple exponential function values for multiple data elements in the data set;

obtaining an addition operation result of the plurality of exponential function values;

obtaining the reciprocal of the result of the addition operation;

Obtaining a specific function value of the i-th data element based on the exponential function value and the reciprocal of the i-th data element among the plurality of data elements;

Wherein, obtaining the reciprocal of the addition operation result includes:

processing the addition operation result into at least first data and second data;

Obtaining the reciprocal of the addition result based on at least the first data and the second data;

Wherein, the length of the addition operation result is N1 bits, the length of the first data is N2 bits, the length of the second data is N3 bits, and both N2 and N3 are smaller than N1.

Another aspect of the present application provides an artificial intelligence accelerator, including:

processor; and

A memory, on which executable codes are stored, which, when executed by the processor, cause the processor to perform the method as described above.

The technical solution provided by this application may include the following beneficial effects:

In the technical solution of the embodiment of the present application, the addition result of the exponential function value of each data element is at least processed into the first data and the second data whose length is lower than the addition result, and through at least the first data and the second data Preset processing is performed to obtain the reciprocal of the result of the addition operation. By reducing the bit width of the processed data, the calculation amount of data processing can be reduced, thereby improving the acquisition speed of the nonlinear function value.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Description of drawings

The above and other objects, features and advantages of the present application will become more apparent by describing the exemplary embodiments of the present application in more detail with reference to the accompanying drawings, wherein, in the exemplary embodiments of the present application, the same reference numerals generally represent same parts.

Fig. 1 is a schematic structural diagram of a neural network shown in an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a neural network for classification shown in an embodiment of the present application;

FIG. 3 is a structural block diagram of a hardware acceleration circuit according to an embodiment of the present application;

FIG. 4A is a structural block diagram of a hardware acceleration circuit according to another embodiment of the present application;

Fig. 4B is a schematic structural diagram of a basic look-up table circuit unit according to an embodiment of the present application;

FIG. 5 is a structural block diagram of a hardware acceleration circuit according to another embodiment of the present application;

FIG. 6 is a structural block diagram of a hardware acceleration circuit shown in another embodiment of the present application;

7 to 9 are schematic flowcharts of data processing acceleration methods in some embodiments of the present application;

Fig. 10 is a structural block diagram of an artificial intelligence accelerator according to an embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of this application to those skilled in the art.

The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first", "second", "third" and so on may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

The calculation process of the nonlinear function may involve the calculation process of the exponential function and/or the reciprocal, for example, the calculation process of the Softmax function may involve the calculation process of the exponent (exp) and the reciprocal of the sum of the exponents (1/sum_of_exp).

An embodiment of the present application provides a data processing acceleration solution, which processes the addition result of the exponential function value of each data element at least as the first data and the second data whose length (that is, the bit width) is lower than the addition result, and passes at least Preset processing is performed on the first data and the second data to obtain the reciprocal of the addition result. By reducing the bit width of the processed data, the calculation amount of data processing can be reduced, thereby increasing the acquisition speed of the nonlinear function value.

FIG. 1 is a schematic structural diagram of a neural network shown in an embodiment of the present application.

Referring to FIG. 1 , a topology structure of a neural network 100 is shown, including an input layer, a hidden layer and an output layer. The neural network 100 is capable of performing calculations or operations based on the data elements I ₁ , I ₂ received by the input layer and generating output data O ₁ , O ₂ based on the results of the performed calculations.

For example, the neural network 100 may be a deep neural network (Deep Neural Networks, DNN for short) including one or more hidden layers. The neural network 100 in FIG. 1 includes an input layer L1, two hidden layers L2, L3 and an output layer L4. Among them, DNN includes but is not limited to convolutional neural network (Convolutional Neural Networks, referred to as CNN) and recurrent neural network (Recurrent Neural Network, referred to as RNN).

It should be noted that the four layers shown in FIG. 1 are only for the convenience of understanding the technical solution of the present application, and should not be construed as limiting the present application. For example, a neural network may include more or fewer hidden layers.

Nodes in different layers of the neural network 100 can be connected to each other for data transmission. For example, a node may receive data from other nodes to perform calculations on the received data, and output calculation results to nodes in other layers.

表示第一层的第一个节点与第二层的第一个节点之间的权重。/>

表示第一层的第一个节点的输出数据。/>

表示第二层中的第一个节点的偏置值，则第二层的第一个节点的输出数据可以表示为：/>

其它节点的输出数据的计算方式类似，在此不再详述。Each node may determine output data for that node based on output data and weights received from nodes in previous layers. For example, in Figure 1

Indicates the weight between the first node of the first layer and the first node of the second layer. />

Represents the output data of the first node of the first layer. />

Indicates the bias value of the first node in the second layer, then the output data of the first node in the second layer can be expressed as: />

The calculation methods of the output data of other nodes are similar and will not be described in detail here.

In some embodiments, the neural network is configured with an activation function layer, such as a softmax (softmax) function layer, and the softmax function layer can convert the result value of each class into a probability value.

In some embodiments, the neural network is configured with a loss function layer after the flexible maximum function layer, and the loss function layer can calculate loss as an objective function for training or learning.

It can be understood that the neural network can respond to the data to be processed, and obtain a recognition result after processing the data to be processed; the data to be processed can include at least one of voice data, text data and image data, for example.

A typical type of neural network is a neural network for classification. A neural network for classification can determine the class to which a data element belongs by calculating the probability that the data element corresponds to each class.

Fig. 2 is a schematic structural diagram of a neural network for classification shown in an embodiment of the present application.

Referring to FIG. 2 , the neural network 200 for classification in this embodiment may include a hidden layer 210 , a fully connected layer (FullConnect Layer, FC layer for short) 220 , a flexible maximum function layer 230 and a loss function layer 240 .

As shown in FIG. 2 , the neural network 200 performs calculations in sequence in response to the data to be processed in the order of the hidden layer 210 and the FC layer 220 , and the FC layer 220 outputs a calculation result s, which corresponds to the classification probability of the data element. Wherein, the FC layer 220 may include a plurality of nodes respectively corresponding to a plurality of classes, and each node outputs a result value corresponding to a probability that a data element is classified into a corresponding class. For example, referring to Fig. 1 together, the FC layer 220 corresponds to the output layer L4 in Fig. 1, has two nodes, and corresponds to two classifications (the first class and the second class), then the output value of one of the nodes can be represented The resulting value of the probability that the data element is classified into the first class, and the output value of the other node may be a result value representing the probability of the data element being classified into the second class. The FC layer 220 outputs the calculation result s to the flexible maximum function layer 230, and the flexible maximum function layer 230 converts the calculation result s into a probability value y, and can also perform normalization processing on the probability value y.

The softmax function layer 230 outputs the probability value y to the loss function layer 240 , and the loss function layer 240 can calculate the cross-entropy loss (cross-entropy loss) L of the result s based on the probability value y.

然后，FC层220执行基于交叉熵损失L的梯度的学习处理。例如，可根据梯度下降算法来更新FC层220的权重。进一步的，可在隐藏层210中执行后续的学习处理。During the backpropagation learning process, the softmax function layer 230 calculates the gradient of the cross-entropy loss L

Then, the FC layer 220 performs learning processing based on the gradient of the cross-entropy loss L. For example, the weights of the FC layer 220 may be updated according to a gradient descent algorithm. Further, subsequent learning processing may be performed in the hidden layer 210 .

The neural network 200 can be implemented by software, or by hardware circuits, or by a combination of software and hardware. For example, in the case of hardware circuit implementation, the hidden layer 210, FC layer 220, flexible maximum function layer 230, and loss function layer 240 are all implemented by hardware circuits, which can be integrated in an artificial intelligence chip, or distributed among multiple chips accomplish. Through such a configuration, when the flexible maximum function layer 230 is implemented by CPU/GPU, data migration between other layers of the neural network and processors such as CPU/GPU can be avoided, the efficiency of neural network data processing can be improved, and the data processing delay can be reduced. time and power consumption, and avoid increasing occupied bandwidth.

The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

FIG. 3 is a structural block diagram of a hardware acceleration circuit according to an embodiment of the present application. In the present application, the hardware acceleration circuit, for example, can be used but not limited to realize the flexible maximum function layer 230 in the above-mentioned neural network 200, and the hardware acceleration circuit can be, for example but not limited to, a CPLD (Complex Programming logic device, complex programmable logic device) chip , FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips, circuit components in special chips, etc.

In order to facilitate the understanding of this application, the Softmax function is explained as follows. Assuming that there is an array X, the calculation formula of the Softmax function value of the i-th element x _i can be shown in formula (1).

表示数组X中至少部分元素的指数函数值的加法运算结果。In formula (1), σ(x) _i represents the Softmax function value of the i-th element x _i , e is a natural constant, x _i represents the i-th element of the array X, and c represents the largest element in the array X,

Represents the result of the addition of the values of the exponential function for at least some of the elements in array X.

Referring to FIG. 3 , a hardware acceleration circuit includes an exponential function module 11, an adder 21, a first processing circuit 31, a second processing circuit 32, a third processing circuit 33,

Exponential function module 11, configured to obtain multiple exponential function values of multiple data elements in the data set.

In one embodiment, the exponential function module 11 can respond to the index value of each data element in the data set, output the index function value corresponding to each data element based on the first lookup table, and output the respective indices of all data elements in the data set function value.

The adder 21 is used to obtain the addition operation result of a plurality of exponential function values.

In one embodiment, the adder 21 may perform an addition operation on the respective exponential function values of all the data elements according to the respective exponential function values of all the data elements input by the exponential function module 11, and output the sum of the exponential function values of all the data elements in the data set The result of the addition operation.

It can be understood that the addition result of the exponential function value may be a result obtained by directly adding the exponential function value, or may be a result obtained by performing an addition operation on the exponential function value after a specific transformation. For the case of performing a specific transformation, depending on the transformation type, corresponding inverse transformation may be performed on the subsequently obtained data processing results or no other inverse transformation processing shall be performed. Similarly, the processing of other data should also be broadly understood to include the above two situations, and should not be limited to the processing of the data itself. Other embodiments are similar and will not be described in detail below.

The first processing circuit 31 is configured to perform preset processing on the addition result, so as to process the addition result into at least first data and second data.

In one embodiment, the length of the addition operation result output by the adder 21 is N1 bits, and the first processing circuit 31 can perform data conversion on the addition operation result whose length is N1 bits, and output the first data and the second data, the first The length of the data is N2 bits, the length of the second data is N3 bits, and both N2 and N3 are smaller than N1.

The second processing circuit 32 is configured to perform preset processing on at least the first data and the second data, so as to obtain the reciprocal of the addition result.

In one embodiment, the second processing circuit 32 performs preset processing on the first data and the second data, and in response to the first data and the second data, outputs a lookup table corresponding to the first data and the second data based on a corresponding lookup table. For the table result, the reciprocal of the addition operation result is obtained by performing data operations on the table lookup results corresponding to the first data and the second data.

The third processing circuit 33 is configured to perform preset processing on the exponential function value and reciprocal of the i-th data element among the plurality of data elements, so as to obtain a specific function value of the i-th data element.

In an embodiment, the third processing circuit 33 may perform a multiplication operation on the exponential function value of the i-th data element among the plurality of data elements and the reciprocal of the addition result, and output the flexible maximum function value of the i-th data element.

In this embodiment, the addition result of the exponential function value of each data element is at least treated as the first data and the second data whose length (that is, the bit width) is lower than the addition result, and at least the first data and the second The data is pre-processed to obtain the reciprocal of the result of the addition operation. By reducing the bit width of the processed data, the calculation amount of data processing can be reduced, thereby improving the acquisition speed of nonlinear function values.

FIG. 4A is a structural block diagram of a hardware acceleration circuit shown in another embodiment of the present application.

Referring to FIG. 4A , a hardware acceleration circuit includes an exponential function module 11 , an adder 21 , a first processing circuit 31 , a second processing circuit 32 , and a third processing circuit 33 .

The exponential function module 11 includes a first lookup table circuit 1101; the first lookup table circuit 1101 is configured to obtain multiple exponential function values corresponding to multiple data elements in the data set based on the first lookup table.

The first lookup table circuit 1101 may output the exponential function value corresponding to each data element based on the first lookup table, and output the respective N4-bit exponential function values of all data elements in the data set.

The adder 21 is used to obtain the addition operation result of a plurality of exponential function values.

In one embodiment, the adder 21 may perform addition operation on the respective N4-bit exponential function values of all data elements according to the respective N4-bit exponential function values of all data elements input by the exponential function module 11, and output all data of the data set The addition operation result of the exponential function value of the element, and the addition operation result may be an N1-bit fixed-point integer.

The first processing circuit 31 includes an integer-to-floating-point conversion circuit 311; an integer-to-floating-point conversion circuit 311 is used to convert the addition result from an integer to a floating-point number represented by the first exponent data and the first mantissa data.

In a specific implementation, the integer-to-floating-point conversion circuit 311 includes: a leading 0 counting circuit or a leading 1 detection circuit, a shifter and a subtractor.

The leading 0 counting circuit is used to output the number of leading 0s in the result of the addition operation; the number of leading 0s is the number of 0s that appear between scanning from the highest bit of binary data to the first 1. The leading 1 detection circuit is used to output the number of digits of the leading 1 in the result of the addition operation; the leading 1 is the first 1 scanned from the highest bit of the binary data.

The shifter is used to output the first mantissa data of the addition operation result according to the number of leading 0s or the number of digits of the leading 1; in a specific implementation, the shifter uses the number of leading 0s as the number of shift bits to shift the addition result to the left The number of bits shifted, the output bit width is the shifted data of N3 bits, that is, the data of N3 consecutive bits is intercepted from the next bit of the leading 1 to the low bit direction from the addition result, as the result of the addition First mantissa data.

The subtractor is used for subtracting a preset value and the number of leading 0s or the number of leading 1s, so as to output the first exponent data of the addition result.

The second processing circuit 32 includes a first conversion circuit 321 , a second conversion circuit 322 and a third conversion circuit 323 .

The first conversion circuit 321 is used for converting the first exponent data into a negative number.

In one embodiment, the first conversion circuit 321 includes a second lookup table circuit 3212; the second lookup table circuit 3212 is configured to output a negative number corresponding to the first exponent data based on the second lookup table.

The second conversion circuit 322 is used for converting the fractional part of the floating point number represented by the first exponent data and the first mantissa data into another floating point number represented by the second exponent data and the second mantissa data according to the first mantissa data.

In one embodiment, the second conversion circuit 322 includes a third lookup table circuit 3223 and a fourth lookup table circuit 3224; the third lookup table circuit 3223 is used to obtain the first mantissa corresponding to the first mantissa data based on the third lookup table. The second exponent data exp2; the fourth look-up table circuit 3224, configured to obtain the second mantissa data frac1 corresponding to the first mantissa data based on the fourth look-up table.

The third conversion circuit 323 includes an exponent adder 3231 and a shifter 3232 . The exponent adder 3231 is used to obtain the sum of the negative number of the first exponent data and the second exponent data; the shifter 3232 is used to use the sum value as a shift parameter to perform shift processing on the second mantissa data to obtain an addition operation The inverse of the result.

It can be understood that the shift processing on the second mantissa data may be performed after necessary conversion or processing (such as 1-complement processing mentioned later) on the second mantissa data.

The third processing circuit 33 includes a multiplier 331 for adding the exponential function value of the i-th data element among the multiple data elements output by the exponential function module 11 and the multiple exponential function values output by the second processing circuit 32 The reciprocal of the result is multiplied, and the value of the softmax function for the ith data element is output.

It can be understood that, in some other embodiments, part or all of the table look-up manner in the above process may also be replaced by software calculation by a processor (such as CPU or GPU).

A more detailed description will be given below in conjunction with the formula.

In one embodiment, the floating-point expression of the addition operation result fp0 is:

Then its reciprocal can be expressed as:

make

but:

In combination with the above formula, the integer-to-floating-point conversion circuit 311 converts the addition operation result fp0 in fixed-point integer format into a floating-point number represented by the first exponent data exp0 and the first mantissa data frac0. The second lookup table circuit 3212 outputs a negative number -exp0 corresponding to the first exponent data exp0 based on the second lookup table. The circuit 3223 of the second converting circuit 322 outputs the second exponent data exp1 corresponding to the first mantissa data frac0 based on the third lookup table. The fourth lookup table circuit 3224 of the second conversion circuit 322 outputs the second mantissa data frac1 corresponding to the first mantissa data frac0 based on the fourth lookup table.

可通过将2^{-exp 0+exp 1}与

相乘获得。在一个具体实现中，可以将/>

补1后，将-exp0+exp1的结果作为移位参数，对/>

进行移位获得。As shown in the above formula, the reciprocal of the addition result fp0

can be obtained by combining 2 ^{-exp 0+exp 1} with

Multiply to get. In a specific implementation, the /> can be

After complementing 1, the result of -exp0+exp1 is used as a shift parameter, for />

Obtained by shifting.

It can be understood that the conversion of fp0 and frac0 in the above formula is an approximate conversion, and the error caused by the conversion has negligible impact on the calculation accuracy in the application.

The third processing circuit 33 is used to multiply the N4-bit exponential function value of the i-th data element and the reciprocal of the N5-bit addition result of the multiple data elements, so as to obtain the N6-bit index of the i-th data element The result of the multiplication operation. Further, the N6-bit multiplication result can be converted, for example, converted to an N7-bit result with a lower bit width, and the converted result can be used as the flexible maximum function value of the i-th data element output by the hardware acceleration circuit . It can be understood that converting the result of the multiplication operation from a bit width of N6 bits to N7 bits can be realized, for example, by saturating, rounding, and the like. Rounding processing includes, for example, rounding, rounding up, rounding down, rounding toward zero, and the like.

In one embodiment, the length of the first exponent data and the second exponent data can be both N2 bits, the length of the first mantissa data and the second mantissa data can be both N3 bits; the values of N2 and N3 can be in [1, 32], in some specific examples, the value range can be [8, 12], and N2 and N3 can be equal or unequal.

In this embodiment, the first lookup table, the second lookup table, the third lookup table and the fourth lookup table can be stored in a storage module, and the storage module can be, for example, RAM (Random-Access Memory, random access memory), ROM (Read-Only Memory, read-only memory), FLASH, etc.

In one embodiment, the hardware acceleration circuit includes at least two look-up table circuits from the first look-up table circuit to the fourth look-up table circuit, that is, includes two, three or all of the look-up table circuits, and at least two look-up table circuits Each has a basic look-up table circuit element.

Referring to shown in Fig. 4B, in one embodiment, basic look-up table circuit unit 20 comprises input terminal group 22, control terminal group 23, output terminal group 24 and logic circuit 21; Input terminal group 22 is connected with memory 10, will look-up table The data input logic circuit 21; The logic circuit 21 selects the value corresponding to the index value in the lookup table through the index value (also called address) input from the control terminal group 23, and outputs from the output terminal group 24. The logic circuit 21 may be, for example, a logic gate circuit or a logic switch circuit. It can be understood that in this application, a terminal group refers to a group of connection terminals, including one or more connection terminals. In the case where the control terminal group 23 has A control terminals and the output terminal group 24 has B output terminals, the basic lookup table circuit unit 20 is called A input and B output.

The basic look-up table circuit unit 20 can perform a table look-up output based on the stored look-up table. Taking the first lookup table as an example, the lookup table also has A input and B output, the data element of the lookup table is an index value with a bit width of A bits, and the output data is an exponential function value with a bit width of B bits. The first lookup table in the storage area stores the true value of the exponential function value, and the basic lookup table circuit unit is used to realize the mapping relationship between the index value and the true value of the exponential function value.

Taking the first look-up table circuit to the fourth look-up table circuit of the hardware acceleration circuit as an example each having a basic look-up table circuit unit, the storage module includes a first storage area to a fourth storage area, and the first look-up table to the fourth look-up table respectively store In the first storage area to the fourth storage area; the first look-up table circuit includes the first basic look-up table circuit unit, the second look-up table circuit includes the second basic look-up table circuit unit, and the third look-up table circuit includes the third basic look-up table The circuit unit, the fourth look-up table circuit includes a fourth basic look-up table circuit unit. The first basic lookup table circuit unit is connected to the first storage area, and is used to output the corresponding exponential function value stored in the first lookup table of the first storage area in response to the index value of the i-th data element; the second basic lookup The table circuit unit is connected with the second storage area, and is used to output the corresponding negative number stored in the second lookup table of the second storage area in response to the index value of the first index data; the third basic lookup table circuit unit is connected with the third storage area The area connection is used to respond to the index value of the first mantissa data, and output the corresponding second index data stored in the third look-up table of the third storage area; the fourth basic look-up table circuit unit is connected with the fourth storage area, using In response to the index value corresponding to the first mantissa data, the corresponding second mantissa data stored in the fourth lookup table of the fourth storage area is output. In another embodiment, the hardware acceleration circuit includes at least two look-up table circuits among the first look-up table circuit to the fourth look-up table circuit, and some of the look-up table circuits share one basic look-up table circuit unit. By multiplexing the basic lookup table circuit units, the required basic lookup table circuit units can be reduced, thereby effectively reducing the area and cost of the lookup hardware acceleration circuit.

Taking the first look-up table circuit and the second look-up table circuit of the hardware acceleration circuit as an example sharing a basic look-up table circuit unit (for example, called the first basic look-up table circuit unit), the first basic look-up table circuit unit includes a first input The terminal group, the first control terminal group, the first output terminal group and the first logic gate circuit, the first input terminal group is connected with the storage module, and the first logic gate circuit is used for: in the first time period, in response to the first control an index value of the i-th data element input by the terminal group, an exponential function value corresponding to the i-th data element output from the first output terminal group based on the first lookup table, and, at a second time after the first time period A segment, in response to an index value of the first exponent data input from the first control terminal group, outputs a negative number corresponding to the first exponent data from the first output terminal group based on the second lookup table.

It can be understood that in a specific implementation of this embodiment, the storage module includes a first storage area, and the first lookup table and the second lookup table are stored in the first storage area in time division. Since only one storage area needs to be configured for time-sharing storage of any one of the first lookup table and the second lookup table, the storage space occupied by the lookup table is effectively reduced, and the hardware cost can be reduced. In another specific implementation, the storage module includes a first storage area and a second storage area, the first lookup table is stored in the first storage area, and the second lookup table is stored in the second storage area.

It can be understood that in this application, the index value of a certain data may be the data itself, or it may be obtained after specific transformation of the data.

In this embodiment, the exponential function value of each data element is obtained by means of a table lookup through the hardware lookup table circuit, the addition result of the exponential function value is obtained through the adder, and the addition result is converted into a plurality of data with lower bit widths. part, and then realize the division operation of the addition result through table lookup and subsequent addition and multiplication processing, and obtain the corresponding reciprocal of the addition result; because complex exponential operations and reciprocal operations are avoided, the nonlinear function calculation process can be improved. Data processing speed, faster acquisition of nonlinear function values. On the other hand, excessive hardware circuit area and high cost for realizing exponential operation and reciprocal operation are avoided.

Further, through the table lookup of three lower bit width data, that is, after the result of the addition operation is converted from an integer to a floating point number represented by the first exponent data and the first mantissa data whose bit width is reduced, through the first lookup The table obtains the negative number of the first exponent data, and obtains the second exponent data and the second mantissa data through the second lookup table and the third lookup table, which can significantly reduce the dependence of the lookup table on a large storage space, and reduce the area and size of the lookup table logic circuit. Cost, speed up table lookup time, and then improve data processing speed.

For example, if the result of the addition operation is a 16-bit integer, the lookup table required for direct table lookup includes 2^16 (i.e. 65536) entries, which requires a large storage space to store data, and causes the cost of the lookup table logic circuit to be too high. high. On the other hand, it takes 65536 cycles to complete a single table lookup result, and the processing time is too long. In this application, for example, the 16-bit addition result can be converted from an integer to a floating-point number represented by the first exponent data of 8 bits and the first mantissa data of 8 bits, and the first look-up table to the third The lookup table is configured as 8 inputs and 8 outputs, then the total number of entries of the three lookup tables is 3× ²⁸ =768; obviously, the latter greatly saves the storage space required by the lookup table, the area and cost of the lookup table logic circuit , and speed up the table lookup.

FIG. 5 is a structural block diagram of a hardware acceleration circuit shown in another embodiment of the present application.

Referring to FIG. 5 , a hardware acceleration circuit includes an exponential function module 11 , an adder 21 , a first processing circuit 31 , a second processing circuit 32 , and a third processing circuit 33 .

Exponential function module 11, configured to obtain multiple exponential function values of multiple data elements in the data set.

The adder 21 is used to obtain the addition operation result of a plurality of exponential function values.

In this embodiment, the result of the addition operation is a floating point number. The adder 21 can add the respective N4-bit exponential function values of all data elements according to the respective N4-bit exponential function values of all data elements input by the exponential function module 11, and output the exponential function values of all data elements in the data set. The addition operation result of N1-bit floating-point type.

The first processing circuit 31 includes a third look-up table circuit 313 and a fourth look-up table circuit 314; the third look-up table circuit 313 is used to obtain index data corresponding to the addition result based on the third look-up table; the fourth look-up table circuit 314 It is used for obtaining the mantissa data corresponding to the addition operation result based on the fourth lookup table.

The second processing circuit 32 is configured to perform preset processing on the exponent data and the mantissa data, so as to obtain the reciprocal of the addition operation result.

The third processing circuit 33 is configured to perform preset processing on the exponential function value and reciprocal of the i-th data element among the plurality of data elements, so as to obtain a specific function value of the i-th data element.

FIG. 6 is a structural block diagram of a hardware acceleration circuit shown in another embodiment of the present application.

Referring to FIG. 6 , a hardware acceleration circuit includes a subtractor 61 , an exponential function module 11 , an adder 21 , a first processing circuit 31 , a second processing circuit 32 , and a third processing circuit 33 .

The subtractor 61 is configured to subtract the multiple initial data in the initial data set from the maximum value among the multiple initial data, so as to obtain a data set including multiple data elements.

The exponential function module 11 includes a first lookup table circuit 1101; the first lookup table circuit 1101 is configured to obtain multiple exponential function values corresponding to multiple data elements in the data set based on the first lookup table.

In a specific embodiment, a mathematical transformation is performed on the initial data set input to the hardware acceleration circuit, so that the element x _i =xi _′ -c is used to subtract each initial data in the initial data set X and the initial data set The maximum value is subtracted, and the data elements corresponding to each initial data in the initial data set X are output, and the data set is composed of data elements corresponding to each initial data in the initial data set X, and the extraction of each data element in the data set The value is 0 or a negative number. Subtracting multiple initial data in the initial data set by the subtractor 61 can reduce the value range of the data elements, thereby facilitating the realization of the solution of the present application with less bit-width data and corresponding hardware circuits. On the other hand, the value of each data element in the data set is a negative number or 0, so that the value of the exponential function of the data element with e as the base can be normalized to a range of (0, 1].

In order to better understand the lookup process of this embodiment, the following table 1 shows a specific example of the first lookup table, which is N0 bit input and N4 bit output, where N0 and N4 are both 8. The data element of the first lookup table may be an index value with a bit width of N0 bits, and the output data may be an exponential function value with a bit width of N4 bits. For ease of understanding, the data in Table 1 are expressed in decimal format. It can be understood that the first lookup table in the storage module only stores the true value of the exponential function value, and the first lookup table circuit is used to realize the mapping relationship between the index value and the true value of the exponential function value, and the data elements and the normalized exponential function Values are included in the table for better understanding of the application.

Table 1

As shown in Table 1, the data element output by the subtractor 61 is a negative number or 0, and the value range of the data element is defined as [-10, 0]. In order to look up the table, the value range [-10, 0] is discretized into 256 points (that is, 2 ^N0 ) as shown in the column "data element", and the index function value corresponding to each point is shown in the column "normalized exponent function value", each data element point corresponds to an integer value in the range [0, 255] shown in the column "index value", and each normalized exponential function value corresponds to the column "exponential function value" An integer value within the range of [0, 255] shown, the data in the column "exponential function value" is stored in the first lookup table of the storage module as a true value, and the table lookup can be realized through the index value.

For the implementation of the adder 21 , the first processing circuit 31 , the second processing circuit 32 , and the third processing circuit 33 , reference may be made to the previous implementation examples, and details are not repeated here.

In a specific implementation, the data elements may be fixed-point integers with a bit width of 8 bits. Each exponential function value in the first lookup table is a fixed-point integer whose bit width is 8 bits, and the addition result of multiple exponential function values is a fixed-point integer whose bit width is 32 bits, and the first index data and the second index data of the addition result The first mantissa data, the second exponent data and the second mantissa data are fixed-point integers with a bit width of 8 bits, that is, the second lookup table, the third lookup table and the fourth lookup table are all 8 inputs and 8 outputs, and the result of the multiplication operation is For a fixed-point integer with a bit width of 16 bits, the specific function value after the conversion of the multiplication operation result is a fixed-point integer with a bit width of 8 bits; that is, N0, N2, N3, N4, N5, and N7 are 8, N1 is 32, and N6 is 16.

It can be understood that in other implementations, N0, N2, N3, N4, N5, and N7 can be other values; for example, the value range of N0, N2, N3, N4, N5, and N7 can be [1, 32] , in some specific examples, the value range can be [8, 12], for example, N0, N2, N3, N4, N5, N7 can also be unequal, for example, the values of N0, N3 can be 9, 10, 11, 12, N2, N4, N5, N7 are 8. Because the dynamic range of the value of the Softmax function is very wide, most of the related technologies use software modules to realize the function. The embodiment of the present application provides a hardware circuit solution basically based on 8 bits, and can effectively balance important indicators such as circuit cost, power consumption, bandwidth, performance, and data accuracy.

In this embodiment, in the process of obtaining the reciprocal of the addition operation result of the exponential function value of each data element by means of table lookup, the addition operation result is converted to floating point form to obtain the index data of the addition operation result in floating point form and mantissa data, the exponent data and mantissa data of the addition result are respectively searched from multiple lookup tables, and the reciprocal of the addition result is obtained based on the output of multiple lookup tables, and a reciprocal with higher precision can be obtained.

Further, through the calculation process of the softmax function, the result of the addition operation is converted into a floating-point form, and the reciprocal of the result of the addition operation is obtained based on the data of the table lookup multiple times through multiple table lookups, and the input/ The output data bit width is configured in a small range, which can reduce the storage resources occupied by the lookup table and the area of the lookup table circuit, and reduce the occupied bandwidth. On the other hand, it can improve the table lookup speed and fixed-point operation within the allowable range of precision. speed, thereby further speeding up the response speed of the circuit and reducing power consumption.

The present application also provides embodiments of the data processing acceleration method.

Fig. 7 is a schematic flowchart of a data processing acceleration method shown in an embodiment of the present application.

Referring to Figure 7, a data processing acceleration method, including:

In step S110, multiple exponential function values of multiple data elements in the data set are obtained.

In step S120, an addition operation result of a plurality of exponential function values is obtained.

In step S130, the reciprocal of the addition result is obtained.

In step S140, the specific function value of the i-th data element is obtained based on the reciprocal of the exponential function value of the i-th data element and the result of the addition among the plurality of data elements.

Wherein, obtaining the reciprocal of the addition result in step S130 includes:

Step S130A, converting the addition result into at least first data and second data.

Step S130B, at least according to the first data and the second data, obtain the reciprocal of the addition result.

Wherein, the addition result is data with a length of N1 bits, the first data is data with a length of N2 bits, the second data is data with a length of N3 bits, and both N2 and N2 are smaller than N1.

It can be understood that the addition result of the exponential function value may be a result obtained by directly adding the exponential function value, or may be a result obtained by performing an addition operation on the exponential function value after a specific transformation. For the case of transformation, depending on the type of transformation, corresponding inverse transformation may be performed on the subsequently obtained data processing results or no other inverse transformation processing shall be performed. Similarly, the processing of other data should also be broadly understood to include the above two situations, and should not be limited to the processing of the data itself.

Fig. 8 is a schematic flowchart of a data processing acceleration method according to another embodiment of the present application.

Referring to Figure 8, a data processing acceleration method includes:

In step S801, multiple exponential function values corresponding to multiple data elements in the data set are obtained.

In an embodiment, the first lookup table module may respond to the index value of each data element in the data set, output the exponential function value corresponding to each data element based on the first lookup table, and output all the data elements in the data set The respective N4-bit exponential function value.

In step S802, an addition operation result of a plurality of exponential function values is obtained.

In one embodiment, the N4-bit exponential function values of all data elements can be added by an adder to obtain the N1-bit addition results of the exponential function values of all data elements in the data set output by the adder, and the addition operation The result may be an N1-bit fixed-point integer.

In step S803, the addition result is converted from an integer to a floating point number represented by the first exponent data and the first mantissa data.

In one embodiment, the addition operation result output by the adder is an N1-bit integer represented by a fixed point, and the fixed-point integer may be converted to data by an integer-to-floating-point circuit to obtain the N2-bit first exponent data exp0 and First mantissa data frac0 of N3 bits.

In step S804, the first exponent data is converted into a negative number.

In an embodiment, the negative number exp1 corresponding to the first exponent data may be output based on the second lookup table in response to the index value of the first exponent data through the second lookup table circuit.

In step S805, according to the first mantissa data, the decimal part of the floating point number is converted into another floating point number represented by the second exponent data and the second mantissa data.

In one embodiment, the second index data exp2 corresponding to the first mantissa data can be output based on the third look-up table in response to the index value of the first mantissa data through the third look-up table circuit; The circuit, in response to the index value of the first mantissa data, outputs second mantissa data frac1 corresponding to the first mantissa data based on the fourth lookup table.

In step S806, the reciprocal of the addition result is obtained according to the negative number of the first exponent data, the second exponent data, and the second mantissa data.

In one embodiment, the sum of the negative number of the first exponent data and the second exponent data is obtained by an exponent adder, and the sum is used as a shift parameter by a shifter to perform shift processing on the second mantissa data, Get the reciprocal of the N5 bits of the addition result.

In step S807, preset processing is performed on the exponential function value of the ith data element among the multiple data elements and the reciprocal of the addition result, so as to obtain the specific function value of the ith data element.

In one embodiment, the exponential function value of the N4 bits of the i-th data element among the plurality of data elements can be multiplied by the reciprocal of the N5 bits through a multiplication circuit to obtain the multiplication of the N6 bits of the i-th data element Operation results; further, the multiplication result of N6 bits can be converted, for example, converted to a result of N7 bits with a lower bit width, and the converted result can be used as the flexibility of the i-th data element output by the hardware acceleration circuit Maximum function value. It can be understood that converting the result of the multiplication operation from a bit width of N6 bits to N7 bits can be realized, for example, by saturating, rounding, and the like. Rounding processing includes, for example, rounding, rounding up, rounding down, rounding toward zero, and the like.

In one embodiment, the length of the first exponent data and the second exponent data can be both N2 bits, the length of the first mantissa data and the second mantissa data can be both N3 bits; the values of N2 and N3 can be in [1, 32], and in some specific examples, the value range can be [8, 12].

In this embodiment, the exponential function value of each data element is obtained in a table look-up manner through the hardware lookup table circuit, the addition result of the exponential function value is obtained through the adder, and the addition result is converted to floating point, and the addition in floating point form The exponent part and the mantissa part of the operation result are input, the division operation of the addition operation result is realized through the lookup table circuit, and the corresponding reciprocal of the addition operation result is obtained, which avoids complicated exponent operation and reciprocal operation, and can improve the softmax function calculation process. Data processing speed, get Softmax function value faster. On the other hand, excessive hardware circuit area and high cost for realizing exponential operation and reciprocal operation are avoided.

Fig. 9 is a schematic flowchart of a data processing acceleration method according to another embodiment of the present application.

Referring to Figure 9, a data processing acceleration method includes:

In step S901, the maximum value among the plurality of initial data in the initial data set is subtracted to obtain a data set including a plurality of data elements.

In step S902, multiple exponential function values corresponding to multiple data elements in the data set are obtained.

In step S903, the addition operation results of a plurality of exponential function values are obtained.

In step S904, the reciprocal of the addition result is obtained.

In step S905, the specific function value of the i-th data element is obtained based on the reciprocal of the exponential function value of the i-th data element and the result of the addition among the plurality of data elements.

Among them, the result of the addition operation is a floating-point number;

Obtaining the reciprocal of the addition result in step S904 includes:

Convert the addition operation result into exponent data and mantissa data;

Based on at least the exponent data and the mantissa data, the reciprocal of the result of the addition operation is obtained.

Wherein, the length of the addition operation result is N1 bits, the length of the exponent data is N2 bits, and the length of the mantissa data is N3 bits, and both N2 and N3 are smaller than N1.

For relevant features of the data processing acceleration method in the embodiment of the present application, please refer to the relevant content in the foregoing hardware acceleration circuit embodiment, and details are not repeated here.

The data processing acceleration method according to the embodiment of the present application can be applied to an artificial intelligence accelerator. FIG. 10 is a schematic structural diagram of an artificial intelligence accelerator according to an embodiment of the present application.

Referring to FIG. 10 , an artificial intelligence accelerator 1000 includes a memory 1010 and a processor 1020 .

The artificial intelligence accelerator 1020 may be a general processor, such as a CPU (Central Processing Unit, central processing unit), or an artificial intelligence processor (IPU) for performing artificial intelligence calculations. Artificial intelligence computing may include machine learning computing, brain-like computing, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, and the like. The artificial intelligence processor may for example include GPU (Graphics Processing Unit, graphics processing unit), DLA (Deep Learning Accelerator, deep learning accelerator), NPU (Neural-Network Processing Unit, neural network processing unit), DSP (Digital Signal Process, digital Signal processing unit), field programmable gate array (Field-Programmable Gate Array, FPGA), application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or a combination. The present application does not limit the specific type of the processor.

The memory 1010 may include various types of storage units such as system memory, read only memory (ROM), and persistent storage. Wherein, the ROM may store static data or instructions required by the processor 1020 or other modules of the computer. The persistent storage device may be a readable and writable storage device. Persistent storage may be a non-volatile storage device that does not lose stored instructions and data even if the computer is powered off. In some embodiments, the permanent storage device adopts a mass storage device (such as a magnetic or optical disk, flash memory) as the permanent storage device. In some other implementations, the permanent storage device may be a removable storage device (such as a floppy disk, an optical drive). The system memory can be a readable and writable storage device or a volatile readable and writable storage device, such as dynamic random access memory. System memory can store some or all of the instructions and data that the processor needs at runtime. In addition, the memory 1010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and magnetic disks and/or optical disks may also be used. In some embodiments, memory 1010 may include a readable and/or writable removable storage device, such as a compact disc (CD), a read-only digital versatile disc (e.g., DVD-ROM, dual-layer DVD-ROM), Read-only Blu-ray Disc, Super Density Disc, Flash memory card (eg SD card, min SD card, Micro-SD card, etc.), magnetic floppy disk, etc. Computer-readable storage media do not contain carrier waves and transient electronic signals transmitted by wireless or wire.

Executable codes are stored in the memory 1010 , and when the executable codes are processed by the processor 1020 , the processor 1020 may execute part or all of the methods mentioned above.

In a possible implementation manner, the artificial intelligence accelerator may include multiple processors, and each processor may independently run various assigned tasks. The present application does not limit the processor and the tasks run by the processor.

It can be understood that, unless otherwise specified, each functional unit/module in each embodiment of the present application may be integrated into one unit/module, or each unit/module may exist separately physically, or two or more than two Units/modules are integrated together. The above-mentioned integrated units/modules can be implemented in the form of hardware or in the form of software program modules.

If the integrated unit/module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, or the like. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and so on. Unless otherwise specified, the artificial intelligence processor may be any appropriate hardware processor, such as CPU, GPU, FPGA, DSP, ASIC, and the like. Unless otherwise specified, the storage module can be any suitable magnetic storage medium or magneto-optical storage medium, such as, resistive variable memory RRAM (Resistive Random Access Memory), dynamic random access memory DRAM (Dynamic Random Access Memory), static random access memory Access memory SRAM (Static Random-Access Memory), Enhanced Dynamic Random Access Memory EDRAM (Enhanced Dynamic Random Access Memory), high-bandwidth memory HBM (High-Bandwidth Memory), hybrid memory cube HMC (Hybrid Memory Cube), etc.

If the integrated unit/module is realized in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory. Several instructions are included to make a computer device (which may be a personal computer, server or network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

In a possible implementation manner, an artificial intelligence chip is also disclosed, which includes the above-mentioned hardware acceleration circuit.

In a possible implementation manner, a board card is also disclosed, which includes a storage device, an interface device, a control device, and the above-mentioned artificial intelligence chip; wherein, the artificial intelligence chip and the storage device, the control device And the interface devices are respectively connected; the storage device is used to store data; the interface device is used to realize the data transmission between the artificial intelligence chip and the external equipment; the control device is used to control the The state of the artificial intelligence chip is monitored.

In a possible implementation manner, an electronic device including the above-mentioned artificial intelligence chip is disclosed. Electronic equipment includes data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, headphones , mobile storage, wearable devices, vehicles, household appliances, and/or medical equipment. Said vehicles include airplanes, ships and/or vehicles; said household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods; said medical equipment includes nuclear magnetic resonance instruments, Ultrasound and/or electrocardiograph.

In addition, the method according to the present application can also be implemented as a computer program or computer program product, the computer program or computer program product including computer program code instructions for executing some or all of the steps in the above method of the present application.

Alternatively, the present application may also be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium), on which executable code (or computer program or computer instruction code) is stored, When the executable code (or computer program or computer instruction code) is executed by the processor of the electronic device (or server, etc.), the processor is made to perform part or all of the steps of the above-mentioned method according to the present application.

Having described various embodiments of the present application above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims (21)

1. A hardware acceleration circuit, characterized in that, comprising: Exponential function module, is used for obtaining multiple exponential function values of multiple data elements in the data set; an adder, configured to obtain an addition result of the plurality of exponential function values; The first processing circuit is configured to perform preset processing on the addition result, so as to process the addition result into at least first data and second data, wherein the length of the addition result is N1 bits, so The length of the first data is N2 bits, the length of the second data is N3 bits, and both N2 and N3 are smaller than N1; A second processing circuit, configured to perform preset processing on at least the first data and the second data, so as to obtain the reciprocal of the addition result; The third processing circuit is configured to perform preset processing on the exponential function value and the reciprocal of the i-th data element among the plurality of data elements, so as to obtain the specific function value of the i-th data element. 2. The hardware acceleration circuit as claimed in claim 1, characterized in that: The result of the addition operation is an integer; The first processing circuit includes: an integer-to-floating-point conversion circuit, configured to convert the addition operation result from an integer to a floating-point number represented by the first exponent data and the first mantissa data. 3. The hardware acceleration circuit according to claim 2, wherein the second processing circuit comprises: a first conversion circuit for converting the first exponent data into a negative number; a second conversion circuit for converting the fractional part of the floating point number into another floating point number represented by the second exponent data and the second mantissa data according to the first mantissa data; The third conversion circuit is used to obtain the reciprocal of the addition result according to the negative number, the second exponent data and the second mantissa data. 4. The hardware acceleration circuit according to claim 3, wherein the third conversion circuit comprises: an exponent adder, used to obtain the sum of the negative number of the first exponent data and the second exponent data; a shifter, configured to use the sum value as a shift parameter to perform shift processing on the second mantissa data. 5. The hardware acceleration circuit as claimed in claim 3, characterized in that: The exponential function module includes: a first lookup table circuit, configured to obtain multiple exponential function values corresponding to multiple data elements in the data set based on the first lookup table; and/or, The first conversion circuit includes: a second lookup table circuit, configured to obtain a negative number corresponding to the first index data based on the second lookup table; and/or, The second conversion circuit includes: a third lookup table circuit, used to obtain second exponent data corresponding to the first mantissa data based on the third lookup table; a fourth lookup table circuit, used to obtain the second index data corresponding to the first mantissa data based on the fourth lookup table , to obtain second mantissa data corresponding to the first mantissa data. 6. The hardware acceleration circuit as claimed in claim 3, characterized in that: The length of the first exponent data and the second exponent data is N2 bits, and the length of the first mantissa data and the second mantissa data is N3 bits; The values of N2 and N3 are in the range [1, 32]. 7. The hardware acceleration circuit according to claim 5, characterized in that: the hardware acceleration circuit comprises at least two look-up table circuits in the first look-up table circuit to the fourth look-up table circuit, The at least two look-up table circuits each have a basic look-up table circuit unit; or, The at least two look-up table circuits share one basic look-up table circuit unit. 8. The hardware acceleration circuit as claimed in claim 1, characterized in that: The result of the addition operation is a floating point number; The first processing circuit includes: a third lookup table circuit, used to obtain index data corresponding to the addition result based on the third lookup table; a fourth lookup table circuit, used to obtain the index data corresponding to the addition operation result based on the fourth lookup table Mantissa data corresponding to the addition result; The second processing circuit is configured to perform preset processing on the exponent data and the mantissa data, so as to obtain the reciprocal of the addition result; The third processing circuit is configured to perform preset processing on the exponential function value and the reciprocal of the i-th data element among the plurality of data elements, so as to obtain the specific function value of the i-th data element. 9. The hardware acceleration circuit according to claim 1, characterized in that: Also comprising: a subtractor, configured to subtract a plurality of initial data in the initial data set from a maximum value among the plurality of initial data, so as to obtain the data set including the plurality of data elements; The third processing unit includes a multiplier, configured to multiply the exponential function value of the i-th data element among the plurality of data elements and the reciprocal, and output the flexible maximum function of the i-th data element value. 10. An artificial intelligence chip, comprising the hardware acceleration circuit according to any one of claims 1 to 9. 11. A data processing acceleration method, characterized in that being applied to an artificial intelligence accelerator, the method comprises: Obtain multiple exponential function values for multiple data elements in the data set; obtaining an addition operation result of the plurality of exponential function values; obtaining the reciprocal of the result of the addition operation; Obtaining a specific function value of the i-th data element based on the exponential function value and the reciprocal of the i-th data element among the plurality of data elements; Wherein, obtaining the reciprocal of the addition operation result includes: processing the addition operation result into at least first data and second data; Obtaining the reciprocal of the addition result based on at least the first data and the second data; Wherein, the length of the addition operation result is N1 bits, the length of the first data is N2 bits, the length of the second data is N3 bits, and both N2 and N3 are smaller than N1. 12. The method of claim 11, wherein: The result of the addition operation is a floating point number; The processing the addition result at least into first data and second data includes: converting the addition result into exponent data and mantissa data. 13. The method of claim 11, wherein: The result of the addition operation is an integer; Said processing said addition result into at least first data and second data includes: converting said addition result from an integer into a floating point number represented by first exponent data and first mantissa data, and, according to said first mantissa data, converting the fractional part of the floating point number into another floating point number represented by the second exponent data and the second mantissa data; The obtaining the reciprocal corresponding to the addition result at least according to the first data and the second data includes: obtaining the addition result at least according to the first exponent data, the second exponent data and the second mantissa data corresponding reciprocal. 14. The method according to claim 13, wherein at least according to the first exponent data, the second exponent data and the second mantissa data, obtaining the reciprocal corresponding to the addition operation result comprises: obtaining the negative of said first index data; obtaining the sum of the negative number of the first index data and the second index data; The sum value is used as a shift parameter to perform shift processing on the second mantissa data. 15. The method of claim 14, wherein, The obtaining multiple exponential function values of multiple data elements in the data set includes: obtaining multiple exponential function values corresponding to multiple data elements in the data set based on a first lookup table; and/or, The obtaining a negative number of the first index data includes: obtaining a negative number corresponding to the first index data based on a second lookup table. 16. The method according to claim 13, wherein said obtaining second exponent data and second mantissa data according to said first mantissa data comprises: Obtaining second exponent data corresponding to the first mantissa data based on a third lookup table; Based on the fourth lookup table, second mantissa data corresponding to the first mantissa data is obtained. 17. The method of claim 13, wherein: The length of the first exponent data and the second exponent data is N2 bits, and the length of the first mantissa data and the second mantissa data is N3 bits; The values of N2 and N3 are in the range [1, 32]. 18. The method of claim 11, wherein, Before the obtaining multiple exponential function values of multiple data elements in the data set, it also includes: subtracting the multiple initial data in the initial data set from the maximum value among the multiple initial data, so as to obtain the The data collection of a plurality of data elements. 19. The method according to claim 11, wherein the specific value of the i-th data element is obtained based on the exponential function value and the reciprocal of the i-th data element in the plurality of data elements Function values include: Multiplying the exponential function value of the i-th data element among the plurality of data elements with the reciprocal to obtain the flexible maximum function value of the i-th data element. 20. The method according to any one of claims 11 to 19, wherein the method is used to realize the flexible maximum function layer of the neural network, and the neural network is used to classify the data to be processed; wherein, The data to be processed includes at least one of voice data, text data and image data. 21. An artificial intelligence accelerator, comprising: processor; and A memory, on which executable codes are stored, and when the executable codes are executed by the processor, cause the processor to execute the method according to any one of claims 11-20.

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