CN116304812A - Circuits, systems and chips for recognizing emotions based on EEG signals - Google Patents

Abstract

The invention relates to a circuit, a system and a chip for identifying emotion based on an electroencephalogram signal, which comprises a feature extraction unit and a neural network processing unit; the neural network processing unit comprises a first LSTM module, a first data processing module, a second LSTM module, a second data processing module, a classification module and an output module; the characteristic extraction unit performs discrete wavelet transform processing on the original electroencephalogram signals and then outputs characteristic data; the first LSTM module outputs first-stage processing data based on the characteristic data; the first data processing module outputs secondary processing data according to the primary processing data; the second LSTM module processes the secondary processing data and then outputs tertiary processing data; the classification module performs classification processing on the three-level processing data and then outputs classification data; and the output module outputs the classification result after processing the classification data. The invention is characterized by the energy of wavelet coefficient, and cooperates with LSTM network to recognize emotion, which can reduce hardware consumption and improve accuracy.

Description

Circuits, systems and chips for recognizing emotions based on EEG signals

technical field

The present invention relates to the technical field of EEG signal processing, more specifically, to a circuit, system and chip for recognizing emotions based on EEG signals.

Background technique

In order to achieve higher accuracy in the existing emotional recognition neural networks based on EEG signals, some network architectures are relatively simple, but require more complex feature extraction methods; some use simpler features, but their network scale is relatively large. larger. When the networks in the above two cases are deployed on hardware circuits, a relatively large hardware overhead will be introduced and the hardware cost will be increased.

Contents of the invention

The technical problem to be solved by the present invention is to provide a circuit, system and chip for recognizing emotions based on EEG signals.

The technical solution adopted by the present invention to solve the technical problem is: to construct a circuit for recognizing emotions based on EEG signals, including: a feature extraction unit and a neural network processing unit connected to the feature extraction unit;

The neural network processing unit includes: a first LSTM module, a first data processing module, a second LSTM module, a second data processing module, a classification module and an output module connected to the feature extraction unit in sequence;

After the feature extraction unit performs discrete wavelet transform processing on the original EEG signal, output feature data;

After the first LSTM module processes the feature data based on the LSTM algorithm, it outputs the first-level processed data;

After the first data processing module performs batch normalization and integration processing on the primary processing data, it outputs secondary processing data;

After the second LSTM module processes the secondary processing data based on the LSTM algorithm, it outputs tertiary processing data;

After the classification module classifies the three-level processing data, it outputs the classification data;

After the output module processes the classification data, it outputs classification results.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the feature extraction unit is a discrete wavelet feature extraction unit;

After the discrete wavelet feature extraction unit performs discrete wavelet transform on the original EEG signal, obtains a fuzzy component and a detail component, and uses the detail component as the feature data;

The fuzzy component and the detail component are the fuzzy component and the detail component corresponding to the original EEG signal.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the first LSTM module and the second LSTM module include: a Tanh activation function submodule;

The Tanh activation function submodule includes: a sequentially connected shift circuit, a selection circuit and an addition circuit;

The shift circuit accesses the feature data and performs shift processing on the feature data;

The selection circuit outputs corresponding selection data after selecting the data shifted by the shift circuit;

The addition circuit performs addition processing on the selected data.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the selection circuit includes: a first multiplexer, a second multiplexer, a third multiplexer, an inverter, an AND gate and NOR gate;

The first input end of the first multiplexer is connected to the first output end of the shift circuit, the second input end of the first multiplexer is connected to the second output end of the shift circuit connected, the third input terminal of the first multiplexer is connected to the output terminal of the AND gate, and the first input terminal of the AND gate is connected to the second output terminal of the shift circuit through the inverter The second input terminal of the AND gate is connected to the input data, the address line of the first multiplexer is connected to the input data, and the output terminal of the first multiplexer is connected to the addition circuit;

The first input end of the second multiplexer is connected to the third output end of the shift circuit, the second input end of the second multiplexer is connected to the fourth output end of the shift circuit connected, the third input terminal of the second multiplexer is connected to the fifth output terminal of the shift circuit, the fourth input terminal of the second multiplexer is connected to the sixth output terminal of the shift circuit The output terminal is connected, the address line of the second multiplexer is connected to the input data, and the output terminal of the second multiplexer is connected to the adding circuit;

The fourth input terminal of the third multiplexer is connected to the output terminal of the NOR gate, the second input terminal of the NOR gate is connected to the input data, and the first input terminal of the NOR gate is The parameter data is connected, the address line of the third multiplexer is connected to the input data, and the output terminal of the second multiplexer is connected to the adding circuit.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the adding circuit includes: a compressor and an adder;

The first input end of the compressor is connected to the output end of the first multiplexer, the second input end of the compressor is connected to the output end of the second multiplexer, and the first input end of the compressor is connected to the output end of the second multiplexer. The three input ends are connected to the output end of the third multiplexer, and the first output end of the compressor is respectively connected to the first input end of the adder and the output end of the Tanh activation function submodule, and the compressor The second output end of the adder is connected to the second input end of the adder, and the output end of the adder is connected to the output end of the Tanh activation function submodule.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the compressor is a 3/1 compressor.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the first data processing module and the second data processing module include: a square root calculation sub-module;

The square root calculation sub-module adopts a piecewise linear function algorithm combined with Taylor expansion for calculation.

In the circuit for recognizing emotions based on EEG signals according to the present invention, the square root calculation submodule includes: a Taylor calculation unit;

The Taylor calculation unit includes: a leading zero detection module, a compensation module, a first shift module, a second shift module, a third shift module, a subtraction module and an addition module;

The leading zero detection module, the compensation module, the first shift module, the third shift module and the addition operation module are connected in sequence, and the input terminal of the leading zero detection module is connected to the input signal , the first input end of the subtraction module is connected to the input signal, the second input end of the subtraction module is connected to the leading zero detection module, and the output end of the subtraction module is connected to the second The first input terminal of the shift module, the second input terminal of the second shift module is connected to the first shift module, and the output terminal of the second shift module is connected to the addition module.

The present invention also provides a system for recognizing emotions based on EEG signals, including: the above-mentioned circuit for recognizing emotions based on EEG signals.

The present invention also provides a chip, including: the above-mentioned circuit for recognizing emotions based on electroencephalogram signals.

The circuit, system and chip implementing the present invention for recognizing emotions based on EEG signals have the following beneficial effects: comprising: a feature extraction unit and a neural network processing unit; the neural network processing unit includes: a first LSTM module, a first data processing module, The second LSTM module, the second data processing module, the classification module and the output module; the feature extraction unit performs discrete wavelet transform processing on the original EEG signal and then outputs the feature data; the first LSTM module outputs the primary processing data based on the feature data; the first The data processing module outputs the second-level processing data according to the first-level processing data; the second LSTM module outputs the third-level processing data after processing the second-level processing data; the classification module outputs the classification data after classifying the third-level processing data; output After the module processes the classification data, it outputs the classification result. The present invention is characterized by the energy of wavelet coefficients, cooperates with LSTM network to carry out emotion recognition, can not only reduce hardware consumption, but also improve accuracy.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

Fig. 1 is a functional block diagram of a circuit for recognizing emotions based on EEG signals provided by an embodiment of the present invention;

2 is a schematic diagram of a circuit structure for extracting blur component and detail component information provided by an embodiment of the present invention;

3 is a schematic diagram of a circuit structure of a Tanh activation function provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a circuit structure of a 3/1 compressor provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a circuit structure of Taylor calculation provided by an embodiment of the present invention;

Fig. 6 is a schematic diagram of cascading leading zero detection provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The present invention uses the energy of wavelet coefficients as characteristic data, cooperates with LSTM network, and carries out emotion recognition. Compared with the existing method, not only the accuracy rate is significantly improved, but also the operation involved in the overall design is as easy as possible to realize the hardware circuit, making the hardware Consumption is greatly reduced, significantly reducing hardware costs. In addition, the present invention separately optimizes the activation function and square root calculation that are difficult to implement in the neural network, realizes the brain-computer emotion recognition neural network and its hardware implementation.

Specifically, in a preferred embodiment, as shown in FIG. 1 , the circuit for recognizing emotions based on EEG signals includes: a feature extraction unit 10 and a neural network processing unit 20 connected to the feature extraction unit 10 .

In the embodiment of the present invention, the feature extraction unit 10 outputs feature data after discrete wavelet transform processing is performed on the original EEG signal.

Optionally, in the embodiment of the present invention, the feature extraction unit 10 is a discrete wavelet feature extraction unit. Wherein, the discrete wavelet feature extraction unit performs discrete wavelet transform on the original EEG signal to obtain a fuzzy component and a detail component, and uses the detail component as feature data. The fuzzy component and the detail component are the fuzzy component and the detail component corresponding to the original EEG signal.

Specifically, for any function f(t)∈L ² (R), its discrete wavelet transform form is as follows:

In formula (1), ψ(t) is the base wavelet or mother wavelet. a is the scaling factor (also known as the scale factor); b is the translation factor. The scale factor a and translation factor b are discretized, that is:

在一个特定的位置研究一个函数或信号过程，然后再平衡到另一个位置继续研究。如果放大倍数过大，不能不就是尺度太小，就可以按小步长移动一个距离；反之亦然。因此，本发明实施例中，对于小尺度的高频成分，采样步长小；对于大尺度的低频成本，采样步长大。It can be seen from the above that f(t) is decomposed according to different frequency channels. The basic idea of this discretization is to choose an appropriate magnification

Study a function or signal process at a specific location, and then rebalance to another location to continue the study. If the magnification is too large, it must be that the scale is too small, and you can move a distance in small steps; and vice versa. Therefore, in the embodiment of the present invention, for small-scale high-frequency components, the sampling step is small; for large-scale low-frequency components, the sampling step is large.

In the embodiment of the present invention, after discrete wavelet transform is performed on the original EEG signal, corresponding fuzzy components and detail components are obtained, and then the energy of the wavelet coefficients is selected and used as feature data to be input to the neural network processing unit 20 . Specifically, the present invention selects and uses the energy of wavelet coefficients as feature data, on the one hand, it can avoid the use of wavelet reconstruction algorithm, and can significantly reduce the amount of calculation; on the other hand, the energy of wavelet coefficients can give signal strength information, and its The computational complexity is low, and it is easy to be deployed in hardware circuits.

Further, in order to facilitate engineering implementation, in the embodiment of the present invention, the wavelet function Daubechies4(db4) with a limited support set is selected to extract the intensity information of the signal from the fuzzy component and the detail component according to the following formula, namely:

(3) In the formula, D _j,k represents the detail component; (4) In the formula, A _5,k represents the fuzzy component; k is the data label.

Wherein, refer to FIG. 2 for the hardware circuit architecture of the discrete wavelet feature extraction unit in the embodiment of the present invention. Concretely, as shown in Figure 2, the discrete wavelet feature extraction unit of the present invention adopts the mode of cascading, has included two branches in each stage, one branch is the high-pass filtering branch, and the other is the low-pass filtering branch road. Wherein, the high-pass filtering branch includes: a high-pass filter (g in the figure) and a down-sampling circuit (↓2 in the figure). The low-pass filtering branch includes: a low-pass filter (shown as h in the figure) and a downsampling circuit (↓2 in the figure). Among them, D1, D2, D3, and D4 in Fig. 2 are detail components, and A4 is a blur component.

In the embodiment of the present invention, the neural network processing unit 20 includes: a first LSTM module 21, a first data processing module 22, a second LSTM module 23, a second data processing module 24, and a classification module 25 connected to the feature extraction unit 10 in sequence and an output module 26 .

Wherein, the first LSTM module 21 outputs the first-level processed data after processing the feature data based on the LSTM algorithm. The first data processing module 22 outputs the secondary processed data after performing batch normalization and integration processing on the primary processed data. The second LSTM module 23 outputs the third-level processed data after processing the second-level processed data based on the LSTM algorithm. The classification module 25 outputs the classification data after performing classification processing on the three-level processing data. The output module 26 outputs the classification result after processing the classification data.

In the embodiment of the present invention, the first LSTM module 21 and the second LSTM module 23 may adopt the same hardware circuit architecture, but may be different in values and weights, and the actual calculation shall prevail. Similarly, the first data processing module 22 and the second data processing module 24 may also adopt the same hardware circuit architecture, but may be different in values and weights, and the actual calculation shall prevail.

In the embodiment of the present invention, both the first LSTM module 21 and the second LSTM module 23 use LSTM (Longshort-termmemory, LSTM) network algorithm for calculation. Further, in order to reduce power consumption, while making the operation easy to hardware Circuit implementation, the invention improves the Tanh activation function in the LSTM network.

In the embodiment of the present invention, both the first LSTM module 21 and the second LSTM module 23 include: a Tanh activation function sub-module.

Specifically, in the confirmation phase of the PWL (PieceWise-Linesar, piecewise linear function) algorithm model, in addition to considering the mean absolute error (Mean absolute error, MAE) concerned in other such designs, it is also increased from the perspective of hardware design The dimension of multiplication and addition complexity is defined, and the main purpose is to accurately evaluate the calculation process of each binary bit, so as to obtain an algorithm model that meets the requirements.

First, set the range of the function argument to [m,n), where m,n are natural numbers. In a preferred embodiment, the possible values are (-2, 2). Divide into s segments evenly within the range. Then the parameters a _i and b _i of the i-th segment function in PWL can be determined according to the following formula:

Absolute error (AE) and MAE are defined as follows:

Among them, x is the independent variable of the function, f(x) and g(x) are the collimation function value and approximate function value respectively. When using a digital circuit to implement an algorithm, a multiplexer (MUX), that is, a multiplexer, is used to select the segment to which the argument belongs. Considering the characteristics of binary, when segmenting the function curve farther, only the integer power of 2 is selected as the number of segments, so that it is easier to control the bit width of the MUX address line, and as far as possible to ensure that the hardware circuit and software algorithm are divided as far as possible consistency.

In the embodiment of the present invention, the proposed PWL algorithm expression is as follows:

(7) In the formula, x is the input independent variable.

Among them, the input data of the network adopts the signal strength information obtained from the EEG signals of the four electrodes FP1, FP2, F3, and C4 in the 10-20 system electrode rotation method according to formula (2) and formula (3).

Optionally, in the embodiment of the present invention, reference may be made to FIG. 3 for the specific circuit architecture of the Tand activation function sub-module.

Specifically, as shown in Figure 3, wherein, the Tanh activation function submodule includes: a sequentially connected shift circuit 211, a selection circuit 212, and an addition circuit 213; the shift circuit 211 accesses the feature data and performs shift processing on the feature data The selection circuit 212 selects the data shifted by the shift circuit 211, and then outputs the corresponding selection data; the addition circuit 213 performs addition processing on the selection data.

Wherein, the selection circuit 212 includes: a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), an inverter, an AND gate and a NOR gate.

The first input end of the first multiplexer is connected with the first output end of the shift circuit 211, the second input end of the first multiplexer is connected with the second output end of the shift circuit 211, and the first multiplexer The third input terminal of the selector is connected to the output terminal of the AND gate, the first input terminal of the AND gate is connected to the second output terminal of the shift circuit 211 through the inverter, and the second input terminal of the AND gate is connected to the input data, The address line of the first multiplexer is connected to the input data, and the output of the first multiplexer is connected to the addition circuit 213; the first input of the second multiplexer is connected to the third output of the shift circuit 211 , the second input end of the second multiplexer is connected to the fourth output end of the shift circuit 211, the third input end of the second multiplexer is connected to the fifth output end of the shift circuit 211, and the second multiplexer The fourth input end of the way selector is connected with the sixth output end of the shift circuit 211, the address line of the second multi-way selector is connected to the input data, and the output end of the second multi-way selector is connected with the addition circuit 213; The fourth input terminal of the multiplexer is connected to the output terminal of the NOR gate, the second input terminal of the NOR gate is connected to the input data, the first input terminal of the NOR gate is connected to the parameter data, and the third multiplexer's The address line is connected to the input data, and the output terminal of the second multiplexer is connected to the adding circuit 213 .

Optionally, in this embodiment of the present invention, the adding circuit 213 includes: a compressor 2131 and an adder 2132 .

The first input end of the compressor 2131 is connected to the output end of the first multiplexer, the second input end of the compressor 2131 is connected to the output end of the second multiplexer, and the third input end of the compressor 2131 is connected to the third multiplexer. The output terminal of the path selector, the first output terminal of the compressor 2131 is respectively connected to the first input terminal of the adder 2132 and the output terminal of the Tanh activation function submodule, and the second output terminal of the compressor 2131 is connected to the second output terminal of the adder 2132 The input terminal and the output terminal of the adder 2132 are connected to the output terminal of the Tanh activation function sub-module.

In order to improve the performance of the circuit, in the embodiment of the present invention, the compressor 2131 adopts a 3/1 compressor 2131 . As shown in FIG. 4 , (a) is used to perform the sum of the low bits, (b) is used to perform the carry of the highest bit in the low bits, and (c) is used to perform the operation of the high bits. By adopting the 3/1 compressor 2131, only retaining the carry information of the highest bit in the low significant bits of the calculation part, and only using the OR gate to obtain the sum of all bits of the low significant bits, the circuit can be greatly reduced area and propagation time, reducing power consumption and improving efficiency.

Optionally, in the embodiment of the present invention, both the first data processing module 22 and the second data processing module 24 are implemented using a batch normalization algorithm (i.e. Batchnormalization, BN algorithm), and using batch normalization can make each layer of input data The distribution of is relatively stable, which accelerates the learning speed of the model.

Optionally, in this embodiment of the present invention, both the first data processing module 22 and the second data processing module 24 include: a square root calculation sub-module. Wherein, the square root calculation sub-module adopts a piecewise linear function algorithm combined with Taylor expansion for calculation.

That is, when carrying out square root operation design, the present invention has used the mode that PWL algorithm and Taylor's expansion formula are combined, through the introduction of Taylor's formula, can avoid due to when using PWL algorithm, when the independent variable takes a small value, the error exceeds the expected range. Issues that increase hardware resource consumption. That is, the present invention starts from the perspective of the Taylor formula, which can not only improve the accuracy, but also reduce the consumption of hardware resources.

Specifically, in a preferred embodiment, the square root calculation submodule includes: a Taylor calculation unit.

As shown in FIG. 5 , the Taylor calculation unit includes: a leading zero detection module, a compensation module, a first shift module, a second shift module, a third shift module, a subtraction module and an addition module.

The leading zero detection module, the compensation module, the first shift module, the third shift module and the addition module are connected in sequence, and the input terminal of the leading zero detection module is connected to the input signal, and the first input terminal of the subtraction module is connected to the input signal. signal, the second input of the subtraction module is connected to the leading zero detection module, the output of the subtraction module is connected to the first input of the second shift module, and the second input of the second shift module is connected to the first shift module, and the output end of the second shift module is connected to the addition operation module.

Among them, the leading zero detection module is used to detect the most significant 1 in the binary number; the compensation module compensates the data to improve the stability of the data; the first shift module, the second shift module and the third shift module The module shifts the data according to the corresponding shifting requirements, the subtraction module executes subtraction, and the addition module executes addition.

Further, in order to improve the detection speed of leading zero detection, in the embodiment of the present invention, the leading zero detection module adopts a segmented detection method, as shown in FIG. 6 . As shown in Figure 6, LOD represents the leading zero detection module. For a 28-bit binary number, the lower 16 bits form a group and the upper 12 bits form a group. When performing leading zero detection, the lower 16 bits and upper 12 bits are separated. Tested individually.

In the embodiment of the present invention, the output module 26 may use a Sigmoid function. Among them, the classification module 25 performs multi-label classification. Since the multi-label classification is performed, the final activation function is the Sigmoid function. For the final multi-label classification of 8 categories, the accuracy can reach 72%. Obviously, the accuracy can be effectively improved.

The present invention also provides a system for recognizing emotions based on EEG signals, including: the circuit for recognizing emotions based on EEG signals disclosed in the embodiments of the present invention.

The present invention also provides a chip, which includes: the circuit for recognizing emotions based on electroencephalogram signals disclosed in the embodiments of the present invention.

The circuit for recognizing emotions based on EEG signals of the present invention can be applied to data calculations such as FPGA calculations and deep learning calculations. In addition, the circuit for identifying emotions based on EEG signals of the present invention can also be applied to fields related to lyric disorder, virtual reality games, and the like.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for relevant details, please refer to the description of the method part.

Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

The above embodiments are only to illustrate the technical conception and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and cannot limit the protection scope of the present invention. All equivalent changes and modifications made in accordance with the scope of the claims of the present invention shall fall within the scope of the claims of the present invention.

Claims (10)

1. A circuit based on EEG signal recognition emotion, is characterized in that, comprises: feature extraction unit and the neural network processing unit that is connected with described feature extraction unit; The neural network processing unit includes: a first LSTM module, a first data processing module, a second LSTM module, a second data processing module, a classification module and an output module connected to the feature extraction unit in sequence; After the feature extraction unit performs discrete wavelet transform processing on the original EEG signal, output feature data; After the first LSTM module processes the feature data based on the LSTM algorithm, it outputs the first-level processed data; After the first data processing module performs batch normalization and integration processing on the primary processing data, it outputs secondary processing data; After the second LSTM module processes the secondary processing data based on the LSTM algorithm, it outputs tertiary processing data; After the classification module classifies the three-level processing data, it outputs the classification data; After the output module processes the classification data, it outputs classification results. 2. the circuit based on EEG signal recognition emotion according to claim 1, is characterized in that, described feature extraction unit is discrete wavelet feature extraction unit; After the discrete wavelet feature extraction unit performs discrete wavelet transform on the original EEG signal, obtains a fuzzy component and a detail component, and uses the detail component as the feature data; The fuzzy component and the detail component are the fuzzy component and the detail component corresponding to the original EEG signal. 3. the circuit based on EEG signal recognition emotion according to claim 1, is characterized in that, described first LSTM module and the second LSTM module comprise: Tanh activation function submodule; The Tanh activation function submodule includes: a sequentially connected shift circuit, a selection circuit and an addition circuit; The shift circuit accesses the feature data and performs shift processing on the feature data; The selection circuit outputs corresponding selection data after selecting the data shifted by the shift circuit; The addition circuit performs addition processing on the selected data. 4. The circuit for recognizing emotions based on EEG signals according to claim 3, wherein the selection circuit comprises: a first multiplexer, a second multiplexer, a third multiplexer, an inverse Phase devices, AND gates, and NOR gates; The first input end of the first multiplexer is connected to the first output end of the shift circuit, the second input end of the first multiplexer is connected to the second output end of the shift circuit connected, the third input terminal of the first multiplexer is connected to the output terminal of the AND gate, and the first input terminal of the AND gate is connected to the second output terminal of the shift circuit through the inverter The second input terminal of the AND gate is connected to the input data, the address line of the first multiplexer is connected to the input data, and the output terminal of the first multiplexer is connected to the addition circuit; The first input end of the second multiplexer is connected to the third output end of the shift circuit, the second input end of the second multiplexer is connected to the fourth output end of the shift circuit connected, the third input terminal of the second multiplexer is connected to the fifth output terminal of the shift circuit, the fourth input terminal of the second multiplexer is connected to the sixth output terminal of the shift circuit The output terminal is connected, the address line of the second multiplexer is connected to the input data, and the output terminal of the second multiplexer is connected to the adding circuit; The fourth input terminal of the third multiplexer is connected to the output terminal of the NOR gate, the second input terminal of the NOR gate is connected to the input data, and the first input terminal of the NOR gate is The parameter data is connected, the address line of the third multiplexer is connected to the input data, and the output terminal of the second multiplexer is connected to the adding circuit. 5. the circuit based on EEG signal recognition emotion according to claim 4, is characterized in that, described addition circuit comprises: compressor and adder; The first input end of the compressor is connected to the output end of the first multiplexer, the second input end of the compressor is connected to the output end of the second multiplexer, and the first input end of the compressor is connected to the output end of the second multiplexer. The three input ends are connected to the output end of the third multiplexer, and the first output end of the compressor is respectively connected to the first input end of the adder and the output end of the Tanh activation function submodule, and the compressor The second output end of the adder is connected to the second input end of the adder, and the output end of the adder is connected to the output end of the Tanh activation function submodule. 6. The circuit for recognizing emotions based on EEG signals according to claim 5, wherein the compressor is a 3/1 compressor. 7. The circuit for recognizing emotions based on EEG signals according to claim 1, wherein the first data processing module and the second data processing module include: a square root calculation submodule; The square root calculation sub-module adopts a piecewise linear function algorithm combined with Taylor expansion for calculation. 8. The circuit for recognizing emotions based on EEG signals according to claim 7, wherein the square root calculation submodule comprises: a Taylor calculation unit; The Taylor calculation unit includes: a leading zero detection module, a compensation module, a first shift module, a second shift module, a third shift module, a subtraction module and an addition module; The leading zero detection module, the compensation module, the first shift module, the third shift module and the addition operation module are connected in sequence, and the input terminal of the leading zero detection module is connected to the input signal , the first input end of the subtraction module is connected to the input signal, the second input end of the subtraction module is connected to the leading zero detection module, and the output end of the subtraction module is connected to the second The first input terminal of the shift module, the second input terminal of the second shift module is connected to the first shift module, and the output terminal of the second shift module is connected to the addition module. 9. A system for recognizing emotions based on EEG signals, characterized by comprising: the circuit for recognizing emotions based on EEG signals according to any one of claims 1-8. 10. A chip, characterized by comprising: the circuit for recognizing emotions based on EEG signals according to any one of claims 1-8.

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