CN116264076A

CN116264076A - Identify the system and its static random access memory cells

Info

Publication number: CN116264076A
Application number: CN202111530980.2A
Authority: CN
Inventors: 何伟立; 张顺志
Original assignee: Himax Technologies Ltd; NCKU Research and Development Foundation
Current assignee: Himax Technologies Ltd; NCKU Research and Development Foundation
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2023-06-16
Anticipated expiration: 2041-12-14
Also published as: CN116264076B

Abstract

The invention relates to an identification system and a static random access memory unit thereof. The SRAM cell includes a first inverter and a second inverter cross-coupled; a first access transistor controlled by the word line to access the output of the first inverter; a second access transistor controlled by the word line to access the output of the second inverter; a first pass transistor controlled by the output of the first inverter for passing the common mode voltage; a second pass transistor controlled by the output of the second inverter for passing the input signal; and a capacitor, which is coupled to the common mode voltage and the input signal by the first pass transistor and the second pass transistor respectively. The invention has the advantages of low power consumption and/or bandwidth improvement.

Description

Identification system and static random access memory unit thereof

Technical Field

The present invention relates to identification technology, and more particularly, to an identification system using a neural network.

Background

Voice activity detection (voice activity detection, VAD) may be used to detect or recognize human voice. Voice activity detection may trigger voice-based applications such as Apple computer (Apple) corporation's virtual assistant Siri (Speech Interpretation and Recognition Interface, voice parsing and recognition interface). Voice activity detection is a front-end device, which is typically an always-on (always-on) and low power system.

Modern computer architecture was proposed by John von Neumann (John von Neumann) in 1945, but a bus (bus) shared between program memory and data memory creates a von Neumann bottleneck. Since a single bus can only access one of the program memory or the data memory at a single time, the processing power is much lower than the operating rate of the CPU. When a CPU is required to process a large amount of data, the effective processing rate of the CPU is severely limited. The cpu is continually forced to wait until the desired data is moved to or from memory.

in-Memory-based operations (CIM) are a technique for integrating operations with Memory. Embedding the operations into the memory reduces the data movement, makes the energy use more efficient, and saves bandwidth for a large number of parallel operations. In-memory computing (in-memory computing), which is a distributed computing approach that stores computing and data close to the data source, is useful for machine learning of the internet of things (Internet of Things, ioT).

Therefore, there is a need to propose a novel mechanism to improve the performance of low power or/and high bandwidth systems (e.g., speech recognition systems).

Disclosure of Invention

In view of the foregoing, it is an objective of the embodiments of the present invention to provide an identification system including static random access memory (Static Random Access Memory, SRAM) cells (cells) that uses the charge redistribution (charge redistribution) principle to generate an accumulated signal, and has low power consumption and/or increased bandwidth.

The invention is a static random access memory cell comprising: the first inverter is connected between the ground and the power supply; a second inverter connected between the ground and the power source, the first inverter being cross-coupled with the second inverter; a first access transistor controlled by the word line to access the output of the first inverter, which is transferred through the first bit line; a second access transistor controlled by the word line to access the output of the second inverter, which is transferred via a second bit line; a first pass transistor controlled by the output of the first inverter for passing the common mode voltage; a second pass transistor controlled by the output of the second inverter for passing the input signal; and a capacitor, which is coupled to the common mode voltage and the input signal by the first pass transistor and the second pass transistor respectively.

Preferably, the method further comprises: and a switch for switching the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, the switch being controlled by a sampling clock signal.

Preferably, the switch is turned on in the sampling stage, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common mode voltage; the switch is turned off in the quantization stage, the lower plate of the capacitor is switchably coupled to the reference voltage by a reverse switch, the reverse switch is controlled by a reverse sampling clock signal having a reverse polarity with respect to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

Preferably, the method further comprises: a first switching transistor connected in series with the first pass transistor; and a second switching transistor connected in series with the second path transistor; wherein the first pass transistor indirectly receives the common-mode voltage by the first switching transistor, and the first switching transistor is controlled by a sampling clock signal; the second path transistor indirectly receives the input signal through the second switching transistor, and the second switching transistor is controlled by the sampling clock signal.

Preferably, the first switching transistor and the second switching transistor are conducted in a sampling stage, so that a lower plate of the capacitor is sampled to obtain a sampling voltage, and an upper plate of the capacitor is coupled to the common mode voltage; the first switching transistor and the second switching transistor are disconnected in the quantization stage, the lower plate of the capacitor is switched and coupled to the reference voltage by a reverse switch, the reverse switch is controlled by a reverse sampling clock signal, the reverse switch has opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

Preferably, the first inverter comprises a first transistor and a second transistor connected in series between the ground and the power supply, wherein the second transistor is opposite to the first transistor; the second inverter comprises a third transistor and a fourth transistor connected in series between the ground and the power supply, wherein the fourth transistor is opposite to the third transistor.

According to an embodiment of the invention, the identification system comprises a plurality of SRAM cells and a quantizer. The SRAM cells are arranged in rows, each row of SRAM cells receives a respective input signal and generates a respective output signal, which is connected to generate sub-signals, and all rows of sub-signals are connected to generate an accumulated signal. A quantizer receives the accumulated signal to generate a digital output, the quantizer comprising at least one capacitor array shared with the SRAM cell.

Preferably, the quantizer comprises a continuous asymptotic analog-to-digital converter.

Preferably, the successive approximation analog-to-digital converter comprises: a first digital-to-analog converter comprising an array of capacitors; a second digital-to-analog converter comprising an array of capacitors; a comparator receiving the output of the first digital-to-analog converter, the output of the second digital-to-analog converter, and the accumulated signal; and a sequential asymptotic logic for receiving the comparison result of the comparator and generating the digital output.

Preferably, a neural network is included, comprising: an input layer whose node receives the input signal; a first layer whose nodes receive the output of the input layer; and an output layer, the node of which receives the output of the first layer, thereby identifying the input signal; wherein the plurality of sram cells form nodes of the input layer.

Preferably, each node of the first layer comprises: a digital-to-analog converter comprising a capacitor array comprising a plurality of capacitors; wherein upper plates of the plurality of capacitors are connected together as an output of the digital-to-analog converter; the lower plate switches of the plurality of capacitors receive either the digital output or the inverted digital output of the input layer.

Preferably, each of the plurality of sram cells comprises: the first inverter is connected between the ground and the power supply; a second inverter connected between the ground and the power source, the first inverter being cross-coupled with the second inverter; a first access transistor controlled by the word line to access the output of the first inverter, which is transferred through the first bit line; a second access transistor controlled by the word line to access the output of the second inverter, which is transferred via a second bit line; a first pass transistor controlled by the output of the first inverter for passing the common mode voltage; a second pass transistor controlled by the output of the second inverter for passing the input signal; and a capacitor, which is coupled to the common mode voltage and the input signal by the first pass transistor and the second pass transistor respectively; wherein the capacitors of the plurality of sram cells of different rows have weighted binary values, respectively.

Preferably, the sram cell further comprises: and a switch for switching the capacitor to be connected to the outputs of the first pass transistor and the second pass transistor, the switch being controlled by a sampling clock signal.

Preferably, the SRAM cell further comprises a first switching transistor connected in series with the first pass transistor; and a second switching transistor connected in series with the second path transistor; wherein the first pass transistor indirectly receives the common-mode voltage by the first switching transistor, and the first switching transistor is controlled by a sampling clock signal; the second path transistor indirectly receives the input signal through the second switching transistor, and the second switching transistor is controlled by the sampling clock signal.

By means of the technical scheme, the invention has at least the following advantages: the invention can improve the efficiency of the low-power or/and high-bandwidth system.

Drawings

FIG. 1A shows a schematic diagram of a (artificial) neural network suitable for use in an identification system according to an embodiment of the present invention.

FIG. 1B shows a block diagram of an identification system according to an embodiment of the invention.

FIG. 2A is a circuit diagram of a SRAM cell (FIG. 1B) according to an embodiment of the present invention.

FIG. 2B is a circuit diagram of a SRAM cell (FIG. 1B) according to another embodiment of the present invention.

FIG. 3A shows a circuit diagram of a successive approximation analog-to-digital converter (SAR ADC) as a quantizer in an identification system according to an embodiment of the present invention.

FIG. 3B shows a circuit diagram of a successive approximation analog-to-digital converter (SAR ADC) as a quantizer in an identification system according to another embodiment of the present invention.

Fig. 4A shows an equivalent circuit of a cyclic asymptotic analog-to-digital converter (SAR ADC) during a first sampling phase.

Fig. 4B shows an equivalent circuit of a cyclic asymptotic analog-to-digital converter (SAR ADC) during a second sampling phase.

Fig. 4C and 4D show equivalent circuits of successive asymptotic analog-to-digital converters (SAR ADCs) in the first quantization stage and the second quantization stage, respectively, when Vip (of the first digital-to-analog converter (DAC)) is greater than Vin (of the second digital-to-analog converter (DAC)).

Fig. 4E and 4F show equivalent circuits of successive asymptotic analog-to-digital converters (SAR ADCs) in the first quantization stage and the second quantization stage, respectively, when Vip (of the first digital-to-analog converter (DAC)) is smaller than Vin (of the second digital-to-analog converter (DAC)).

Fig. 5A shows a circuit diagram of a digital-to-analog converter (DAC), which represents a node of the first layer of fig. 1A.

Fig. 5B and 5C show equivalent circuit diagrams of the digital-to-analog converter in the reset phase and the output phase, respectively.

Fig. 5D illustrates timing diagrams of the related signals of fig. 5B and 5C.

[ Main element symbols description ]

100: identification system

11: static random access memory unit

200A: continuous asymptotic analog-to-digital converter

200B: continuous asymptotic analog-to-digital converter

21: first digital-to-analog converter

211: first virtual capacitor

22: second digital-to-analog converter

221: second virtual capacitor

23: comparator with a comparator circuit

24: sequential asymptotic logic

Vin: input signal

Vin1 to Vin6: input signal

CLKs: sampling clock signal

CLKsb: inverse sampling clock signal

Vcm: common mode voltage

Vmac: accumulating signals

SRAM: static random access memory

M1: first transistor

M2: second transistor

M3: third transistor

M4: fourth transistor

M5: fifth transistor/first access transistor

M6: sixth transistor/second access transistor

M7: seventh transistor/first pass transistor

M8: eighth transistor/second pass transistor

M9: ninth transistor/first switching transistor

M10: tenth transistor/second switching transistor

Q: output of

Qb: output of

BL: first bit line

BLb: second bit line

WL: word line

SW1: switch

SW2: reversing switch

C: capacitor with a capacitor body

Vref: reference voltage

Vrefp: positive reference voltage

Vrefn: negative reference voltage

Dout: digital output

DACout: output of

bit0 to bit3: digital output

bit0b to bit3b: inverse digital output

SW: switch

SWb: switch

Reset: reset signal

Reset_b: reverse reset signal

Detailed Description

FIG. 1A shows a schematic diagram of a (artificial) neural network suitable for use in an identification system according to an embodiment of the present invention. The neural network may include connected nodes (or neurons) with weights between the connected nodes, which may be obtained by training a dataset (dataset). The recognition system may be adapted for speech recognition to recognize whether the input signal is speech or noise. As illustrated in FIG. 1A, the nodes of the input layer receive input signals (e.g., vin 1-Vin 6) representing the extracted features of different channels, respectively, and the nodes of the output layer can identify whether the input signals are voice or noise. The nodes of one or more hidden layers (e.g., the first layer shown) receive the output of the previous layer and generate an output to send to the next layer.

FIG. 1B shows a block diagram of an identification system 100 according to an embodiment of the invention. The recognition system 100 illustrated in FIG. 1B may be suitable for the input layer of FIG. 1A. According to one of the features of the present embodiment, the identification system 100 uses in-memory operation (CIM) technology, which integrates operation and memory, thereby reducing power consumption and saving bandwidth.

The identification system 100 of the present embodiment may include a plurality of Static Random Access Memory (SRAM) cells 11 arranged in a row. For each row, the sram cell 11 receives respective input signals (e.g., vin 1-Vin 6) and generates respective (weighted) output signals, which are connected (added) to generate sub-signals. Next, the sub-signals of all the rows are connected to generate an accumulated signal Vmac, which represents an output signal obtained by multiplying the input signal (the plurality of sram cells 11).

Fig. 2A shows a circuit diagram of the sram cell 11 (fig. 1B) according to an embodiment of the present invention. In this embodiment, the sram cell 11 may include eight transistors (e.g., metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) and one capacitor (i.e., 8T 1C). The sram cell 11 of the present embodiment may include a first inverter including a first transistor M1 (e.g., an nmos fet) and a second transistor M2 (e.g., a pmos fet) connected in series between ground and a power supply, wherein the second transistor M2 is opposite to the first transistor M1. The sram cell 11 further comprises a second inverter comprising a third transistor M3 (e.g., an nmos fet) and a fourth transistor M4 (e.g., a pmos fet) connected in series between ground and a power supply, wherein the fourth transistor M4 is of a type opposite to the third transistor M3. The first inverter (M1, M2) is cross-coupled (cross-coupled) with the second inverter (M3, M4). That is, the output Q of the first inverter (M1, M2) is coupled to the input of the second inverter (M3, M4), and the (inverted) output Qb of the second inverter (M3, M4) is coupled to the input of the first inverter (M1, M2).

The sram cell 11 may comprise a first access transistor comprising a fifth transistor M5 (e.g. an nmos fet) controlled by a word line WL to access the output Q of the first inverter (M1, M2) for transfer via a first bit line BL. The sram cell 11 further comprises a second access transistor comprising a sixth transistor M6 (e.g. an nmos field effect transistor) controlled by the word line WL to access the (inverted) output Qb of the second inverter (M3, M4) for transfer via the second bit line BLb.

According to one feature of this embodiment, the sram cell 11 may comprise a first pass transistor comprising a seventh transistor M7 (e.g., an nmos fet), whose gate is controlled by the output Q of the first inverter (M1, M2) for passing a common-mode voltage Vcm (via the drain). The sram cell 11 further comprises a second pass transistor comprising an eighth transistor M8 (e.g. an nmos field effect transistor), the gate of which is controlled by the output Qb of the second inverter (M3, M4) for passing the input signal Vin (via the drain). The seventh transistor M7 is connected to the output (at the source) of the eighth transistor M8.

According to another feature of the present embodiment, the sram cell 11 may include a capacitor C, and the common mode voltage Vcm and the input signal Vin are coupled through a seventh transistor M7 and an eighth transistor M8, respectively. In this embodiment, the capacitor C is switched to receive the output of the first/second pass transistor M7/M8 by a switch SW1, the switch SW1 being controlled by the sampling clock signal CLKs. Notably, the values (or weights) of the capacitors C of different rows (of the identification system 100) are different from one another. The capacitors C of the SRAM cells 11 of different rows have weighted binary-weighted values (e.g., C, 2C, 4C, and 8C), respectively.

Fig. 2B shows a circuit diagram of the sram cell 11 (fig. 1B) according to another embodiment of the present invention. In this embodiment, the sram cell 11 may include ten transistors and one capacitor (i.e., 10T 1C). The sram cell 11 of fig. 2B is similar to that of fig. 2A, except as described below. As shown in fig. 2B, the sram cell 11 further includes a first switching transistor including a ninth transistor M9 (e.g., an nmos transistor) connected in series with the first pass transistor M7; and a second switching transistor including a tenth transistor M10 (e.g., an N-type metal oxide semiconductor field effect transistor) connected in series with the second path transistor M8. Thus, the first pass transistor M7 indirectly receives the common mode voltage Vcm through the first switching transistor M9 (the gate thereof is controlled by the sampling clock signal CLKs); and the second pass transistor M8 indirectly receives the input signal Vin through the second switching transistor M10 (the gate thereof is controlled by the sampling clock signal CLKs). However, the capacitor C is directly connected to the output of the first/second pass transistor M7/M8 without via the switch SW 1. Therefore, the first switching transistor M9 and the second switching transistor M10 are used as a switch together, so that the capacitor C can switch the receiving common-mode voltage Vcm and the input signal Vin through the first pass transistor M7 and the second pass transistor M8 respectively.

In operation, the switch SW1 (or the first/second switching transistor M9/M10) is turned on during the sampling phase such that the lower plate of the capacitor C (from the output of the first/second pass transistor M7/M8) samples the analog voltage and the upper plate of the capacitor C is coupled to the common mode voltage Vcm. The switch SW1 (or the first/second switching transistor M9/M10) is turned off during the quantization (quantization) stage, the lower plate of the capacitor C is switched and coupled to the reference voltage Vref (e.g., the positive reference voltage Vrefp or the negative reference voltage Vrefn) by the reverse switch SW2, the reverse switch SW2 is controlled by the reverse sampling clock signal CLKsb (which has the opposite polarity with respect to the sampling clock signal CLKs), and the upper plate of the capacitor C is obtained with the previous sampling voltage.

Fig. 3A shows a circuit diagram of a sequential asymptotic analog-to-digital converter (successive approximation register analog-to-digital converter, SAR ADC) 200A according to an embodiment of the present invention, as a quantizer in the identification system 100. The successive approximation analog-to-digital converter 200A converts the continuous analog wave into separate digital values, which perform binary search (binary search) at all quantization levels, and finally converges to a digital output Dout at each conversion. The successive approximation analog-to-digital converter 200A is used as a quantizer, and is operable in conjunction with the SRAM cell 11 of FIG. 1B. The successive approximation analog-to-digital converter 200A may include a first digital-to-analog converter (DAC) 21 including an array of capacitors; and a second digital-to-analog converter (DAC) 22 comprising an array of capacitors. The capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 are switchably coupled to the input signals (e.g., vin 1-Vin 6) and the common mode voltage Vcm. The successive approximation analog-to-digital converter 200A may include a comparator 23 that receives the output of the first digital-to-analog converter (DAC) 21 (at the non-inverting input node) and the output of the second digital-to-analog converter (DAC) 22 (at the inverting input node). In addition, the comparator 23 also receives the accumulation signal Vmac. The successive approximation analog-to-digital converter 200A may include successive approximation logic 24 that receives the comparison result from the comparator 23 and generates the digital output Dout. According to one of the features of the present embodiment, the capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 can be shared with the sram cell 11 of fig. 1B.

Fig. 3B shows a circuit diagram of a successive approximation analog-to-digital converter (SAR ADC) 200B according to another embodiment of the present invention, as a quantizer in the identification system 100. The sequential asymptotic analog-to-digital converter (SAR ADC) 200B of fig. 3B is similar to the sequential asymptotic analog-to-digital converter (SAR ADC) 200A of fig. 3A, except for the following differences. In the present embodiment, the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 further include a first dummy or replica capacitor 211 and a second dummy or replica capacitor 221, respectively, which are switchably connected to the input signals (e.g., vin1 to Vin 6) and the common mode voltage Vcm.

Fig. 4A shows an equivalent circuit of the successive approximation analog-to-digital converter (SAR ADC) 200B in a first sampling stage, and fig. 4B shows an equivalent circuit of the successive approximation analog-to-digital converter (SAR ADC) 200B in a second sampling stage. Fig. 4C and 4D show equivalent circuits of the successive approximation analog-to-digital converter (SAR ADC) 200B during the first quantization stage and the second quantization stage, respectively, when Vip (of the first digital-to-analog converter (DAC) 21) is greater than Vin (of the second digital-to-analog converter (DAC) 22). Fig. 4E and 4F show equivalent circuits of the successive approximation analog-to-digital converter (SAR ADC) 200B during the first quantization stage and the second quantization stage, respectively, when Vip (of the first digital-to-analog converter (DAC) 21) is smaller than Vin (of the second digital-to-analog converter (DAC) 22).

According to the above embodiment, the sram cell 11 employs the charge redistribution (charge redistribution) principle to generate the accumulated signal Vmac, instead of using the charge sharing (charge sharing) principle of the conventional system. Therefore, the timing of the above embodiments of the present invention is simplified compared to the conventional system, and a reset phase is not required. Furthermore, the capacitor array of the successive approximation analog-to-digital converter 200A/B may be in a sampling phase to generate the accumulated signal Vmac. Furthermore, virtual capacitors are used in the successive approximation analog-to-digital converter 200B of fig. 3B, so that the signal swing can approach the full range.

Fig. 5A shows a circuit diagram of a digital-to-analog converter (DAC) 500, which represents a node of the first layer of fig. 1A. Fig. 5B and 5C show equivalent circuit diagrams of the digital-to-analog converter 500 in the reset phase and the output phase, respectively, and fig. 5D illustrates timing diagrams of related signals of fig. 5B and 5C. In this embodiment, the digital-to-analog converter (DAC) 500 may include a capacitor array including a plurality of capacitors (e.g., C, 2C, 4C, and 8C). The upper plates of the capacitors are connected together as the output DACout of the digital-to-analog converter (DAC) 500. The lower plate of the capacitor switches to receive the digital output of the previous layer or the inverted digital output. Wherein bit 0-bit 3 represent the digital outputs produced by the sequential asymptotic logic 24 of the previous layer (e.g., the input layer of FIG. 1A), and bit0 b-bit 3b represent the inverse digital outputs with polarities opposite to those of the digital outputs bit 0-bit 3, respectively. For example, the digital outputs bit0 and bit0b are electrically coupled to the corresponding capacitors via switches SW and SWb, respectively (wherein the operation of switch SW is opposite to switch SWb), and the switch SW/SWb is controlled by the weights trained in advance and stored in advance. The output DACout of the digital-to-analog converter (DAC) 500 is then sent to a comparator (e.g., a node at the output layer) to identify speech or noise.

The present invention is not limited to the above-mentioned embodiments, but is not limited to the above-mentioned embodiments, and any simple modification, equivalent changes and modification made to the above-mentioned embodiments according to the technical matters of the present invention can be made by those skilled in the art without departing from the scope of the present invention.

Claims

1. A static random access memory unit, characterized in that, comprising:

a first inverter connected between the ground and the power supply;

a second inverter connected between the ground and the power supply, the first inverter and the second inverter are cross-coupled;

The first access transistor is controlled by the word line to access the output of the first inverter, which is transmitted through the first bit line;

a second access transistor controlled by the word line to access the output of the second inverter, which is transmitted through the second bit line;

The first pass transistor is controlled by the output of the first inverter to allow the common-mode voltage to pass;

a second pass transistor controlled by the output of the second inverter to allow the input signal to pass; and

The capacitor is switchably coupled to the common-mode voltage and the input signal via the first pass transistor and the second pass transistor respectively.

2. The SRAM unit according to claim 1, further comprising:

A switch is used to switch the output of the capacitor connected to the first pass transistor and the second pass transistor, and the switch is controlled by a sampling clock signal.

3. The static random access memory unit according to claim 2, wherein the switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to to the common-mode voltage; the switch is disconnected during the quantization stage, and the lower plate of the capacitor is coupled to the reference voltage by switching the reverse switch, which is controlled by the reverse sampling clock signal, which is relatively The sampled clock signal has opposite polarity, and the upper plate of the capacitor receives the sampled voltage.

4. The SRAM unit according to claim 1, further comprising:

a first switching transistor connected in series with the first pass transistor; and

a second switching transistor connected in series with the second pass transistor;

Wherein the first pass transistor indirectly receives the common mode voltage through the first switch transistor, the first switch transistor is controlled by the sampling clock signal; and the second pass transistor is controlled by the second pass transistor The switching transistor is used to indirectly receive the input signal, and the second switching transistor is controlled by the sampling clock signal.

5. The static random access memory unit according to claim 4, wherein the first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is obtained by sampling sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are disconnected during the quantization phase, and the lower plate of the capacitor switches the coupling Connected to a reference voltage, the inverse switch is controlled by an inverse sampling clock signal having an opposite polarity with respect to the sampling clock signal, and the upper plate of the capacitor receives the sampling voltage.

6. The static random access memory unit according to claim 1, wherein the first inverter comprises a first transistor and a second transistor connected in series between the ground and the power supply, wherein the first inverter The type of the second transistor is opposite to that of the first transistor; the second inverter includes a third transistor and a fourth transistor, which are connected in series between the ground and the power supply, wherein the fourth transistor has a type opposite to the third transistor.

7. An identification system, characterized in that it comprises:

A plurality of static random access memory units are arranged in rows, and the static random access memory units of each row respectively receive corresponding input signals and generate corresponding output signals, which are connected to generate sub-signals, and the sub-signals of all rows are connected to generate cumulative signal; and

a quantizer receiving the accumulated signal to generate a digital output, the quantizer comprising at least one capacitor array;

Wherein the at least one capacitor array is shared with the plurality of SRAM units.

8. The identification system of claim 7, wherein the quantizer comprises a progressive analog-to-digital converter.

9. The identification system according to claim 8, wherein the progressive analog-to-digital converter comprises:

a first digital-to-analog converter comprising an array of capacitors;

a second digital-to-analog converter comprising an array of capacitors;

a comparator that receives the output of the first digital-to-analog converter, the output of the second digital-to-analog converter, and the accumulated signal; and

The continuous asymptotic logic receives the comparison result of the comparator and generates the digital output accordingly.

10. The recognition system of claim 7, comprising a neural network comprising:

an input layer, the nodes of which receive the input signal;

a first layer, the nodes of which receive the output of the input layer; and

an output layer, the nodes of which receive the output of the first layer to identify the input signal;

Wherein the plurality of static random access memory units constitute nodes of the input layer.

11. The identification system according to claim 10, wherein each node of the first layer comprises:

a digital-to-analog converter comprising a capacitor array comprising a plurality of capacitors;

The upper plates of the plurality of capacitors are connected together as the output of the digital-to-analog converter; the lower plates of the plurality of capacitors switch to receive the digital output or the reverse digital output of the input layer.

12. The identification system according to claim 7, wherein each of the plurality of static random access memory units comprises:

a first inverter connected between the ground and the power supply;

a capacitor for switching coupling the common-mode voltage and the input signal via the first pass transistor and the second pass transistor respectively;

The capacitors of the plurality of SRAM cells in different rows have weighted binary values respectively.

13. The identification system according to claim 12, wherein the static random access memory unit further comprises:

14. The identification system according to claim 13, wherein the switch is turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampled voltage, and the upper plate of the capacitor is coupled to the common mode voltage; the switch is disconnected during the quantization stage, and the lower plate of the capacitor is coupled to the reference voltage by switching the reverse switch, which is controlled by the reverse sampling clock signal, which is relative to the sampling clock The signal is of opposite polarity and the upper plate of the capacitor gets the sampled voltage.

15. The identification system according to claim 12, wherein the static random access memory unit further comprises:

16. The identification system according to claim 15, wherein the first switching transistor and the second switching transistor are turned on during the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and The upper plate of the capacitor is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are disconnected during the quantization phase, and the lower plate of the capacitor is switched and coupled to the reference voltage by a reverse switch , the inverse switch is controlled by an inverse sampling clock signal having an opposite polarity relative to the sampling clock signal, and the upper plate of the capacitor receives the sampling voltage.