CN116243558B

CN116243558B - Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof

Info

Publication number: CN116243558B
Application number: CN202310245841.8A
Authority: CN
Inventors: 刘伟; 刘伟文; 曹衍灿; 邬新根; 刘英策
Original assignee: Xiamen Changelight Co Ltd
Current assignee: Xiamen Changelight Co Ltd
Priority date: 2023-03-15
Filing date: 2023-03-15
Publication date: 2025-11-21
Anticipated expiration: 2043-03-15
Also published as: CN116243558A

Abstract

This invention provides a photolithography method, an LED chip, and a fabrication method for thick photoresist. In thick photoresist applications, weak exposure reduces the influence of Poisson's spot at pattern intersections, avoiding pattern distortion. Furthermore, the _SiO2 /metal hard mask process can be eliminated in subsequent etching processes, significantly reducing production costs. Low-temperature curing and development cycles improve the uniformity of the thick photoresist and the uniformity of the linewidth after development. Further, using an aluminum disk as a carrier for ICP etching to form the preset pattern on the structure to be etched is achieved. Using aluminum as a carrier, which is low-cost, highly malleable, and has higher thermal conductivity, effectively solves the problems of poor thermal conductivity and low etching rate of traditional silicon carbide carriers, thereby greatly increasing production capacity and effectively reducing manufacturing costs.

Description

Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof.

Background

With the continuous development of semiconductor light emitting technology, the application of LEDs is more and more varied, and particularly, the development of LEDs in display technology is advanced. Meanwhile, due to the high resolution requirement of the LED display screen, the distance between LED chips and the size of the chips are also smaller and smaller, such as Mi n i-LEDs and other micro-light emitting devices.

The LED is a semiconductor device for converting electric energy into light energy, and is widely used in the fields of lighting, display, backlight, etc. because of its advantages of small size, long lifetime, rich colors, low energy consumption, etc. Mi n i-LED is used as a sub-millimeter light-emitting diode, the size of the Mi n i-LED is generally 80-200 um, the Mi n i-LED is a new generation of l ed technology, the Mi n i-LED is used for adapting the characteristics of high efficiency, high reliability, high brightness and quick response time of a small-pitch LED, the power consumption and the cost of the small-pitch LED are lower, however, as the size of a chip is reduced, the channel occupation ratio is higher and higher, the light-emitting area of the chip is directly influenced, and therefore, an etching channel with high depth-to-width ratio is urgently needed to be prepared.

In the existing manufacturing field, it is generally required to apply a thick photoresist as an etching mask layer for full exposure, and to use SiO2 or metal as a hard mask layer to avoid the influence on the epitaxial layer caused by the uncleanness of the thick photoresist development.

It should be noted that in the prior art, in order to meet the needs of a special process in different semiconductor processes, a thick photoresist (i.e., a thick photoresist) is usually required to be coated for exposure in some photolithography steps, for example, in a process of a 0.13um process node, the thickness of the photoresist to be coated is sometimes 6um or more, while the thickness of a general photoresist is 2um or less, and we define the photoresist with a thickness greater than or equal to three times the general thickness value as a "thick photoresist".

When the development rate at the exposure amount approaches the maximum value, the exposure amount is referred to as full/overexposure, and conversely, weak exposure.

However, as shown in fig. 1 and 2, the above method still has the following disadvantages:

1. by using the thick photoresist as a mask layer, the exposure energy required by the thick photoresist is extremely high, and the strong diffraction brought by the exposure energy can cause the intersection of the channels to form serious poisson light spots, and the etched poisson light spot areas are still abnormal in etching.

2. The thick photoresist is affected by the depth of the adhesive layer, and the exposure degree of the upper surface and the lower surface of the thick photoresist has obvious difference, so that after the photoresist is developed and hardened later, the sidewall of a photoresist reflow channel is very inclined, so that the width of the channel is too wide, and the light-emitting area is seriously affected.

3. SiO ₂ or metal is adopted as a mask protective layer, so that the cost is high, and the process is complex.

In view of this, the present inventors have specifically devised a photolithography method based on thick photoresist application, an LED chip and a method for manufacturing the same, which results therefrom.

Disclosure of Invention

The invention aims to provide a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof, so as to improve the etching morphology of a high aspect ratio channel.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

The photoetching method based on thick photoresist application comprises the steps of providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer, and etching the structure to be etched to form a preset pattern with an intersection, wherein the etching process comprises the following steps:

s01, forming a positive photoresist layer on the surface of the structure to be etched;

S02, forming an exposure area on the positive photoresist layer through weak exposure;

s03, curing the positive photoresist layer;

S04, developing the positive photoresist layer to remove the photoresist corresponding to the exposure area;

s05, repeatedly executing the steps S03 to S04 to form a positive photoresist layer with uniform preset patterns;

S06, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern by etching the structure to be etched.

Preferably, the step S06 includes performing ICP etching with a positive photoresist layer having a uniform preset pattern as a mask and an aluminum disk as a carrier disk to form the preset pattern on the structure to be etched.

Preferably, said step S03 is performed by lowering the ambient temperature to effect said curing of said positive photoresist layer.

Preferably, the multi-step etching is achieved by adjusting at least one of ICP source power, bias source power, and gas flow.

Preferably, the positive photoresist layer is scanned by a plasma prior to the multi-step etch.

Preferably, the total number of times of executing the steps S03 to S04 is n, wherein n is a positive integer, n is not less than 2, and when the nth execution of the step S03 is performed at the corresponding ambient temperature of T _n, T _n≥T_n-1 is performed.

Preferably, T _n-T_n-1. Gtoreq.5℃.

Preferably, the step S04 is performed at room temperature.

Preferably, the positive photoresist layer has a coefficient of thermal expansion of no more than 50 x 10 ^-6/°c.

Preferably, the positive photoresist layer comprises a plurality of photoresist sublayers, and the thermal expansion coefficient of the photoresist sublayers on the top surface is not higher than 50 x 10 ^-6/°c.

Preferably, the preset pattern comprises a channel with an intersection and an aspect ratio greater than 1.

Preferably, the thickness of the positive photoresist layer is 6-50 um, including the endpoint value.

Preferably, the positive photoresist layer comprises EPG-562 photoresist.

The invention also provides a manufacturing method of the LED chip, which adopts the etching method of any one of the above to form a plurality of LED light-emitting units which are mutually isolated through channels, and the LED light-emitting units are of a horizontal structure, and the manufacturing method comprises the following steps:

A01, providing a substrate;

A02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;

a03, exposing part of the first semiconductor layer by etching the epitaxial lamination, so as to form a plurality of grooves and table tops, wherein the grooves are opposite to the table tops;

A04, deep etching the epitaxial lamination until the surface of the substrate is exposed by adopting the photoetching method of any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;

A05, manufacturing a first electrode and a second electrode, wherein the first electrode is deposited on the groove and is far away from the side wall of the groove, the second electrode is deposited on the table top, and the first electrode and the second electrode are far away from each other.

Preferably, the included angle between the channel and the epitaxial lamination is 55-90 degrees, including the end point value.

The invention also provides an LED chip comprising the LED chip with the horizontal structure, wherein the LED chip is obtained by the manufacturing method of any one of the above.

The invention also provides another manufacturing method of the LED chip, which adopts the etching method of any one of the above to form a plurality of LED light-emitting units mutually isolated through channels, wherein the LED light-emitting units are of vertical structures, and the manufacturing method comprises the following steps:

b01, providing a substrate;

b02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;

b03, deeply etching the epitaxial lamination until the surface of the substrate is exposed by adopting the photoetching method of any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;

B04, providing a conductive substrate, and bonding the surface of the epitaxial lamination layer with the conductive substrate through a bonding layer to form a whole;

b05, stripping the substrate to expose the first semiconductor layer;

and B06, manufacturing a first electrode on the exposed surface of the first semiconductor layer.

Preferably, the LED chip is obtained by the manufacturing method of any one of the above.

According to the technical scheme, the photoetching method applied to the substrate Yu Houguang resistor is used for etching a structure to be etched to form a preset pattern with an intersection, firstly, a positive photoresist layer is formed on the surface of the structure to be etched, secondly, after the positive photoresist layer is formed into an exposure area under the weak exposure effect, the positive photoresist layer is cured again, then the positive photoresist layer is developed to remove the photoresist corresponding to the exposure area, then, the curing and the developing are repeatedly carried out to form the positive photoresist layer with the uniform preset pattern, and finally, the positive photoresist layer with the uniform preset pattern is used as a mask, and the structure to be etched is etched to form the preset pattern with the intersection. Therefore, when the thick photoresist is applied, the Poisson light spot influence of the pattern intersection is weakened through weak exposure, the S iO ₂/metal hard mask process can be canceled in the subsequent etching process while the pattern distortion is avoided, the production cost is greatly reduced, and the uniformity of the thick photoresist and the uniformity of the line width after development are improved through the cyclic operation of low-temperature curing and development.

Furthermore, the aluminum disc is used as a bearing disc for ICP etching, so that the structure to be etched forms the preset pattern, and the bearing disc made of aluminum is low in use cost, strong in plasticity and higher in heat conduction performance, so that the problems of poor heat conduction performance and low etching rate of the traditional silicon carbide bearing disc can be well solved, the productivity is greatly improved, and the manufacturing cost is effectively reduced.

Then, by adjusting at least one of the ICP source power, the bias source power, and the gas flow rate to achieve multi-step etching, ICP etch depth uniformity and post-etch line width uniformity can be ensured.

Further, before the multi-step etching, the positive photoresist layer is scanned by plasma, so that the photoresist pattern is ensured to have no residual film and the evenness of the photoresist is improved.

Finally, the total times of executing the steps S03 to S04 is n, wherein n is a positive integer, n is more than or equal to 2, when the n-th execution of the step S03 is performed for the first time, the corresponding environment temperature is T _n, T _n≥T_n-1, and the side wall morphology of the photoresist can be well improved while the etching resistance of the photoresist is improved through the adjustment of multiple curing temperatures.

The invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels are formed through the photoetching method, regular and flat channels are formed, the risks that the channels overlap edges with the electrode grooves and the performance of the LED chip is influenced are avoided, meanwhile, the problem of large inclination of the channels of the LED chip can be effectively solved through the photoetching method, the channels with steep sides are obtained, the size of the channels can be effectively reduced, the effective area and the light-emitting area of the LED chip can be furthest obtained, the LED chip is particularly suitable for miniature LED chips (such as Mini/Micro-LEDs and the like), the productivity of the LED chip can be greatly improved, and the manufacturing cost can be effectively reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a topography of an LED chip after forming a cross channel by deep etching in the prior art;

FIG. 2 is a diagram of an FIB test after forming a cross channel by deep etching of an LED chip according to the prior art;

FIG. 3 is a flow chart of a photolithography method according to embodiment 1 of the present invention;

FIG. 4 is a graph showing the development rate of the EPG-562 photoresist (10 um thick) provided in example 1 of the present invention at different exposure levels;

fig. 5.1 to 5.7 are schematic structural diagrams corresponding to the method for manufacturing an LED chip according to embodiment 2 of the present invention;

fig. 6.1 to 6.7 are schematic structural diagrams corresponding to the method for manufacturing an LED chip according to embodiment 3 of the present invention;

Fig. 7 is a topography of the LED chip provided in embodiment 2 after deep etching to form a trench;

FIG. 8 is a FIB test chart of the LED chip of embodiment 2 after deep etching to form a trench;

The symbols in the drawings illustrate:

L1L 2. Ln: a sub-epitaxial stack;

1. The semiconductor device comprises a substrate, 2, a first type semiconductor layer, 3, an active layer, 4, a second type semiconductor layer, 5.1, a groove, 5.2, a mesa, 6, a channel, 7, a transparent conductive layer, 8, an insulating layer, 9, a second electrode, 10, a first electrode, 11 and a conductive substrate.

Detailed Description

In order to make the contents of the present invention more clear, the contents of the present invention will be further described with reference to the accompanying drawings. The present invention is not limited to this specific embodiment. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

As shown in FIG. 3, the lithography method based on thick photoresist application comprises providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer, and etching the structure to be etched to form a preset pattern with an intersection, wherein the etching process comprises the following steps:

Based on the above embodiments, in one embodiment of the present application, the positive photoresist layer includes EPG-562 photoresist.

Based on the above embodiments, in one embodiment of the present application, the thickness of the positive photoresist layer is 6 to 50um, including the endpoint value.

Based on the above embodiments, in one embodiment of the present application, the thermal expansion coefficient of the positive photoresist layer is not higher than 50×10 ^-6/°c.

Based on the above embodiments, in one embodiment of the present application, the positive photoresist layer includes a plurality of photoresist sub-layers, and the thermal expansion coefficient of the photoresist sub-layers on the top surface is not higher than 50×10 ^-6/°c.

As shown in the schematic diagram of the development rate change of the EPG-562 photoresist (with a thickness of 10 um) under different exposure amounts in fig. 4, in one embodiment of the present application, the exposure energy corresponding to the portion with a larger gradient (i.e., within the dashed line frame) in the graph is selected based on the above embodiment.

Further, when the EPG-562 photoresist is used, the exposure energy can be selected from the exposure energy corresponding to the thickness of the photoresist of 14-17 mj/cm ² for weak exposure, and the total exposure energy can be accumulated according to the total thickness of the photoresist, and the invention is not limited to the method.

S03, curing the positive photoresist layer to improve the flatness of the thick photoresist;

On the basis of the above embodiments, in one embodiment of the present application, the step S03 is performed by reducing the ambient temperature to effect the curing of the positive photoresist layer.

Based on the above embodiments, in one embodiment of the present application, the ambient temperature T1 corresponding to the first curing is preferably 20 to 100 ℃ and the curing time is 5 to 100s.

on the basis of the above-described embodiments, in one embodiment of the present application, the first development is performed by the developer at room temperature to perform the step S04.

The developer includes TMAH developer, TBAH developer, and the like, and the present application is not limited thereto.

Based on the above embodiments, in one embodiment of the present application, the total number of times of executing the steps S03 to S04 is n, where n is a positive integer, n is greater than or equal to 2, and when the n-th execution of the step S03 is performed at the corresponding ambient temperature of T _n, then T _n≥T_n-1.

Based on the above embodiments, in one embodiment of the present application, T _n-T_n-1. Gtoreq.5℃.

Based on the above embodiments, in one embodiment of the present application, the environmental temperature T2 corresponding to the second curing is preferably 50 to 120 ℃ and the curing time is 10 to 100s. And after the second solidification, cooled to room temperature to perform the second development. The developer used for the second development may be the same as or different from the developer corresponding to the first development, and the present application is not limited thereto.

The number of times n of the present embodiment is not limited to a specific range, and similarly, the third time of curing and the fourth time of curing are performed at a temperature of at least 5 ℃ in accordance with T _n-T_n-1.

Based on the above embodiment, in one embodiment of the present application, the step S06 includes performing ICP etching with a positive photoresist layer having a uniform preset pattern as a mask and an aluminum disk as a carrier disk to form the preset pattern on the structure to be etched.

Based on the above embodiments, in one embodiment of the present application, the multi-step etching is implemented by adjusting at least one of the ICP source power, the bias source power, and the gas flow rate during the ICP etching.

On the basis of the above embodiments, in one embodiment of the present application, the positive photoresist layer is scanned by plasma prior to the multi-step etching.

Note that the number of etching steps is not limited in this embodiment. In one embodiment of the present application, the multi-step etching is achieved by adjusting the upper electrode power, the lower electrode power, and the gas flow during the ICP etching, and specifically, the etching step includes 2 steps of etching:

The first etching step is performed by plasma scanning the positive photoresist layer in an O ₂/Ar atmosphere, and then by an upper electrode with a power of 800-630W and an upper electrode with a power of 100-700W and a gas flow of 100-250 sccm.

And secondly, performing a second deep etching step by using Cl ₂/BCl₃ gas, wherein the power of the upper electrode is 800-630W, the power of the upper electrode is 300-800W, and the gas flow is not less than 200sccm.

On the basis of the above embodiment, in one embodiment of the present application, the preset pattern includes the channel 6 having the intersection and the aspect ratio greater than 1.

Finally, the steps S03 to S04 are repeatedly executed for n times, wherein n is a positive integer and is more than or equal to 2, when the environment temperature corresponding to the nth execution of the step S03 is T _n, T _n＞T_n-1 is carried out, and the side wall morphology of the photoresist can be well improved while the etching resistance of the photoresist is improved through the adjustment of multiple curing temperatures.

Example 2

The embodiment of the invention also provides a manufacturing method of the LED chip, which adopts the etching method described in the embodiment 1 to form a plurality of LED light-emitting units mutually isolated through the channels 6, wherein the LED light-emitting units are of a horizontal structure, and the manufacturing method comprises the following steps:

a01, as shown in FIG. 5.1, a substrate 1 is provided;

a02, as shown in FIG. 5.2, growing an epitaxial stack comprising a first type semiconductor layer 2, an active layer 3 and a second type semiconductor layer 4 stacked in sequence on the surface of the substrate 1;

A03, as shown in fig. 5.3, etching the epitaxial lamination to expose part of the first semiconductor layer 2, thereby forming a plurality of grooves 5.1 and a table top 5.2, wherein the grooves 5.1 are opposite to the table top 5.2;

A04, as shown in fig. 5.4, deep etching the epitaxial lamination to expose the surface of the substrate 1 by adopting the photoetching method described in any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through the channels 6;

For ease of illustration, fig. 5.4 illustrates only 2 sub-epitaxial stacks (L1, L2), which may be included in the actual fabrication of the product, as the case may be, and the application is not limited thereto.

A05, as shown in fig. 5.7, a first electrode 10 and a second electrode 9 are manufactured, wherein the first electrode 10 is deposited on the groove 5.1 and is far away from the side wall of the groove 5.1, the second electrode 9 is deposited on the table top 5.2, and the first electrode 10 and the second electrode 9 are far away from each other.

Before the first electrode 10 and the second electrode 9 are fabricated, as shown in fig. 5.5, the transparent conductive layer 7 may be fabricated on the mesa 5.2 to serve as a current spreading, and then, as shown in fig. 5.6, the insulating layer 8 may be fabricated on the sidewall of the epitaxial stack to serve as an insulating protection and/or a mirror between the electrode and the sidewall, which is not limited in this embodiment.

Based on the above embodiments, in one embodiment of the present application, the included angle between the channel 6 and the epitaxial layer stack is 55 ° to 90 °, including the end point value.

The embodiment of the invention also provides an LED chip which comprises the LED chip with the horizontal structure, and the LED chip is obtained by the manufacturing method of any one of the above.

The embodiment of the invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels 6 are formed through the photoetching method described in the embodiment 1, as shown in fig. 7 and 8, regular and flat channels 6 are formed, the risks that the channels overlap with the electrode grooves 5.1 and the performance of the LED chip is influenced are avoided, meanwhile, the problem of large inclination of the channels 6 of the LED chip can be effectively solved through the photoetching method, and the channels 6 with steep sides are obtained, so that the size of the channels 6 can be effectively reduced, the effective area and the light-emitting area of the LED chip can be maximally obtained, and the LED chip is particularly suitable for miniature LED chips (such as Mini/Micro-LEDs and the like), the productivity of the LED chip can be greatly improved, and the manufacturing cost can be effectively reduced.

Example 3

The embodiment of the invention also provides another manufacturing method of an LED chip, which adopts the etching method described in the embodiment 1 to form a plurality of LED light-emitting units mutually isolated through the channel 6, wherein the LED light-emitting units are of a vertical structure, and the manufacturing method comprises the following steps:

b01, as shown in FIG. 6.1, a substrate 1 is provided;

B02, as shown in fig. 6.2, growing an epitaxial stack comprising a first type semiconductor layer 2, an active layer 3 and a second type semiconductor layer 4 stacked in order on the surface of the substrate 1;

B03, as shown in fig. 6.3, deep etching the epitaxial stack layer to expose the surface of the substrate 1 by adopting the photolithography method described in any one of the above, so as to form a plurality of sub epitaxial stack layers which are mutually arranged at intervals through the channels 6;

For ease of illustration, fig. 6.3 illustrates only 3 sub-epitaxial stacks (L1, L2, L3), which may be included in the thousands of sub-epitaxial stacks during actual fabrication of the product, as the case may be, and the application is not limited thereto.

B04, as shown in fig. 6.4 and 6.5, providing a conductive substrate 11, and bonding the conductive substrate 11 to form a whole on the surface of the epitaxial lamination through a bonding layer;

b05, as shown in fig. 6.6, peeling off the substrate 1 to expose the first semiconductor layer 2;

as shown in fig. 6.7, a first electrode 10 is formed on the exposed surface of the first type semiconductor layer 2.

In this embodiment, the conductive substrate 11 may be used as the second electrode 9 of the LED chip to be in contact with the outside.

On the basis of the above embodiments, in one embodiment of the present application, the LED chip is obtained by the manufacturing method described in any one of the above.

The embodiment of the invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels 6 are formed through the photoetching method described in the embodiment 1, regular and flat channels 6 are formed, the risks that the channels and electrodes overlap and the performance of the LED chip are influenced are avoided, meanwhile, the problem that the inclination of the channels 6 of the LED chip is large can be effectively solved through the photoetching method, the channels 6 with steep sides are obtained, the size of the channels 6 can be effectively reduced, the effective area and the light-emitting area of the LED chip are maximally obtained, the LED chip is particularly suitable for miniature LED chips (such as Mi n i/M icro-LEDs and the like), the productivity of the LED chip can be greatly improved, and the manufacturing cost can be effectively reduced.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of additional like elements in an article or apparatus that comprises such an element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The photoetching method based on thick photoresist application is characterized by comprising the steps of providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer, and etching the structure to be etched to form a preset pattern with an intersection, and the etching process comprises the following steps:

s03, curing the positive photoresist layer;

s06, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern by etching the structure to be etched;

Taking a positive photoresist layer with a uniform preset pattern as a mask, and performing ICP etching by taking an aluminum disc as a bearing disc to enable the structure to be etched to form the preset pattern;

said step S03 is performed by lowering the ambient temperature to effect said curing of said positive photoresist layer.

2. The method of claim 1, wherein the multi-step etching is performed by adjusting at least one of upper electrode power, lower electrode power, and gas flow during the ICP etching.

3. The method according to claim 1, wherein the steps S03 to S04 are repeated for n, wherein n is a positive integer and n is not less than 2, and the ambient temperature corresponding to the nth step S03 is T _n, T _n＞T_n-1.

4. A lithographic method for use with a substrate Yu Houguang according to claim 3, wherein T _n- T_n-1 is ≡5 ℃.

5. The method of claim 1, wherein said step S04 is performed at room temperature.

6. A method of lithographically applying the substrate Yu Houguang resist of claim 1 wherein the positive photoresist layer has a coefficient of thermal expansion of no greater than 50 x 10 ^-6/°c.

7. A method of lithographically applying the substrate Yu Houguang resist of claim 1 wherein the positive photoresist layer comprises a plurality of photoresist sublayers and the top surface photoresist sublayers have a coefficient of thermal expansion no greater than 50 x 10 ^-6/°c.

8. The method of claim 1, wherein the predetermined pattern comprises a trench having an intersection and an aspect ratio greater than 1.

9. The method of claim 1, wherein the positive photoresist layer has a thickness of 6-50 um, inclusive.

10. A lithographic method for a substrate Yu Houguang resist application according to claim 1, wherein said positive photoresist layer comprises EPG-562 photoresist.

11. A method for manufacturing an LED chip, characterized in that a plurality of LED light emitting units isolated from each other by a channel are formed by using the photolithography method applied by the resistor Yu Houguang according to any one of claims 1 to 10, and the LED light emitting units are of a horizontal structure, the method comprising the steps of:

A01, providing a substrate;

A04, deep etching the epitaxial lamination to expose the surface of the substrate by adopting the photoetching method of any one of claims 1 to 10 to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;

12. The method of claim 11, wherein the channel and the epitaxial layer stack have an included angle of 55 ° to 90 °, inclusive.

13. An LED chip comprising a horizontal structure LED chip, characterized in that the LED chip is obtained by the manufacturing method according to any one of claims 11 to 12.

14. A method for manufacturing an LED chip, wherein a plurality of LED light emitting units isolated from each other by a channel are formed by using the photolithography method applied by the resistor Yu Houguang according to any one of claims 1 to 10, and the LED light emitting units are of a vertical structure, the method comprising the steps of:

b01, providing a substrate;

B03, deep etching the epitaxial lamination to expose the surface of the substrate by adopting the photoetching method of any one of claims 1 to 10 to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;

b05, stripping the substrate to expose the first semiconductor layer;

15. The method of claim 14, wherein the channel and the epitaxial layer stack have an included angle of 55 ° to 90 °, inclusive.

16. An LED chip comprising a vertical structure LED chip, characterized in that the LED chip is obtained by the manufacturing method according to any one of claims 14 to 15.