CN116166178A - Basic storage unit management circuit and basic storage unit management method - Google Patents

Abstract

A basic storage unit management circuit and a basic storage unit management method. The basic storage unit management circuit includes a receiving circuit, a transmission circuit, a first buffer and an idle basic storage unit controller. The first buffer is used to store a bit table, wherein the bit table includes a plurality of first bits, which respectively correspond to a plurality of basic storage units, and each first bit in the plurality of first bits is used for Indicating whether a corresponding basic storage unit is an idle basic storage unit. The idle basic storage unit controller is coupled to the receiving circuit, the transmitting circuit and the first buffer, and is used to manage the bit table stored in the first buffer, and process the corresponding receiving circuit or transmitting circuit according to the bit table At least one basic storage unit of at least one packet transmitted.

Description

Basic storage unit management circuit and basic storage unit management method

technical field

The invention relates to data management, in particular to a basic storage unit management circuit and a basic storage unit management method for idle basic storage units.

Background technique

In a traditional switch, router or media access control (MAC), a memory, such as a static random access memory (SRAM), is usually divided into multiple A basic storage unit, and a multi-bit (multi-bit) free basic storage unit link list (link list) can be used to manage idle basic storage units in a plurality of basic storage units, however, some problems may occur. Since the address of a free basic storage unit in the multi-bit free basic storage unit linked list is stored in the previous free basic storage unit, there is one part of the multi-bit free basic storage unit linked list. The size of memory (such as SRAM) may increase due to the number of basic storage units, which may increase cost and read time. In addition, the throughput of get/release (get/release) idle basic storage units ) may be limited by the bandwidth of the memory, therefore, a novel architecture is highly desired to replace the linked list of idle basic storage units.

Contents of the invention

Therefore, one object of the present invention is to provide a basic storage unit management circuit and a related basic storage unit management method to solve the above problems.

At least one embodiment of the present invention provides a basic storage unit management circuit, wherein the basic storage unit management circuit may include a receiving circuit, a transmission circuit, a first buffer and an idle basic storage unit controller. The first buffer can be used to store a bit table, wherein the bit table includes a plurality of first bits, which respectively correspond to a plurality of basic storage units, and each first bit in the plurality of first bits is used for To indicate whether a corresponding basic storage unit is an idle basic storage unit. The idle basic storage unit controller can be coupled to the receiving circuit, the transmitting circuit and the first buffer, and can be used to manage the bit table stored in the first buffer, and process the received or transmitted data received by the corresponding receiving circuit according to the bit table. At least one basic storage unit of at least one packet transmitted by the circuit, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller assigns a first basic storage unit corresponding to the basic storage unit One bit is set to a first logical value; and when the basic storage unit of the plurality of basic storage units is not an idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit to a second logical value.

At least one embodiment of the present invention provides a basic storage unit management method. The basic storage unit management method may include: storing a bit table, wherein the bit table includes a plurality of first bits, which respectively correspond to a plurality of basic storage units, and each of the plurality of first bits One bit is used to indicate whether a corresponding basic storage unit is an idle basic storage unit; and using an idle basic storage unit controller to process at least one corresponding to a receiving circuit received or a transmitting circuit transmitted according to the bit table Packet at least one basic storage unit, and manage the bit table, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first corresponding to the basic storage unit One bit is set to a first logical value, and when the basic storage unit of the plurality of basic storage units is not an idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit to a second logical value.

One of the benefits of the present invention is that the basic storage unit management circuit provided by the present invention can utilize the memory buffer and the temporary register buffer storing the bit table to manage idle basic storage units, and the idle basic storage unit of the basic storage unit management circuit The storage unit controller first finds out a target second bit with a first logic value (for example, 1) from a plurality of second bits of the register buffer to obtain a read address, and according to the read bit address to read a target effective free storage unit flag field in the bit table of the memory buffer, and find out at least one target No. One bit is used to obtain at least one idle basic storage unit. In this way, the time for reading the memory buffer can be greatly reduced. In addition, in order to reduce the power consumption of the memory buffer and save the bandwidth of the memory buffer, the present invention also A basic storage unit management circuit is provided, which includes a free basic storage unit buffer, wherein the free basic storage unit buffer can be used to reduce the access times of the memory buffer.

Description of drawings

FIG. 1 is a schematic diagram of the corresponding relationship between bits in a memory buffer and bits in a register buffer according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a basic storage unit management circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a basic storage unit management circuit according to another embodiment of the invention.

FIG. 4 is a flow chart of a basic storage unit management method according to an embodiment of the invention.

Symbol Description

100,200,300: SRAM buffers

101,201,301: bit table

110,210,310: scratchpad buffer

a~d: valid idle storage unit flag field

e～h: the second digit

20,30: Basic storage unit management circuit

220,320: idle basic storage unit controller

230,330: receiving circuit

240,340: transmission circuit

350: Free basic storage unit buffer

B10,B21,B22,B27: the first digit

S400, S402: steps

Detailed ways

FIG. 1 is a schematic diagram of the corresponding relationship between bits in a memory buffer and bits in a register buffer according to an embodiment of the invention. As shown in FIG. 1, a memory buffer (such as a static random access memory buffer 100; labeled "SRAM buffer" in FIG. 1 for brevity) may be used to store a bit table 101, wherein the bit table 101 can include 32 first bits (which correspond to 32 basic storage units respectively), and each first bit in the 32 first bits can be used to indicate whether a corresponding basic storage unit is a Idle basic storage unit, for example, when a basic storage unit in 32 basic storage units is an idle basic storage unit, then a first bit corresponding to the basic storage unit is a first logic value (such as 1 ); and when a basic storage unit among the 32 basic storage units is not an idle basic storage unit, then a first bit corresponding to the basic storage unit is a second logic value (for example, 0). In addition, in order to save the time of reading the memory buffer and to find out the free basic storage unit more quickly, the bit table can be divided into a plurality of effective free storage unit identification fields (field) in units of bits For example, the MxN (for example MxN=32) first bits in the bit table 101 can be divided into N (for example N=4) effective idle storage units of M (for example M=8) bits A unit identification field (for example, an effective idle storage unit identification field a to an effective idle storage unit identification field d).

The register buffer 110 can be used to store 4 second bits (for example, the second bit e ~ the second bit h, which respectively correspond to the effective idle storage unit flag field a ~ effectively idle in the bit table 101 Storage unit identification field d), wherein each of the 4 second bits can be used to indicate whether a corresponding valid idle storage unit identification field contains a first logic value (for example, 1) At least one first bit (that is, indicating whether at least one idle basic storage unit is included in the 8 basic storage units corresponding to the 8 first bits in the corresponding effective idle storage unit identification field). When an effective idle storage unit identification field in the four effective idle storage unit identification fields includes at least one first bit with a first logical value (such as 1), then the corresponding effective idle storage unit identification field The second bit of is the first logical value (for example, 1); and when all the first bits contained in one of the four valid free memory unit flag fields have the second logical value (such as 0) (that is, there is no idle basic storage unit in the 8 basic storage units corresponding to the 8 first bits in the effective idle storage unit indication field), then the effective idle storage unit indication field The corresponding second bit is a second logical value (eg, 0). For example, since the valid free storage unit flag field a in the bit table 101 includes 4 first bits with a first logical value (for example, 1), the valid free memory unit flag field a corresponds to The second bit e is a first logical value (eg, 1). For another example, since all the first bits contained in the effective free storage unit flag field c in the bit table 101 have the second logic value (for example, 0), the first bit corresponding to the effective spare memory unit flag field c The bit g is a second logic value (eg, 0).

FIG. 2 is a schematic diagram of a basic storage unit management circuit 20 according to an embodiment of the invention. As shown in FIG. 2, the basic storage unit management circuit 20 may include a memory buffer (such as a static random access memory buffer 200; for brevity, labeled as "SRAM buffer" in FIG. 2), a register buffer device 210, an idle basic storage unit controller 220, a receiving circuit 230, and a transmitting circuit 240, wherein the SRAM buffer 200 and the temporary register buffer 210 can be respectively composed of the SRAM buffer shown in FIG. 1 100 and scratchpad buffer 110 to achieve. The SRAM buffer 200 can be used to store a bit table 201. In this embodiment, the bit table 201 can include 32 first bits (which respectively correspond to 32 basic storage units), and bit The 32 first bits in table 201 can be divided into 4 effective idle storage unit identification fields (such as effective idle storage unit identification field a ~ effective idle storage unit identification field d) in units of 8 bits, However, this is only an example rather than a limitation of the present invention. In practice, the size of the bit table 201 and the field division of the effective free storage unit flag can be adjusted according to requirements. The temporary register buffer 210 can be used to store 4 second bits (for example, the second bit e ~ the second bit h, which respectively correspond to the effective idle storage unit flag field a ~ effectively idle in the bit table 201 storage unit designation field d), however, this is only used as an example, rather than a limitation of the present invention, in practice, the number of second bits stored in the register buffer 210 will depend on the bit table 201 is the number of effective free storage unit indication fields. For the sake of brevity, the similar content of the SRAM buffer 200 and the register buffer 210 in this embodiment will not be repeated here.

The idle basic storage unit controller 220 can be coupled to the SRAM buffer 200, the receiving circuit 230 and the transmitting circuit 240, and can be used to manage the bit table 201 stored in the SRAM buffer 200, and according to The bit table 201 is used to process at least one basic storage unit corresponding to at least one packet received by the receiving circuit 230 or transmitted by the transmission circuit 240, wherein the 32 basic storage units corresponding to the 32 first bits of the bit table 201 When a basic storage unit in is an idle basic storage unit, the idle basic storage unit controller 220 can set the first bit corresponding to the basic storage unit as a first logic value (such as 1); and when the bit table 201 When a basic storage unit among the 32 basic storage units corresponding to the 32 first bits is not an idle basic storage unit, the idle basic storage unit controller 220 can set the corresponding first bit of the basic storage unit to Second logical value (eg 0). In addition, the free basic storage unit controller 220 can also be coupled to the register buffer 210, wherein when one of the four valid free storage unit identification fields of the bit table 201 includes the When there is at least one first bit of a logical value (such as 1), the idle basic storage unit controller 220 can set the second bit corresponding to the effectively idle storage unit flag field to the first logical value (such as 1). ; and when all the first bits included in one of the 4 valid idle storage unit identification fields of the bit table 201 have a second logical value (such as 0), the basic storage is idle The cell controller 220 may set the second bit corresponding to the valid free storage cell flag field to a second logical value (eg, 0).

When the receiving circuit 230 receives a received packet, the idle basic storage unit controller 220 can obtain at least one idle basic storage unit for temporarily storing the received packet through the SRAM buffer 200 and the register buffer 210 , for example, the idle basic storage unit controller 220 will first find out the 4 second bits (such as the second bit e to the second bit h) of the register buffer 210 that have the first logic value (eg 1) of a target second bit (eg second bit e, second bit f or second bit h) to obtain a read address, and read static A target effective free storage unit flag field in the bit table 201 of the random access memory buffer 200 (for example, an effective free memory unit flag field a corresponding to the second bit e, a field corresponding to the second bit f The valid free storage unit flag field b or the valid spare memory unit flag field d) corresponding to the second bit h, and finally find the first logic value (such as 1) from the target valid free memory unit flag field ) to obtain at least one free basic storage unit.

It should be noted that, after the at least one idle basic storage unit is used to temporarily store the received packet, the idle basic storage unit controller 220 can also be used to set the at least one target corresponding to the at least one idle basic storage unit first The bit is updated from a first logic value (such as 1) to a second logic value (such as 0). In addition, when the idle basic storage unit controller 220 updates the at least one target first corresponding to the at least one idle basic storage unit After the bit, when all the first bits in the target valid idle cell flag field including the at least one target first bit have a second logic value (for example, 0), the basic cell controller 220 is idle It can also be used to update the second bit of the register buffer 210 corresponding to the target effective free storage unit flag field from a first logic value (such as 1) to a second logic value (such as 0), on the other hand After the idle basic storage unit controller 220 has updated the at least one target first bit corresponding to the at least one idle basic storage unit, the target valid idle storage unit flag column containing the at least one target first bit When the bit still contains at least one first bit with a first logic value (for example, 1), the idle basic storage unit controller 220 can additionally be used to mark the effective idle storage unit corresponding to the target in the register buffer 210 The second bit of the field remains at the first logical value (eg, 1). The idle basic storage unit controller 220 can implement the 32 first bits in the bit table of the SRAM buffer 200 and the 4 second bits of the register buffer 210 through a pipeline (pipeline) mode. bit update, but the present invention is not limited thereto.

When the transmission circuit 240 finishes transmitting a transmission packet, the transmission circuit 240 releases (releases) at least one basic storage unit corresponding to the transmission packet to the idle basic storage unit controller 220, and the idle basic storage unit controller 220 can be used to The at least one basic storage unit of the packet is used to change at least one target first bit in the at least one target effective idle storage unit flag field in the bit table 201 of the SRAM buffer 200 by a second logic value ( For example, 0) is updated to a first logic value (for example, 1), that is, at least one basic storage unit corresponding to the at least one target first bit is at least one idle basic storage unit. In addition, in the case that at least one target first bit in the originally at least one target valid free storage unit flag field has a second logical value (for example, 0) (that is, the original at least one target valid free storage unit flag There is no idle basic storage unit in the field), after the idle basic storage unit controller 220 has updated the at least one target first bit, the at least one target effective idle storage unit containing the at least one target first bit When the flag field contains at least one first bit with a first logical value (for example, 1), the idle basic storage unit controller 220 can also be used to effectively idle the memory corresponding to the at least one object in the register buffer 210 At least one second bit of the unit identification field is updated from a second logic value (such as 0) to a first logic value (such as 1). In the case of including at least one first bit with a first logic value (for example, 1) (that is, the original at least one target effective free storage unit flag field already has a free basic storage unit), the idle basic storage unit controller 220 may also be used to maintain at least one second bit corresponding to the at least one target valid free storage unit flag field in the register buffer 210 as a first logical value (eg, 1).

In addition, in order to reduce the power consumption of the memory buffer and save the bandwidth of the memory buffer, a free basic storage unit buffer can be used to reduce the number of access times of the memory buffer. FIG. 3 is a basic memory buffer according to another embodiment of the present invention. A schematic diagram of the memory cell management circuit 30 . As shown in FIG. 3, the basic storage unit management circuit 30 may include a memory buffer (such as a static random access memory buffer 300; for brevity, labeled as "SRAM buffer" in FIG. 3), a register buffer controller 310, idle basic storage unit controller 320, receiving circuit 330, transmission circuit 340, and release basic storage unit buffer 350, wherein the basic storage unit management circuit 30 shown in FIG. 3 is the same as the basic storage unit management circuit shown in FIG. 2 20 is that the basic storage unit management circuit 30 may further include a release basic storage unit buffer 350 . The release basic storage unit buffer 350 can be coupled to the idle basic storage unit controller 320 and the transmission circuit 340, and can be used to temporarily store at least one basic storage unit corresponding to the transmission packet released when the transmission circuit 340 finishes transmitting a transmission packet , wherein the free basic storage unit controller 320 can acquire at least one basic storage unit corresponding to the transmission packet from the released basic storage unit buffer 350 as the free basic storage unit. In this way, when the receiving circuit 330 receives a received packet, the idle basic storage unit controller 320 can pre-read at least one basic storage unit corresponding to the transmission packet temporarily stored in the released basic storage unit buffer 350 for use The received packet is used without going through the SRAM buffer 300 and the register buffer 310 to obtain idle basic storage units (which reduces the access times of the SRAM buffer 300 ).

In this embodiment, the idle basic storage unit corresponding to the first bit B10 in the SRAM buffer 300 (which is represented by 5 bits whose decimal value is 10) is temporarily stored in the basic storage unit buffer 350 for release. into free basic storage unit buffer 350, and labeled "5'd10" in FIG. into free basic storage unit buffer 350, and labeled "5'd21" in FIG. into the free basic storage unit buffer 350, and is labeled "5'd22" in FIG. into the freed basic cell buffer 350, and is labeled "5'd27" in FIG. 3). It should be noted that when at least one basic storage unit corresponding to the transmission packet temporarily stored in the released basic storage unit buffer 350 is occupied (that is, there is no idle basic storage unit in the released basic storage unit buffer 350), The idle basic storage unit controller 320 can find out a target second bit with a first logic value (for example, 1) from the 4 second bits of the register buffer 310 to obtain a read address, and According to the read address, read a target effective free storage unit flag field in the bit table 301 of the SRAM buffer 300, and find out the first logic from the target effective free memory unit flag field At least one target first bit of a value (eg, 1) is used to obtain at least one free basic storage unit for receiving packets. In other words, if the free basic storage unit buffer 350 has an idle basic storage unit available for use, the idle basic storage unit controller 320 will preferentially read the released basic storage unit buffer 350, if it cannot be obtained from the released basic storage unit buffer 350 For the desired free basic storage unit, the free basic storage unit controller 320 obtains the free basic storage unit through the register buffer 310 and the SRAM buffer 300 .

In the above-mentioned embodiment, the idle basic storage unit controller 220 (or the idle basic storage unit controller 320) can quickly use the second bit stored in the register buffer 210 (or the register buffer 310) From the bit table of the SRAM buffer 200 (or the SRAM buffer 300), find the first bit indicating a free basic storage unit, however, the scratchpad buffer may be optional ) components, for example, in some embodiments of the present invention, the data management circuit 20 (or the data management circuit 30) can omit the register buffer 210 (or the register buffer 310), and directly A search is performed in the bit table of the RAM buffer 200 (or the SRAM buffer 300 ) to find the first bit indicating a free basic memory unit. To sum up, any data management circuit that uses the bits recorded in the bit table to indicate whether the corresponding basic storage unit is an idle basic storage unit falls within the scope of the present invention.

FIG. 4 is a flow chart of a basic storage unit management method according to an embodiment of the invention. If the same result can be obtained, the steps do not have to be executed sequentially according to the flow shown in FIG. 4. For example, the basic storage unit management method shown in FIG. Or the data management circuit 30 shown in FIG. 3 is implemented.

In step S400, the static random access memory buffer can store a bit table, wherein the bit table can include a plurality of first bits, which respectively correspond to a plurality of basic storage units, and a plurality of first bits Each first bit in can be used to indicate whether the corresponding basic storage unit is an idle basic storage unit.

In step S402, an idle basic storage unit controller may be used to manage the bit table, and at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit is processed according to the bit table, wherein When a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller may set a first bit corresponding to the basic storage unit to a first logic value, and when the plurality of basic storage units When the basic storage unit of the basic storage units is not an idle basic storage unit, the idle basic storage unit controller can set the first bit corresponding to the basic storage unit to a second logical value.

Since a skilled person can easily understand the operation of each step shown in FIG. 4 through the content of the above description, for the sake of brevity, the similar content in this embodiment will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A basic storage unit management circuit, comprising: a receiving circuit; a transmission circuit; A first buffer for storing a bit table, wherein the bit table includes a plurality of first bits, which respectively correspond to a plurality of basic storage units, and each of the plurality of first bits One bit is used to indicate whether a corresponding basic storage unit is an idle basic storage unit; an idle basic storage unit controller, coupled to the receiving circuit, the transmitting circuit and the first buffer, and used for managing the bit table stored in the first buffer, and processing according to the bit table At least one basic storage unit corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controls The controller sets a first bit corresponding to the basic storage unit to a first logical value; and when the basic storage unit of the plurality of basic storage units is not the idle basic storage unit, the idle basic storage unit controller The first bit corresponding to the basic storage unit is set as a second logic value. 2. The basic storage unit management circuit as claimed in claim 1, wherein the plurality of first bits in the bit table are divided into a plurality of valid idle storage unit flag fields, and the basic storage unit management circuit further Include: A second buffer, coupled to the idle basic storage unit controller, and used to store a plurality of second bits, which respectively correspond to the plurality of effective idle storage unit flag fields, wherein the plurality of second bits Each second bit in is used to indicate whether at least one first bit with the first logical value is contained in a corresponding valid free storage unit flag field; Wherein when a valid idle storage unit identification field of the plurality of valid idle storage unit identification fields includes the at least one first bit with the first logic value, the idle basic storage unit controller stores the effective idle storage unit A second bit corresponding to the unit flag field is set as a logic value among the first logic value and the second logic value; When all the first bits included in the flag field have the second logic value, the idle basic storage unit controller sets the second bit corresponding to the effective idle memory unit flag field to the first logic value value and the other logical value of the second logical value. 3. The basic storage unit management circuit as claimed in claim 2, wherein when the receiving circuit receives a received packet, the idle basic storage unit controller first finds out from the plurality of second bits of the second buffer A target second bit with the logical value is obtained to obtain a read address, and a target valid free storage unit flag column in the bit table of the first buffer is read according to the read address bits, and find out at least one target first bit with the first logic value from the target effective free storage unit flag field to obtain at least one free basic storage unit. 4. The basic storage unit management circuit as claimed in claim 3, wherein the idle basic storage unit controller is further configured to update the at least one target first bit from the first logic value to the second logic value. 5. The basic storage unit management circuit as claimed in claim 2, wherein when the transmission circuit finishes transmitting a transmission packet, the transmission circuit releases at least one basic storage unit corresponding to the transmission packet to the idle basic storage unit controller . 6. The basic storage unit management circuit as claimed in claim 5, wherein the idle basic storage unit controller is further configured to list the bits in the first buffer according to the at least one basic storage unit of the transport packet At least one target first bit in the at least one target valid free storage unit flag field is updated from the second logic value to the first logic value. 7. The basic storage unit management circuit as claimed in claim 2, further comprising: a release basic storage unit buffer, coupled to the transmission circuit and the idle basic storage unit controller, and used to temporarily store at least one basic storage corresponding to the transmission packet released when the transmission circuit finishes transmitting a transmission packet unit, wherein the free basic storage unit controller acquires the at least one basic storage unit corresponding to the transport packet from the released basic storage unit buffer as a free basic storage unit. 8. The basic storage unit management circuit as claimed in claim 7, wherein when the receiving circuit receives a received packet, the idle basic storage unit controller reads the buffer corresponding to the free basic storage unit The at least one basic storage unit of the transmitted packet is used by the received packet. 9. The basic storage unit management circuit as claimed in claim 8, wherein when the at least one basic storage unit corresponding to the transmission packet temporarily stored in the released basic storage unit buffer is occupied, the idle basic storage unit The unit controller finds a target second bit with the logic value from the plurality of second bits of the second buffer to obtain a read address, and reads the read address according to the read address. a target valid free storage unit flag field in the bit table of the first buffer, and at least one target first bit with the first logical value is found from the target valid free memory unit flag field to Obtain at least one free basic storage unit for use by the received packet. 10. A basic storage unit management method, comprising: storing a bit table, wherein the bit table includes a plurality of first bits corresponding to a plurality of basic storage units, and each first bit in the plurality of first bits is used to indicate a phase whether the corresponding basic storage unit is an idle basic storage unit; and Use an idle basic storage unit controller to manage the bit table, and process at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit according to the bit table, wherein when the plurality of When a basic storage unit of the basic storage unit is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit to a first logic value, and when the plurality of basic storage units When the basic storage unit of the storage unit is not the idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit to a second logic value.

Images