CN116153610A - Inductance structure and forming method thereof - Google Patents

Abstract

The technical solution of the present application provides an inductance structure and its forming method. The inductance structure includes: an inductance main wire distributed in a spiral shape, and includes a plurality of inductance sub-wires isolated by an insulating layer; a first auxiliary wire correspondingly arranged in the phase Below the insulating layer adjacent to the inductance sub-wires; the second auxiliary wire connects the adjacent inductance sub-wires and the corresponding first auxiliary wires; wherein, the inductance main wire, the first auxiliary wire forming a conductive path with the second auxiliary wire. The technical solution of the present application can improve the electromigration resistance of the inductor structure.

Description

Inductor structure and its formation method

technical field

The present application relates to the field of semiconductor manufacturing, and in particular to an inductor structure and a forming method thereof.

Background technique

As a magnetic energy storage element, the inductance element can realize many functions when used in conjunction with the electric energy storage element. Inductive components have the ability to pass low frequency and block high frequency, and can be used to reduce power supply voltage, filter and other circuits to play a key role, and are an indispensable and important component of radio frequency circuits. When the device is working, a certain current flows through the metal interconnection, and the metal ions will generate mass transport along the conductor. As a result, holes or whiskers (hills) will be generated in some parts of the conductor, which will lead to metal interconnection. Open circuit or short circuit, this is the phenomenon of electromigration.

In a DC circuit, the current is evenly distributed over a uniform wire cross-section. However, in AC circuits such as radio frequency, when the alternating current passes through the conductor, due to the electromagnetic field around the conductor, the conductor itself will generate additional eddy currents, and the magnetic field of the eddy current will cause the current in the conductor to tend to concentrate on the surface of the conductor, while the current inside the conductor Density drops. That is, the current density on the wire is the maximum on the surface, and decreases with the increase of the depth into the wire. This phenomenon is called the skin effect. As the design frequency continues to increase, the adhesion effect becomes more serious, and the current becomes more concentrated on the thinner surface of the conductor. The existence of the skin effect reduces the effective cross-sectional area of the wire, and the current mainly passes through the surface layer of the wire, while the current passing through the inner layer of the wire is very small or even completely zero. However, due to the reduction of the effective cross-sectional area, the current density carried by the wire in the current-passing part increases sharply, which will significantly increase the risk of electromigration failure of the inductor wire.

In addition, the general-purpose inductance components are basically designed in the form of concentric multi-turn coils. Due to the current edge effect and local Joule heating at the bending position of the connection, the risk of electromigration will further increase. The commonly used inductance scheme is usually composed of the uppermost layer or two layers of metal interconnection wires. The requirements of different inductance values can be achieved by changing the number of coil turns. It has not been widely accepted to improve the electromigration resistance of inductors. sexual method.

Contents of the invention

The technical problem to be solved in this application is to improve the electromigration resistance of the inductive structure.

In order to solve the above-mentioned technical problems, the present application provides an inductance structure, which includes: the inductor main wire, which is distributed in a spiral shape, and includes several inductor sub-wires separated by insulating layers; the first auxiliary wire is correspondingly arranged in the adjacent Below the insulating layer between the inductance sub-wires; the second auxiliary wire connects the adjacent inductance sub-wires and the corresponding first auxiliary wires; wherein, the inductance main wire, the first auxiliary wire and the The second auxiliary wire forms a conductive path.

In the embodiment of the present application, the length of the inductor sub-wires is 40 μm˜70 μm, and the total length of all the inductor sub-wires is 3 mm˜20 mm.

In the embodiment of the present application, the length difference of the insulating layer between the first auxiliary wire and the adjacent inductor sub-wire is 0.1 μm to 2 μm, and the length of the first auxiliary wire and the inductor sub-wire is The width difference is 0 to 10 μm.

In the embodiment of the present application, the inductance structure further includes: a first dielectric layer located between adjacent first auxiliary wires and between adjacent second auxiliary wires, wherein the bottom of the insulating layer is The first dielectric layer is adjacent, and the top of the insulating layer extends to the surface of the inductor sub-conductor.

In the embodiment of the present application, the bottom of the insulating layer is adjacent to the first auxiliary wire, and the top of the insulating layer is coplanar with the surface of the inductor wire; the second dielectric layer is located adjacent to the Between the first auxiliary wires; the third dielectric layer is located on the surface of the second dielectric layer and is adjacent to the second auxiliary wires and the inductor sub-wires; the fourth dielectric layer is located between the insulating layer and the inductance sub-wires. The surface of the inductor wire described above.

In the embodiment of the present application, the first auxiliary wire, the second auxiliary wire, and the inductor sub-wire all include an adhesion layer, a seed layer, and an electroplating epitaxial layer that are sequentially stacked and distributed.

In the embodiment of the present application, the inductor main wire is the top wire layer in the interconnection structure, the first auxiliary wire is a wire layer below the top wire layer, and the second auxiliary wire is the The wire connection between the top wire layer and the certain wire layer.

The present application also provides a method for forming an inductor structure, including: forming discrete first auxiliary wires; forming a first dielectric layer between adjacent first auxiliary wires and on the surface of the first auxiliary wires; A discrete second auxiliary wire is formed in the first dielectric layer on the surface of the first auxiliary wire, and the surface of the second auxiliary wire is coplanar with the surface of the first dielectric layer; on the second auxiliary wire The surface of the first dielectric layer and part of the surface of the first dielectric layer form an inductor main wire, and the inductor main wire includes a plurality of inductor sub-wires distributed at intervals; between adjacent inductor sub-wires and on the surface of the inductor sub-wire An insulating layer is formed; wherein, a first auxiliary wire is correspondingly disposed under the insulating layer between adjacent inductor sub-wires, and the second auxiliary wire connects adjacent inductor sub-wires and corresponding first auxiliary wires wires to form a conductive path.

In the embodiment of the present application, the method for forming the first auxiliary wire includes: forming a first auxiliary wire material layer; etching part of the first auxiliary wire material layer to form a plurality of first auxiliary wires separated by first openings; Auxiliary wire.

In the embodiment of the present application, the method for forming the second auxiliary wire includes: etching part of the first dielectric layer on the surface of each of the first auxiliary wires to form a second opening; in the second opening and forming a second auxiliary wire material layer on the surface of the first dielectric layer; planarizing the second auxiliary wire material layer so that the second auxiliary wire material layer is coplanar with the surface of the first dielectric layer, and The second auxiliary wire is formed in the second opening.

In the embodiment of the present application, the method for forming the inductor main wire includes: forming an inductor main material layer on the surface of the second auxiliary wire and the first dielectric layer; etching part of the surface of the first dielectric layer The inductor main wire material layer forms several inductor sub-wires separated by the third opening, and the second auxiliary wire connects the inductor sub-wires at both ends of the third opening and the corresponding first auxiliary wires.

In the embodiment of the present application, the method for forming the insulating layer includes: forming an insulating material in the third opening and on the surface of the inductor main wire; planarizing the insulating material to a target thickness to form the insulating layer .

The present application also provides another method for forming an inductance structure, including: forming discrete first auxiliary wires, and including a second dielectric layer between adjacent first auxiliary wires; A third dielectric layer is formed on the surface of the second dielectric layer; a second auxiliary wire, an inductor main wire, and an insulating layer are formed in the third dielectric layer; wherein, the second auxiliary wire is located at a part of the first auxiliary wire The surface of the inductor main wire is located on the surface of the second auxiliary wire and part of the third dielectric layer, and the inductor main wire includes several inductor sub-wires separated by the insulating layer, adjacent to the inductor A first auxiliary wire is correspondingly disposed under the insulating layer between the sub-wires, and the second auxiliary wire connects the inductance sub-wires at both ends of the insulating layer and the corresponding first auxiliary wires to form a conductive path.

In the embodiment of the present application, the method for forming the first auxiliary wire and the second dielectric layer includes: forming a second dielectric material layer; etching the second dielectric material layer to form a fourth opening and a second dielectric layer layer; sequentially form a first adhesion layer, a first seed layer, and a first electroplating epitaxial layer in the fourth opening; planarize, so that the first adhesion layer, the first seed layer, and the first electroplating epitaxial layer layer and the surface of the second dielectric layer are coplanar, and the first auxiliary wire is formed in the fourth opening.

In the embodiment of the present application, the method for forming the second auxiliary wire, the inductor main wire and the insulating layer includes: etching part of the third dielectric layer to form a first groove for defining the inductor main wire; etching Part of the third dielectric layer at the bottom of the first trench forms an insulating layer and a first through hole for defining the second auxiliary wire; sequentially formed in the first trench and the first through hole The second adhesion layer, the second seed layer and the second electroplating epitaxial layer; performing planarization so that the surfaces of the second adhesion layer, the second seed layer, the second electroplating epitaxial layer and the insulating layer are coplanar, The inductor sub-wire is formed in the first trench, and the second auxiliary wire is formed in the first through hole.

In the embodiment of the present application, the method for forming the second auxiliary wire, the inductor main wire and the insulating layer includes: etching part of the third dielectric layer, stopping on part of the first auxiliary wire, and forming a second through hole; Etching the third dielectric layer on one side of the second through hole to form an insulating layer and a third through hole for defining the second auxiliary wire and a second trench for defining the inductor sub-wire; A third adhesion layer, a third seed layer, and a third electroplating epitaxial layer are sequentially formed in the second groove and the third through hole; planarization is performed so that the third adhesion layer, the third seed layer , the surface of the third electroplating epitaxial layer and the insulating layer are coplanar, the inductor sub-wire is formed in the second groove, and the second auxiliary wire is formed in the third through hole.

The technical solution of the present application divides the long wire of the inductance coil into several inductance sub-wires with shorter length and spaced distribution, and connects the inductance sub-wires in series through the first auxiliary wire and the second auxiliary wire, wherein the second auxiliary wire The metal atom migration movement caused by electromigration is blocked, so that the effective electromigration length of the inductor main wire is shortened to the length of the separated inductor sub-wire, thereby improving the electromigration resistance.

The inductor main wire can be used as the top wire layer in the interconnection structure, the first auxiliary wire can be used as a wire layer below the top wire layer, and the second auxiliary wire can be used as a wire between the top wire layer and a certain wire layer Therefore, the inductor structure of the present application is compatible with the interconnection structure, and can greatly improve the electromigration resistance of the inductor under the condition of alternating current without changing the current overall structure design of the inductor.

Description of drawings

The following figures describe in detail exemplary embodiments disclosed in this application. Wherein the same reference numerals denote similar structures in the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the accompanying drawings are for illustration and description purposes only, and are not intended to limit the scope of the application, and other embodiments are also possible Complete the invention intention among the application likewise. It should be understood that the drawings are not drawn to scale. in:

FIG. 1 is a schematic top view of an inductor structure of an embodiment of the present application;

Fig. 2 is a cross-sectional view at the A-A position in Fig. 1;

Fig. 3 is the electromigration test result diagram of the inductance structure of the embodiment of the present application;

4 to 8 are structural schematic diagrams of each step of a method for forming an inductance structure according to an embodiment of the present application;

FIG. 9 to FIG. 18 are structural schematic diagrams of each step of another method for forming an inductor structure according to an embodiment of the present application.

Detailed ways

The following description provides specific application scenarios and requirements of the application, with the purpose of enabling those skilled in the art to manufacture and use the contents of the application. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and embodiments without departing from the spirit and scope of the application. application. Thus, the application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The embodiment of the present application provides an inductor structure. Based on the process technology in the current mainstream semiconductor manufacturing field, by adjusting the design of the inductor structure and combining the research results in the field of electromigration, the inductance can be effectively improved without changing the overall structure design of the current mainstream inductor. Electromigration resistance under AC current conditions, and at the same time, it can also dynamically balance design of electromigration resistance, inductance device resistance and even quality factor based on actual use requirements.

Referring to FIG. 1 and FIG. 2 , wherein FIG. 2 is a cross-sectional view at position A-A of FIG. 1 , and FIG. 1 and FIG. 2 only show the main structure forming the conductive path. The inductor structure includes: an inductor main wire, a first auxiliary wire 200 and a second auxiliary wire 300 . Wherein the main inductor wire includes several inductor sub-wires 100 discontinuously distributed, and the adjacent inductor sub-wires 100 are separated by an insulating layer 400 (not shown in FIG. 2 , refer to FIG. 8 ). The inductor main wire in the embodiment of the present application is no longer a continuous and uninterrupted long wire, but is composed of several shorter inductor sub-wires 100 . By splitting the long wires into separated short wires, the effective electromigration length of the wires is shortened to the length of the separated short wires, thereby improving the electromigration resistance.

The conductive wires of the inductance body are distributed in a spiral shape to form an inductance coil, and the shape of the inductance coil may be a quadrilateral or a polygon with more sides. FIG. 1 only shows the shape of a square inductor coil, and other shapes can also be used in other embodiments. The inductor sub-conductor 100 may be the top conductor layer in the interconnection structure. The material of the inductor sub-conductor 100 may include metal, such as tungsten, aluminum, copper and so on.

The first auxiliary wire 200 is correspondingly disposed under the insulating layer 400 between adjacent inductor sub-wires 100 , and the first auxiliary wire 200 acts as a bridge for connecting adjacent inductor sub-wires 100 . Inductor wire 100. In some embodiments, the length of the first auxiliary wire 200 is greater than the length of the insulating layer 400 between adjacent inductor sub-wires 100 , and the width of the first auxiliary wire 200 is larger than that of the inductor sub-wires. The width of the wire 100 is favorable for forming the second auxiliary wire 300 . In some embodiments, the length difference between the first auxiliary wire 200 and the insulating layer 400 between the adjacent inductor sub-wires 100 is 0.1 μm-2 μm, and the first auxiliary wire 200 and the inductor The width difference of the sub-wires 100 is 0-10 μm. The extending direction of the first auxiliary wire 200 and the corresponding extending direction of the insulating layer 400 between the adjacent inductor sub-wires 100 are parallel to each other. The first auxiliary wire 200 may be a wire layer below the top wire layer of the interconnection structure. The material of the first auxiliary wire 200 may include metal, such as tungsten, aluminum, copper and so on.

The second auxiliary wire 300 is located between the main inductor wire and the first auxiliary wire 200 to connect adjacent inductor sub-wires 100 and the corresponding first auxiliary wire 200 . The second auxiliary wire 300 is perpendicular to the extending direction of the first auxiliary wire 200 . The second auxiliary wire 300 and the first auxiliary wire 200 together connect the inductor sub-wire 100 in series, so that the inductor main wire, the first auxiliary wire 200 and the second auxiliary wire 300 form a conductive path. The second auxiliary wire 300 may be a wire connection between the top wire layer and a certain lower wire layer in the interconnection structure. The material of the second auxiliary wire 300 may include metal, such as tungsten, aluminum, copper and so on.

The total length of the inductor sub-wire 100 , that is, the length of the main inductor wire, is related to the electromigration resistance. The smaller the total length of the inductor sub-wire 100 , the stronger the electromigration resistance. Generally speaking, when the length of the inductor body lead is shortened from 200 μm to 50 μm, the electromigration resistance will be improved by more than ten times. In the embodiment of the present application, the longer inductor main wire is split into shorter inductor sub-wires 100, and the second auxiliary wire 300 and the lower first auxiliary wire are passed between adjacent inductor sub-wires 100. 200 connected in series. Due to the existence of the second auxiliary wire 300, the metal atom migration movement caused by electromigration is blocked, so that the effective electromigration length of the main inductor wire is shortened to the length of the inductor sub-wire 100 formed separately, thereby Improvement of electromigration resistance is achieved.

The length of the main wire of the inductor should be within the capability of the selected process platform, which can effectively realize the shortest length of the inductor structure, so as to avoid insufficient electromigration resistance of the overly long first auxiliary wire 200 and affect the overall electromigration life of the inductor. In the embodiment of the present application, the length of the inductor sub-conductor 100 is 40 μm˜70 μm. The total length of all inductor sub-conductors is 3mm-20mm.

The EM test was performed on the inductor structure of the embodiment of the present application on a 40nm platform, and the test results comprehensively reflected the overall EM resistance of the inductor main wire and the second auxiliary wire. Referring to Figure 3, where V1D represents a continuous wire structure with a length of 400 μm, and V1C represents the inductance structure of the embodiment of the present application with the same length, it can be seen that the device life using the inductance structure of the embodiment of the present application can achieve a 40-fold increase in life .

In other embodiments, it is also possible to dynamically adjust the lengths of the separated inductance sub-conductors according to the overall electromigration resistance capability of the inductor and the requirements of the inductance resistance, for example, adopting a longer length to sacrifice part of the electromigration resistance capability , to obtain a lower inductance resistance; or use a shorter length to sacrifice part of the inductance resistance to obtain stronger electromigration resistance.

Referring to FIG. 8, in some embodiments, the inductor structure further includes: a first dielectric layer 610, the first dielectric layer 610 is located between adjacent first auxiliary wires 200 and adjacent to the second auxiliary wires. Surfaces between the wires 300 and the first dielectric layer 610 are coplanar with the surface of the second auxiliary wire 300 . The material of the first dielectric layer 610 may include silicon oxide, silicon nitride or silicon oxynitride and the like. The bottom of the insulating layer 400 is adjacent to the first dielectric layer 610 , and the top of the insulating layer 400 extends to the surface of the inductor sub-wire 100 .

Referring to FIG. 18 , in some other embodiments, the first auxiliary wire 200 , the second auxiliary wire 300 and the inductor sub-wire 100 may all include an adhesive layer, a seed layer and an electroplating epitaxial layer in a stacked distribution. The material of the adhesion layer may include tantalum, tantalum nitride, titanium or titanium nitride, etc., and the material of the seed layer and the electroplating epitaxial layer may include copper or other alloys, for example. The bottom of the insulating layer 400 is adjacent to the first auxiliary wire 200 and the top of the insulating layer 400 is coplanar with the surface of the inductor sub-wire 100 . The insulating layer 400 is not only used to isolate the adjacent inductor sub-wires 100 , but also isolates the second auxiliary wire 300 on the same first auxiliary wire 200 . The inductor structure further includes: a second dielectric layer 620, a third dielectric layer 630 and a fourth dielectric layer 640, wherein the second dielectric layer 620 is located between adjacent first auxiliary wires 200, and the third The dielectric layer 630 is located on the surface of the second dielectric layer 620 and is adjacent to the second auxiliary wire 300 and the inductor wire 100 , the fourth dielectric layer 640 is located between the insulating layer 400 and the inductor surface of the wire 100. The materials of the second dielectric layer 620 , the third dielectric layer 630 , the fourth dielectric layer 640 and the insulating layer 400 may be the same or different. For example, the materials of the second dielectric layer 620 , the third dielectric layer 630 , the fourth dielectric layer 640 and the insulating layer 400 may include silicon oxide, silicon nitride or silicon oxynitride.

The embodiment of the present application also provides a method for forming an inductor structure, including:

Step S10: forming discrete first auxiliary wires;

Step S20: forming a first dielectric layer between adjacent first auxiliary wires and on the surface of the first auxiliary wires;

Step S30: forming discrete second auxiliary wires in the first dielectric layer on the surface of each of the first auxiliary wires, and the second auxiliary wires are coplanar with the surface of the first dielectric layer;

Step S40: forming an inductor main wire on the surface of the second auxiliary wire and part of the surface of the first dielectric layer, and the inductor main wire includes a plurality of inductor sub-wires distributed at intervals;

Step S50: Form an insulating layer between adjacent inductor sub-wires and on the surface of the inductor sub-wires, wherein a first auxiliary wire is correspondingly arranged under the insulating layer between adjacent inductor sub-wires, and the The second auxiliary wire is connected to the adjacent inductor sub-wire and the corresponding first auxiliary wire to form a conductive path.

Referring to FIG. 4 , discrete first auxiliary wires 200 are formed. The first auxiliary wire 200 may be formed on a substrate 500, and the substrate 500 may include a device structure not shown in FIG. 4, a part of an interconnection structure, and the like. The distribution manner of the first auxiliary wires 200 is determined according to the structure of the subsequently formed inductor main wires. The first auxiliary wire 200 may serve as a certain wire layer below the top wire layer in the interconnection structure. In the embodiment of the present application, the method for forming the first auxiliary wire 200 may include: forming a first auxiliary wire material on the surface of the substrate 500, for example, by chemical vapor deposition, physical vapor deposition and other deposition processes; A portion of the first auxiliary wire material is etched to form a plurality of first auxiliary wires 200 separated by the first opening 710 . The material of the first auxiliary wire 200 may include metal, such as aluminum, tungsten and the like.

Referring to FIG. 5 , a first dielectric layer 610 is formed in the first opening 710 between adjacent first auxiliary wires 200 and on the surface of the first auxiliary wires 200 . The method for forming the first dielectric layer 610 may be chemical vapor deposition, physical vapor deposition and other deposition processes. The material of the first dielectric layer 610 may include silicon oxide, silicon nitride or silicon oxynitride and the like.

Referring to FIG. 6, a part of the first dielectric layer 610 on the surface of each of the first auxiliary wires 200 is etched to form a second opening; a second opening is formed in the second opening and on the surface of the first dielectric layer 610. Two auxiliary wire material layers; planarize the second auxiliary wire material layer, make the second auxiliary wire material layer and the surface of the first dielectric layer 610 coplanar, and form the first auxiliary wire material layer in the second opening Two auxiliary wires 300 . The second auxiliary wires 300 are separately located in the first dielectric layer 610 on the surface of each of the first auxiliary wires 200, and the surfaces of the second auxiliary wires 300 and the first dielectric layer 610 are coplanar . The material of the second auxiliary wire 300 may include metal, such as aluminum, tungsten and the like.

Referring to FIG. 7 and FIG. 8 , an inductor body material layer 110 is formed on the surfaces of the first dielectric layer 610 and the second auxiliary wire 300 . For example, deposition processes such as physical vapor deposition and chemical vapor deposition can be used. Then, etching part of the inductance body material layer 110 on the surface of the first dielectric layer 610 exposes the surface of the first dielectric layer 610 between the second auxiliary wires 300 on each first auxiliary wire 200 to form A plurality of inductor sub-wires 100 separated by the third opening, and the second auxiliary wire 300 connects the inductor sub-wires 100 at both ends of the third opening and the corresponding first auxiliary wires 200 . Subsequently, an insulating material is formed in the third opening between adjacent inductor sub-wires 100 and on the surface of the inductor sub-wire 100 ; the insulating material is planarized to a target thickness to form the insulating layer 400 . The second auxiliary wire 300 is connected to the adjacent inductor sub-wire 100 and the corresponding first auxiliary wire 200 below, so that the main inductor wire, the first auxiliary wire 200 and the second auxiliary wire 300 Form a conductive path.

The embodiment of the present application also provides another method for forming an inductor structure, including:

Step S100: forming discrete first auxiliary wires, and including a second dielectric layer between adjacent first auxiliary wires;

Step S200: forming a third dielectric layer on the surface of the first auxiliary wire and the second dielectric layer;

Step S300: forming a second auxiliary wire, an inductor main wire and an insulating layer in the third dielectric layer;

Wherein, the second auxiliary wire is located on a part of the surface of the first auxiliary wire, the inductor main wire is located on the surface of the second auxiliary wire and part of the third dielectric layer, and the inductor main wire includes a The plurality of inductance sub-wires separated by the insulating layer, the first auxiliary wire is correspondingly arranged under the insulating layer between the adjacent inductance sub-conductors, and the second auxiliary wire connects the inductance sub-conductors at both ends of the insulation layer and Correspondingly, the first auxiliary wire forms a conductive path.

Referring to FIG. 9, a second dielectric material layer is formed. The second dielectric material layer may be formed on a substrate 500 in which device structures, partial interconnect structures, and the like are formed. The second dielectric material layer is etched to form the fourth opening 720 and the second dielectric layer 620 . The material of the second dielectric layer 620 may include silicon oxide, silicon nitride, silicon oxynitride and the like.

Referring to FIG. 10 , the first adhesion layer 210 , the first seed layer 220 and the first electroplating epitaxial layer 230 are sequentially formed in the fourth opening 720 . performing planarization, making the surfaces of the first adhesion layer 210, the first seed layer 220, the first electroplating epitaxial layer 230 and the second dielectric layer 620 coplanar, forming the first An auxiliary wire 200 , the first auxiliary wire 200 includes a first adhesive layer 210 , a first seed layer 220 and a first electroplating epitaxial layer 230 . The material of the first adhesion layer 210 may include, for example, tantalum, tantalum nitride, titanium or titanium nitride, and the materials of the first seed layer 220 and the first electroplating epitaxial layer 230 include metals, such as copper or other alloys.

Referring to FIG. 11 , a third dielectric layer 630 is formed on the surfaces of the first auxiliary wire 200 and the second dielectric layer 620 . The material of the third dielectric layer 630 may include silicon oxide, silicon nitride or silicon oxynitride and the like. The process for forming the third dielectric layer 630 may be a common deposition process, such as chemical vapor deposition, physical vapor deposition, and the like.

Next, a second auxiliary wire, an inductor main wire and an insulating layer are formed in the third dielectric layer 630 .

In some embodiments, the method for forming the second auxiliary wire, the inductor main wire and the insulating layer may include the following steps:

Referring to FIG. 12 , a part of the third dielectric layer 630 is etched to form a first trench 730 , and the first trench 730 is used to define the conductive line of the inductor body.

Referring to FIG. 13, a part of the third dielectric layer 630 at the bottom of the first trench 730 is etched by a photolithography process to form an insulating layer 400 and a first through hole 740, and the first through hole 740 is used to define the second auxiliary wire.

Referring to FIG. 14, a second adhesion layer, a second seed layer, and a second electroplating epitaxial layer are sequentially formed in the first trench 730 and the first through hole 740, and the three-layer structure is not distinguished in the figure , the distribution and material selection of the three-layer structure can refer to the first adhesion layer 210 , the first seed layer 220 and the first electroplating epitaxial layer 230 in FIG. 10 . Then perform planarization, make the surfaces of the second adhesion layer, the second seed layer, the second electroplating epitaxial layer and the insulating layer 400 coplanar, and form the inductor sub-conductor in the first trench 730 100 , forming the second auxiliary wire 300 in the first through hole 740 . The inductor sub-wire 100 and the second auxiliary wire 300 include a second adhesive layer, a second seed layer and a second electroplating epitaxial layer. Adjacent inductor sub-wires 100 are isolated by the insulating layer 400 , and the insulating layer 400 also extends to the surface of the first auxiliary wire 200 .

In some other embodiments, the method for forming the second auxiliary wire, the inductor main wire and the insulating layer may include the following steps:

Referring to FIG. 15 and FIG. 16 , a part of the third dielectric layer 630 is etched to stop on a part of the first auxiliary wire 200 to form a second via hole 750 . Etching part of the third dielectric layer 630 on one side of the second through hole 750 to form the insulating layer 400 and the third through hole 760 for defining the second auxiliary wire and the second trench 770 for defining the inductor sub wire .

Referring to FIG. 17, a third adhesion layer, a third seed layer and a third electroplating epitaxial layer are sequentially formed in the second trench 770 and the third through hole 760, and the three-layer structure is not distinguished in the figure , the distribution and material selection of the three-layer structure can refer to the first adhesion layer 210 , the first seed layer 220 and the first electroplating epitaxial layer 230 in FIG. 10 . performing planarization so that the surfaces of the third adhesion layer, the third seed layer, the third electroplating epitaxial layer and the insulating layer 400 are coplanar, and the inductor sub-conductor 100 is formed in the second trench 770 , forming the second auxiliary wire 300 in the third via hole 760 .

Referring to FIG. 18 , after forming the inductor sub-wire 100 and the second auxiliary wire 300 , it may further include: forming a fourth dielectric layer 640 on the surface of the insulating layer 400 and the inductor sub-wire 100 . The material of the fourth dielectric layer 640 may be the same as or different from that of the insulating layer 400 , for example, the material of the fourth dielectric layer 640 may include silicon oxide, silicon nitride, or silicon oxynitride.

The method for forming the inductance structure provided by the embodiment of the present application can be compatible with the existing interconnection process, and can form an inductance structure with strong electromigration resistance without increasing wire connections.

To sum up, after reading the content of this application, those skilled in the art can understand that the content of the foregoing application may be presented by way of example only, and may not be limiting. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to cover various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

It should be understood that the term "and/or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising", "comprising", "comprising" or "comprising", when used in this application document, indicate the presence of the described features, integers, steps, operations, elements and/or components, But it does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or their groups.

It will also be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference signs denote the same elements throughout the specification.

Furthermore, the present specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and/or plan views and/or perspective views. Accordingly, variations from the illustrated shapes as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Claims (17)

1. An inductor structure, comprising:

the inductor main body wires are spirally distributed and comprise a plurality of inductor sub-wires which are isolated by an insulating layer;

the first auxiliary wires are correspondingly arranged below the insulating layers between the adjacent inductor sub-wires;

a second auxiliary wire connecting adjacent ones of the inductor sub-wires and the corresponding ones of the first auxiliary wires;

wherein the inductor main body wire, the first auxiliary wire and the second auxiliary wire form a conductive path.

2. The inductor structure of claim 1, wherein the inductor sub-wires have a length of 40 μm to 70 μm and a total length of all inductor sub-wires is 3mm to 20mm.

3. The inductor structure of claim 1, wherein a difference in length of the insulating layer between the first auxiliary wire and the adjacent inductor sub-wire is 0.1 μm to 2 μm, and a difference in width between the first auxiliary wire and the inductor sub-wire is 0 μm to 10 μm.

4. The inductive structure of claim 1, further comprising: and the first dielectric layer is positioned between the adjacent first auxiliary wires and between the adjacent second auxiliary wires, wherein the bottom of the insulating layer is adjacent to the first dielectric layer, and the top of the insulating layer extends to the surface of the inductance sub-wire.

5. The inductive structure of claim 1, wherein a bottom of said insulating layer is contiguous with said first auxiliary conductor and a top of said insulating layer is coplanar with a surface of said inductive sub-conductor; the inductance structure further includes:

the second dielectric layer is positioned between the adjacent first auxiliary wires;

the third dielectric layer is positioned on the surface of the second dielectric layer and is adjacent to the second auxiliary wire and the inductance sub-wire;

and the fourth dielectric layer is positioned on the surfaces of the insulating layer and the inductance sub-conductor.

6. The inductor structure of claim 5, wherein the first auxiliary conductive line, the second auxiliary conductive line, and the inductor sub-conductive line each comprise an adhesion layer, a seed layer, and an electroplated epitaxial layer stacked in sequence.

7. The inductor structure of claim 1, wherein the inductor body conductive line is a top conductive line layer in an interconnect structure, the first auxiliary conductive line is a conductive line layer below the top conductive line layer, and the second auxiliary conductive line is a conductive line connection between the top conductive line layer and the conductive line layer.

8. A method for forming an inductor structure, comprising:

forming a discrete first auxiliary wire;

forming a first dielectric layer between adjacent first auxiliary wires and on the surface of the first auxiliary wires;

forming a second discrete auxiliary wire in the first dielectric layer on the surface of each first auxiliary wire, wherein the surfaces of the second auxiliary wire and the first dielectric layer are coplanar;

forming an inductance main body wire on the surface of the second auxiliary wire and part of the surface of the first dielectric layer, wherein the inductance main body wire comprises a plurality of inductance sub wires which are distributed at intervals;

forming an insulating layer between adjacent inductor sub-wires and on the surfaces of the inductor sub-wires;

and a first auxiliary wire is correspondingly arranged below the insulating layer between the adjacent inductor sub-wires, and the second auxiliary wire is connected with the adjacent inductor sub-wires and the corresponding first auxiliary wires to form a conductive path.

9. The method of forming an inductor structure of claim 8, wherein the method of forming the first auxiliary conductive line comprises:

forming a first auxiliary conductive material layer;

and etching part of the first auxiliary conducting wire material layer to form a plurality of first auxiliary conducting wires separated by the first openings.

10. The method of forming an inductor structure of claim 8, wherein the method of forming the second auxiliary conductive line comprises:

etching part of the first dielectric layer on the surface of each first auxiliary wire to form a second opening;

forming a second auxiliary conductive material layer in the second opening and on the surface of the first dielectric layer;

and flattening the second auxiliary conducting wire material layer to enable the surfaces of the second auxiliary conducting wire material layer and the first dielectric layer to be coplanar, and forming the second auxiliary conducting wire in the second opening.

11. The method of forming an inductor structure of claim 8, wherein the method of forming the inductor body conductive line comprises:

forming an inductance main body material layer on the surfaces of the second auxiliary wire and the first dielectric layer;

and etching part of the inductance main body conducting wire material layer on the surface of the first dielectric layer to form a plurality of inductance sub-wires separated by a third opening, wherein the second auxiliary wires are connected with the inductance sub-wires at two ends of the third opening and the corresponding first auxiliary wires.

12. The method of forming an inductor structure of claim 11, wherein the method of forming the insulating layer comprises:

forming an insulating material in the third opening and on the surface of the inductance main body wire;

and flattening the insulating material to a target thickness to form the insulating layer.

13. A method for forming an inductor structure, comprising:

forming a first separated auxiliary wire, wherein a second dielectric layer is arranged between the adjacent first auxiliary wires;

forming a third dielectric layer on the surfaces of the first auxiliary wire and the second dielectric layer;

forming a second auxiliary wire, an inductance main body wire and an insulating layer in the third dielectric layer;

the second auxiliary wires are located on part of the surface of the first auxiliary wires, the inductance main body wires are located on the surfaces of the second auxiliary wires and part of the third dielectric layer, the inductance main body wires comprise a plurality of inductance sub-wires separated by the insulating layer, the first auxiliary wires are correspondingly arranged below the insulating layer between the adjacent inductance sub-wires, and the second auxiliary wires are connected with the inductance sub-wires at two ends of the insulating layer and the corresponding first auxiliary wires to form a conductive path.

14. The method of forming an inductor structure of claim 13, wherein the forming the first auxiliary conductive line and the second dielectric layer comprises:

forming a second dielectric material layer;

etching the second dielectric material layer to form a fourth opening and a second dielectric layer;

sequentially forming a first adhesion layer, a first seed crystal layer and a first electroplating epitaxial layer in the fourth opening;

and flattening the surfaces of the first adhesion layer, the first seed crystal layer, the first electroplating epitaxial layer and the second dielectric layer to be coplanar, and forming the first auxiliary wire in the fourth opening.

15. The method of forming an inductor structure of claim 13, wherein the forming the second auxiliary conductive line, the inductor body conductive line, and the insulating layer comprises:

etching part of the third dielectric layer to form a first groove for defining the inductance main body wire;

etching part of the third dielectric layer at the bottom of the first groove to form an insulating layer and a first through hole for defining the second auxiliary wire;

sequentially forming a second adhesion layer, a second seed crystal layer and a second electroplating epitaxial layer in the first groove and the first through hole;

and flattening to enable the surfaces of the second adhesion layer, the second seed crystal layer, the second electroplating epitaxial layer and the insulating layer to be coplanar, forming the inductor conducting wire in the first groove, and forming the second auxiliary conducting wire in the first through hole.

16. The method of forming an inductor structure of claim 13, wherein the forming the second auxiliary conductive line, the inductor body conductive line, and the insulating layer comprises:

etching part of the third dielectric layer, stopping on part of the first auxiliary conducting wire, and forming a second through hole;

etching the third dielectric layer at one side of the second through hole to form an insulating layer, a third through hole for defining the second auxiliary wire and a second groove for defining the inductor sub-wire;

sequentially forming a third adhesion layer, a third seed crystal layer and a third electroplating epitaxial layer in the second groove and the third through hole;

and flattening to enable the surfaces of the third adhesion layer, the third seed crystal layer, the third electroplating epitaxial layer and the insulating layer to be coplanar, forming the inductor conducting wire in the second groove, and forming the second auxiliary conducting wire in the third through hole.

17. The method of forming an inductor structure of claim 13, further comprising: and forming a fourth dielectric layer on the surfaces of the insulating layer and the inductance sub-wires.

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