CN116111567A - Low-voltage ESD protection circuit - Google Patents

Abstract

The present invention provides a low-voltage ESD protection circuit, including: a buffer unit and a current discharge unit. The application introduces a buffer unit for controlling the shutdown or opening of the current discharge unit between VDD-GND. Normally, In the power and working state, the current discharge unit is in the off state and does not affect the normal operation of the protected circuit; when an ESD event occurs at the VDD terminal, the buffer unit provides a high potential for the current discharge unit, and the current discharge unit is turned on. To discharge the ESD current, the low-voltage ESD protection circuit has no capacitor and occupies a small chip area, so that the total area of the device is small. Furthermore, the low-voltage ESD protection circuit provided by this application is suitable for power ports with a gate oxide breakdown voltage greater than 6V such as 3.3V and 5V. Risk of false triggering.

Description

Low Voltage ESD Protection Circuit

technical field

The present application relates to the technical field of ESD protection, in particular to a low-voltage ESD protection circuit.

Background technique

RC (resistor and capacitor series structure) + inverter + Big-NMOS (large-size NMOS tube) is a common and efficient low-voltage ESD protection circuit. When an ESD event occurs at the VDD terminal, the ESD pulse signal will make the Big- The Gate terminal (gate) of the NMOS is at a high potential, so that the Big-NMOS is turned on, and the ESD current is discharged from the channel of the Big-NMOS. However, this circuit needs to consume a large chip area to design capacitance parameters, and there is a risk of false triggering in the case of fast power-on.

Contents of the invention

The present application provides a low-voltage ESD protection circuit, which can solve one of the problems that the current low-voltage ESD protection circuit needs to consume a large chip area to design capacitance parameters, and there is a risk of false triggering in the case of fast power-on.

On the one hand, an embodiment of the present application provides a low-voltage ESD protection circuit, including: a buffer unit and a current discharge unit, wherein,

The buffer unit is used to provide a low potential to the current discharge unit to control the shutdown of the current discharge unit, or provide a high potential to the current discharge unit to control the current discharge unit the opening;

The current discharge unit is used for discharging ESD current when turned on.

Optionally, in the low-voltage ESD protection circuit, the buffer unit includes: a Zener diode and a current limiting resistor, the anode of the Zener diode is connected to one end of the current limiting resistor, and the Zener diode The negative pole is connected to the external high potential, and the other end of the current limiting resistor is connected to the external low potential.

Optionally, in the low-voltage ESD protection circuit, the current discharge unit is a first NMOS transistor, the gate of the first NMOS transistor is connected to the anode of the Zener diode, and the first NMOS transistor The drain of the first NMOS transistor is connected to the cathode of the Zener diode, and the source of the first NMOS transistor is connected to the other end of the current limiting resistor.

Optionally, in the low-voltage ESD protection circuit, the difference between the external high potential and the external low potential is the ESD pulse voltage.

Optionally, in the low-voltage ESD protection circuit, the low-voltage ESD protection circuit further includes: an inverter, the inverter is arranged between the buffer unit and the current discharge unit for boosting The turn-on speed and turn-off speed of the current discharge unit.

Optionally, in the low-voltage ESD protection circuit, the buffer unit includes: a Zener diode and a current limiting resistor, the cathode of the Zener diode is connected to one end of the current limiting resistor, and the Zener diode The positive pole is connected to the external low potential, and the other end of the current limiting resistor is connected to the external high potential.

Optionally, in the low-voltage ESD protection circuit, the inverter includes: an upper MOS transistor and a lower MOS transistor, the gate of the upper MOS transistor is connected to the gate of the lower MOS transistor, and the upper MOS transistor is connected to the gate of the lower MOS transistor. The drain of the MOS transistor is connected to the drain of the lower MOS transistor, the source of the upper MOS transistor is connected to an external high potential, the source of the lower MOS transistor is connected to an external low potential, and the upper MOS transistor is connected to an external low potential. A connection node between the gate of the transistor and the gate of the lower MOS transistor is connected to the cathode of the Zener diode.

Optionally, in the low-voltage ESD protection circuit, the current discharge unit is a first NMOS transistor, and the gate of the first NMOS transistor is connected to the drain of the upper MOS transistor and the lower MOS transistor. The drain of the first NMOS transistor is connected to the source of the upper MOS transistor, and the source of the first NMOS transistor is connected to the source of the lower MOS transistor.

Optionally, in the low-voltage ESD protection circuit, the upper MOS transistor is a PMOS transistor, and the lower MOS transistor is a second NMOS transistor.

Optionally, in the low-voltage ESD protection circuit, the difference between the external high potential and the external low potential is the ESD pulse voltage.

The technical solution of the present application at least includes the following advantages:

The present invention provides a low-voltage ESD protection circuit, including: a buffer unit and a current discharge unit. This application introduces a buffer unit between VDD-GND for controlling the shutdown or opening of the current discharge unit. In the power-on and working state, the current discharge unit is in the off state and does not affect the normal operation of the protected circuit; when an ESD event occurs at the VDD terminal, the buffer unit provides a high potential to the current discharge unit, and the current discharge unit is turned on , to discharge the ESD current, the low-voltage ESD protection circuit has no capacitor, occupies a small chip area, and makes the total area of the device small.

Furthermore, the low-voltage ESD protection circuit provided by this application is suitable for power ports with a gate oxide breakdown voltage greater than 6V such as 3.3V and 5V. Risk of false triggering.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, the accompanying drawings in the following description The figures show some implementations of the present application, and those skilled in the art can obtain other figures based on these figures without any creative effort.

FIG. 1 is a schematic structural view of a low-voltage ESD protection circuit according to Embodiment 1 of the present invention;

2 is a schematic diagram of a TLP test curve of a low-voltage ESD protection circuit according to Embodiment 1 of the present invention;

3 is a schematic structural diagram of a low-voltage ESD protection circuit according to Embodiment 2 of the present invention;

4 is a schematic diagram of a TLP test curve of a low-voltage ESD protection circuit according to Embodiment 2 of the present invention;

Wherein, the reference signs are explained as follows:

11-buffer unit, 12-current discharge unit;

21-buffer unit, 22-current discharge unit, 23-inverter.

Detailed ways

The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplification of the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, or it may be the internal communication of two components, which may be wireless connection or wired connection connect. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below may be combined as long as they do not constitute a conflict with each other.

Embodiment one

An embodiment of the present application provides a low-voltage ESD protection circuit. Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a low-voltage ESD protection circuit according to Embodiment 1 of the present invention. The low-voltage ESD protection circuit includes: a buffer unit 11 and a current discharge unit 12, wherein, the buffer unit 11 is used to provide a low potential to the current discharge unit 12 to control the shutdown of the current discharge unit 12, or the buffer unit 11 is used to provide the current discharge unit 12 The discharge unit 12 provides a high potential to control the opening of the current discharge unit 12; the current discharge unit 12 is used to discharge the ESD current when it is turned on.

Further, the difference between the external high potential and the external low potential is the ESD pulse voltage.

In this embodiment, the external high potential is VDD, and the external low potential is GND (ground terminal).

Further, as shown in FIG. 1 , the buffer unit 11 includes: a Zener diode (Zener) and a current limiting resistor (R), the anode of the Zener diode is connected to one end of the current limiting resistor, and the Zener diode The cathode of the nanodiode is connected to the external high potential VDD, and the other end of the current limiting resistor is connected to the external low potential GND.

Preferably, the current discharge unit 12 is a first NMOS transistor, the gate of the first NMOS transistor is connected to the anode of the Zener diode, and the drain of the first NMOS transistor is connected to the anode of the Zener diode. The cathodes of the diodes are connected, and the source of the first NMOS transistor is connected to the other end of the current limiting resistor.

In this embodiment, the first NMOS transistor is a large-size NMOS transistor (Big-NMOS).

In this embodiment, a buffer unit 11 (a Zener diode and a current limiting resistor) for controlling the current drain unit 12 to be turned off or on is introduced between VDD-GND, and the gate of the first NMOS transistor The terminal (Gate terminal) is connected to the connection node between the Zener diode and the current limiting resistor. Referring to FIG. 2, FIG. 2 is a schematic diagram of a TLP (Transmission Line Pulse, transmission line pulse) test curve of a low-voltage ESD protection circuit according to Embodiment 1 of the present invention. Under normal power-on and normal working conditions, the first NMOS transistor is in an off state, which does not affect the normal operation of the protected circuit. When an ESD event occurs at the VDD terminal, if the ESD pulse voltage is less than the breakdown voltage of the Zener diode (about 6V), the low-voltage ESD protection circuit will not respond; when the ESD pulse voltage is greater than the breakdown voltage of the Zener diode, the The gate of the first NMOS transistor is at a high potential, and the channel of the first NMOS transistor is turned on to discharge the ESD current.

The low-voltage ESD protection circuit is suitable for 3.3V, 5V and other power ports whose gate oxide breakdown voltage is greater than 6V.

In this embodiment, the low-voltage ESD protection circuit has no capacitor and occupies a small chip area, making the total area of the device small; the turn-on voltage of the circuit is about 6V greater than the working voltage, which avoids the risk of false triggering caused by rapid power-on.

Embodiment two

The embodiment of the present application provides a low-voltage ESD protection circuit. Referring to FIG. 3, FIG. 3 is a schematic structural diagram of a low-voltage ESD protection circuit according to Embodiment 2 of the present invention. The low-voltage ESD protection circuit includes: a buffer unit 21, a current discharge unit 22 and an inverter 23, wherein the buffer unit 21 is used to provide a low potential to the current discharge unit 22 to control the shutdown of the current discharge unit 22, or to provide the current discharge unit 22 provides a high potential to control the opening of the current discharge unit 22; the current discharge unit 22 is used to discharge the ESD current when it is turned on; the inverter 23 is located between the buffer unit 21 and the Between the current discharge unit 22, it is used to increase the turn-on speed and the turn-off speed of the current discharge unit 22, and the inverter 23 can increase the driving capability of the circuit, so that the current discharge unit 22 can be turned on more fully.

Further, the difference between the external high potential and the external low potential is the ESD pulse voltage.

In this embodiment, the external high potential is VDD, and the external low potential is GND (ground terminal).

Further, the buffer unit 21 includes: a Zener diode (Zener) and a current limiting resistor (R), the cathode of the Zener diode is connected to one end of the current limiting resistor, and the anode of the Zener diode is connected to an external The low potential GND is connected, and the other end of the current limiting resistor is connected to the external high potential VDD.

Preferably, the inverter 23 includes: an upper MOS transistor and a lower MOS transistor, the gate of the upper MOS transistor is connected to the gate of the lower MOS transistor, and the drain of the upper MOS transistor is connected to the lower MOS transistor. The drains of the MOS transistors are connected, the source of the upper MOS transistor is connected to an external high potential, the source of the lower MOS transistor is connected to an external low potential, the gate of the upper MOS transistor is connected to the lower MOS The junction node of the gate of the tube is connected to the cathode of the Zener diode.

Preferably, the current discharge unit 22 is a first NMOS transistor, the gate of the first NMOS transistor is connected to the connection node between the drain of the upper MOS transistor and the drain of the lower MOS transistor, so The drain of the first NMOS transistor is connected to the source of the upper MOS transistor, and the source of the first NMOS transistor is connected to the source of the lower MOS transistor.

In this embodiment, the first NMOS transistor is a large-size NMOS transistor (Big-NMOS).

Further, the upper MOS transistor is a PMOS transistor, and the lower MOS transistor is a second NMOS transistor.

In this embodiment, the introduction of an inverter 23 between the buffer unit 21 and the current discharge unit 22 can make the current discharge unit 22 (the first NMOS transistor, Big-NMOS) turn on more fully, refer to FIG. 4. FIG. 4 is a schematic diagram of the TLP test curve of the low-voltage ESD protection circuit of the second embodiment of the present invention. Under normal power-on or normal working conditions, the connection between the grid of the upper MOS transistor and the grid of the lower MOS transistor The node (A terminal) and VDD are at the same potential, and the second NMOS transistor in the inverter 23 is turned on, so the gate of the first NMOS transistor, that is, the G terminal, is at the same potential as GND, so the first NMOS transistor is turned off. state; when the ESD pulse voltage exceeds the breakdown voltage of the Zener diode, the PMOS transistor in the inverter 23 is turned on, so that the G end and the VDD end are in an equipotential state, and at this moment, the first NMOS transistor is turned on, and the channel is used to discharge ESD current.

The low-voltage ESD protection circuit is suitable for 3.3V, 5V and other power ports whose gate oxide breakdown voltage is greater than 6V.

In this embodiment, the low-voltage ESD protection circuit has no capacitor and consumes a small area, so that the total area of the device is small; the turn-on voltage of the circuit is about 6V greater than the working voltage, which avoids the risk of false triggering caused by rapid power-on.

Apparently, the above-mentioned embodiments are only examples for clear description, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. However, the obvious changes or changes derived therefrom are still within the protection scope of the invention of the present application.

Claims (10)

1. A low voltage ESD protection circuit comprising: a buffer unit and a current discharge unit, wherein,

the buffer unit is used for providing a low potential for the current discharge unit to control the turn-off of the current discharge unit, or providing a high potential for the current discharge unit to control the turn-on of the current discharge unit;

the current bleed unit is configured to bleed ESD current when turned on.

2. The low voltage ESD protection circuit of claim 1, wherein the buffer unit comprises: the positive pole of the zener diode is connected with one end of the current limiting resistor, the negative pole of the zener diode is connected with external high potential, and the other end of the current limiting resistor is connected with external low potential.

3. The low voltage ESD protection circuit of claim 2 wherein the current bleed unit is a first NMOS transistor having a gate connected to the positive terminal of the zener diode, a drain connected to the negative terminal of the zener diode, and a source connected to the other terminal of the current limiting resistor.

4. The low voltage ESD protection circuit of claim 2 wherein the difference between the external high potential and the external low potential is an ESD pulse voltage.

5. The low-voltage ESD protection circuit of claim 1, further comprising: and the inverter is arranged between the buffer unit and the current discharge unit and is used for improving the opening speed and the closing speed of the current discharge unit.

6. The low voltage ESD protection circuit of claim 5, wherein the buffer unit comprises: the negative pole of the zener diode is connected with one end of the current limiting resistor, the positive pole of the zener diode is connected with external low potential, and the other end of the current limiting resistor is connected with external high potential.

7. The low voltage ESD protection circuit of claim 6 wherein the inverter comprises: the MOS transistor comprises an upper MOS transistor and a lower MOS transistor, wherein a grid electrode of the upper MOS transistor is connected with a grid electrode of the lower MOS transistor, a drain electrode of the upper MOS transistor is connected with a drain electrode of the lower MOS transistor, a source electrode of the upper MOS transistor is connected with an external high potential, a source electrode of the lower MOS transistor is connected with an external low potential, and a connection node of the grid electrode of the upper MOS transistor and the grid electrode of the lower MOS transistor is connected to a cathode of the zener diode.

8. The low voltage ESD protection circuit of claim 7 wherein the current bleed unit is a first NMOS transistor having a gate connected to a connection node between the drain of the upper MOS transistor and the drain of the lower MOS transistor, the drain of the first NMOS transistor being connected to the source of the upper MOS transistor, the source of the first NMOS transistor being connected to the source of the lower MOS transistor.

9. The low voltage ESD protection circuit of claim 7 wherein the upper MOS transistor is a PMOS transistor and the lower MOS transistor is a second NMOS transistor.

10. The low voltage ESD protection circuit of claim 6 wherein the difference between the external high potential and the external low potential is an ESD pulse voltage.

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