CN116031168A - A kind of chip package structure and preparation method thereof - Google Patents

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, which belong to the technical field of chip packaging. The method includes: packaging a first chip; manufacturing a first rewiring component; packaging a second chip, the first surface electrode of the second chip and the first surface electrode The electrodes on the first surface of a chip are connected through the first redistribution component; the second redistribution component is produced, and the second surface electrode of the first chip or the second surface electrode of the second chip is connected to the pad through the second redistribution component; A third redistribution component is manufactured, and the electrodes on the first surface of the first chip and the electrodes on the first surface of the second chip are connected to the pads via the first redistribution component and the third redistribution component. The method of the present invention can realize the interconnection packaging of at least two chips without the help of a lead frame, which greatly reduces the volume of the packaging structure; the same electrodes of the two chips arranged in stacks are connected to the pads after being connected by rewiring components. Redistribution components realize chip electrode interconnection and can reduce package parasitic resistance.

Description

A kind of chip package structure and preparation method thereof

technical field

The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a preparation method thereof.

Background technique

The traditional two-chip package structure is a planar structure. Generally, two chips are placed in parallel on the lead frame, and the electrical signal interconnection between the chips is realized through the lead frame (the front side of the chip is connected to the pin of the lead frame by wire bonding), and then The interconnection between chips is realized by wire bonding. The final product formed by the above packaging structure generally cannot be very thin (including the thickness of the lead frame), and the size of the packaging structure is large.

In order to further reduce the packaging volume of the chip and increase the power density of the product, the existing technology proposes a stacked chip packaging structure based on a lead frame design, that is, chip 1 and chip 2 are stacked and packaged. This packaging structure reduces the power consumption to a certain extent The structural volume of the package improves the integration level, but it still needs the help of a lead frame, and the performance of reducing the package volume is very limited.

Contents of the invention

The object of the present invention is to overcome the problems of the prior art, and provide a chip packaging structure and a preparation method thereof.

The purpose of the present invention is achieved by the following technical solutions: a method for preparing a chip packaging structure, which includes:

Encapsulating the first chip to obtain the first plastic sealing layer;

making a first redistribution component, the first redistribution component is connected to the electrode on the first surface of the first chip;

Encapsulating the second chip to obtain a second plastic sealing layer stacked on the first plastic sealing layer, the first surface electrode of the second chip is connected to the first surface electrode of the first chip through the first rewiring member; the first surface electrode of the first chip The surface electrode and the first surface electrode of the second chip are the same electrode;

Making the second redistribution component, the second surface electrode of the first chip or the second surface electrode of the second chip is connected to the pad through the second redistribution component; when the second surface electrode of the first chip is connected to the pad through the second redistribution component When connecting to the pad, the second surface electrode of the second chip is connected to the pad; disk connection;

A third redistribution component is fabricated, and the electrodes on the first surface of the first chip and the electrodes on the first surface of the second chip are connected to the pads via the first redistribution component and the third redistribution component.

In an example, when the first chip and the second chip are arranged in the same direction, the method includes the following steps:

Paste the first chip on the carrier board, plastic-encapsulate the first chip to obtain a first plastic packaging layer, make a first wiring layer on the first plastic packaging layer, and make a third plastic packaging layer on the first wiring layer;

Making the second wiring layer after removing the carrier plate, and depositing the first dielectric layer;

Making a third inner wiring layer in the first dielectric layer, connecting the third inner wiring layer to the second wiring layer, and making a third outer wiring layer penetrating through the first plastic encapsulation layer and the first dielectric layer;

Fabricating a fourth wiring layer on the first dielectric layer, the fourth wiring layer is connected to the third outer wiring layer, the first wiring layer, the third outer wiring layer, and the fourth wiring layer form a first rewiring component;

Paste the second chip on the fourth wiring layer, connect the electrodes on the first surface of the second chip to the fourth wiring layer, and plastic-encapsulate the second chip to obtain a second plastic-encapsulation layer;

Fabricate the fifth inner wiring layer and the fifth outer wiring layer that pass through the second plastic encapsulation layer, the fifth inner wiring layer is connected to the third inner wiring layer, the second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer are formed The second redistribution component; the fifth outer wiring layer is the third redistribution component, which is connected to the third outer wiring layer;

Welding pads are made on the second plastic encapsulation layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the electrodes on the second surface of the second chip are connected to the welding pads.

In an example, the second chip is plastic-encapsulated to obtain the second plastic-encapsulation layer is replaced by:

The fourth wiring layer and the second chip are plastic-encapsulated to obtain a second plastic-encapsulation layer.

In an example, before making the pads on the second plastic encapsulation layer, it also includes:

making a second dielectric layer on the second plastic sealing layer;

Opening holes in the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are exposed to obtain a number of through holes;

Fill the pin metal in the via hole;

Making pads on the second dielectric layer, so that the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are connected to the pads through lead metal.

In an example, when the first chip and the second chip are reversed, the method includes the following steps:

Pasting the first chip on the carrier plate, plastic sealing the first chip to obtain a first plastic sealing layer, and slotting the first plastic sealing layer to expose the electrodes on the first surface of the first chip;

making a first wiring metal layer in the groove, and the first wiring metal layer is a first redistribution component;

Fabricating a second chip on the first wiring metal layer, so that the first wiring metal layer is connected to the first surface electrode of the second chip;

Carry out plastic sealing to the second chip to obtain the second plastic sealing layer, and make the second wiring metal layer on the second plastic sealing layer, make the first surface electrode of the second chip connect with the second wiring metal layer, then make the fourth plastic sealing layer and then Remove the carrier plate;

Turn over the current packaging structure, make a third wiring metal layer that runs through the first plastic packaging layer and the second plastic packaging layer, so that the third wiring metal layer is connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form the third wiring metal layer. Double wiring parts;

Making a fourth wiring metal layer in the first plastic encapsulation layer, so that the fourth wiring metal layer is connected to the first wiring metal layer, and the fourth wiring metal layer is a third rewiring component;

A third dielectric layer is fabricated on the first plastic packaging layer, and pads are fabricated on the third dielectric layer, and the third wiring metal layer, the fourth wiring metal layer, and the electrodes on the second surface of the first chip are connected to the pads.

In an example, the third wiring metal layer includes interconnected third wiring metal sublayer A and third wiring metal sublayer B, the third wiring metal sublayer A penetrates the second plastic encapsulation layer, and the third wiring metal sublayer B penetrates through the first plastic sealing layer.

In an example, the second chip is plastic-encapsulated to obtain the second plastic-encapsulation layer is replaced by:

The second chip and the first wiring metal layer are plastic-encapsulated to obtain the second plastic-encapsulation layer.

In an example, the making the pad on the third dielectric layer further includes:

making a third dielectric layer on the first plastic sealing layer;

Opening holes in the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed to obtain a number of through holes;

Fill the pin metal in the via hole;

A pad is made on the third dielectric layer, so that the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are connected to the pad through the pin metal.

It should be further explained that the technical features corresponding to the examples of the above method can be combined or replaced to form a new technical solution.

The present invention also includes a chip packaging structure, including a packaging substructure, the packaging substructure is obtained according to the preparation method formed by any one of the above-mentioned examples or multiple examples, and includes a first plastic sealing layer and a second plastic sealing layer that are stacked. , the first chip is packaged in the first plastic sealing layer, and the second chip is packaged in the second plastic sealing layer;

The second surface electrode of the first chip or the second surface electrode of the second chip is connected to the pad through the second redistribution component; when the second surface electrode of the first chip is connected to the pad through the second redistribution component, the first The electrodes on the second surface of the second chip are connected to the pads; when the electrodes on the second surface of the second chip are connected to the pads through the second rewiring element, the electrodes on the second surface of the first chip are connected to the pads;

The first surface electrode of the first chip and the first surface electrode of the second chip are connected to the pad through the first redistribution component and the third redistribution component.

In an example, the packaging structure includes several packaging substructures, and the packaging substructures are spliced horizontally to form a multi-chip packaging structure.

Compared with prior art, the beneficial effect of the present invention is:

The method of the present invention can realize the interconnection packaging of at least two chips without the help of a lead frame. On the one hand, it breaks through the limitation of the area of the lead frame on the number of chip interconnections, and on the other hand, it greatly reduces the volume of the packaging structure; The same electrodes (such as the back electrodes) of the two chips are connected to the pads after being connected by rewiring components, that is, the chip electrodes are interconnected through rewiring components, which can reduce the parasitic resistance of the package; further, the other electrodes of the two chips are also connected through The lead-out of the rewiring component is connected to the pad, and there is no need for additional lead-in wires to bond the chip, which reduces the parasitic resistance of the chip interconnection.

Description of drawings

The specific embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings. The accompanying drawings described here are used to provide a further understanding of the application and constitute a part of the application. In these drawings, the same reference numerals are used to indicate the same or similar parts, the exemplary embodiments of the application and their descriptions are used to explain the application, and do not constitute an undue limitation to the application.

Fig. 1 is a flow chart of the method in an example of the present invention;

Fig. 2 is a schematic diagram of the package substructure prepared in step S1" of the first preferred example of the present invention;

Fig. 3 is a schematic diagram of the package substructure prepared in step S2" of the first preferred example of the present invention;

Fig. 4 is a schematic diagram of the package substructure prepared in step S3" of the first preferred example of the present invention;

Fig. 5 is a schematic diagram of the package substructure prepared in step S4" of the first preferred example of the present invention;

Fig. 6 is a schematic diagram of the package substructure prepared in step S5" of the first preferred example of the present invention;

Fig. 7 is a top view of the package substructure prepared in step S5" of the first preferred example of the present invention;

Fig. 8 is a schematic diagram of the package substructure prepared in step S6" of the first preferred example of the present invention;

Fig. 9 is a schematic diagram of the substructure of the package prepared in step S7" of the first preferred example of the present invention;

Fig. 10 is a schematic diagram of the package substructure prepared in step S8" of the first preferred example of the present invention;

Fig. 11 is a schematic diagram of the substructure of the package prepared in step S9" of the first preferred example of the present invention;

Fig. 12 is a schematic diagram of the substructure of the package prepared in step S10" of the first preferred example of the present invention;

Fig. 13 is a flow chart of the method in another example of the present invention;

Fig. 14 is a schematic diagram of the substructure of the package prepared in step S1"' of the second preferred example of the present invention;

Fig. 15 is a schematic diagram of the substructure of the package prepared in step S2"' of the second preferred example of the present invention;

Fig. 16 is a schematic diagram of the substructure of the package prepared in step S3"' of the second preferred example of the present invention;

Fig. 17 is a schematic diagram of the substructure of the package prepared in step S4"' of the second preferred example of the present invention;

Fig. 18 is a schematic diagram of the structure of the package prepared in step S5"' of the second preferred example of the present invention;

Fig. 19 is a schematic diagram of the substructure of the package prepared in step S6"' of the second preferred example of the present invention;

Fig. 20 is a schematic diagram of the structure of the package prepared in step S7"' of the second preferred example of the present invention;

Fig. 21 is a schematic diagram of the structure of the package prepared in step S8"' of the second preferred example of the present invention;

Fig. 22 is a schematic diagram of the structure of the package prepared in step S9"' of the second preferred example of the present invention;

Fig. 23 is a schematic diagram of the substructure of the package prepared in step S10"' of the second preferred example of the present invention;

Fig. 24 is a schematic diagram of the package substructure prepared in step S11"' of the second preferred example of the present invention.

In the figure: 1-first chip; 2-second chip; 3-carrier; 4a-first plastic sealing layer; 4b-second plastic sealing layer; 4c-third plastic sealing layer; 4d-fourth plastic sealing layer; 5- 1st wiring layer; 6-second wiring layer; 7a-first dielectric layer; 7b-second dielectric layer; 8a-third inner rewiring layer; 8b-third outer rewiring layer; 9-fourth wiring layer ; 10a-fifth inner redistribution layer; 10b-fifth outer redistribution layer; 11-pad; 12-pin metal; 13-front electrode; 14-first inner blind hole; 15-first outer through hole 16-the second inner via hole; 17-the second outer via hole; 18-the first wiring metal layer; 19-the second wiring metal layer; 20-the third wiring metal layer; 21-the fourth wiring metal layer; 22 - fifth wiring metal layer; 23a - fourth dielectric layer; 23b - fifth dielectric layer; 24 - fourth blind hole; 25 - fifth through hole; 26 - seventh through hole; 27 - eighth through hole.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms belonging to "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated direction or positional relationship is based on the direction or positional relationship described in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, or in a specific orientation. construction and operation, therefore, should not be construed as limiting the invention. Furthermore, the use of ordinal numbers (eg, "first and second," "first to fourth," etc.) is for the purpose of distinguishing objects, is not limited to that order, and should not be construed to indicate or imply relative importance.

In the description of the present invention, it should be noted that, unless otherwise specified and limited, "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as there is no conflict with each other.

In an example, a method for preparing a chip packaging structure of the present invention specifically includes the following steps:

Encapsulating the first chip to obtain the first plastic sealing layer;

making a first redistribution component, the first redistribution component is connected to the electrode on the first surface of the first chip;

Encapsulating the second chip to obtain a second plastic sealing layer stacked on the first plastic sealing layer, the first surface electrode of the second chip is connected to the first surface electrode of the first chip through the first rewiring member; the first surface electrode of the first chip The surface electrode and the first surface electrode of the second chip are the same electrode, that is, both represent the front electrode or the back electrode of the chip. In the embodiment of the present invention, the first surface electrode is the back electrode, and the second surface electrode is the front electrode;

Making the second redistribution component, the second surface electrode of the first chip or the second surface electrode of the second chip is connected to the pad through the second redistribution component; when the second surface electrode of the first chip is connected to the pad through the second redistribution component When connecting to the pad, the second surface electrode of the second chip is connected to the pad; disk connection;

A third redistribution component is fabricated, and the electrodes on the first surface of the first chip and the electrodes on the first surface of the second chip are connected to the pads via the first redistribution component and the third redistribution component.

It should be noted that in this example, the steps do not need to be performed in the order described above. In order to ensure the production efficiency and reduce the difficulty of process manufacturing, some steps can be performed at the same time (such as part of the redistribution layer in the first redistribution component, the second Part of the redistribution layer in the second redistribution component can be fabricated simultaneously), or the steps can be reversed (for example, part of the redistribution layer in the second redistribution component can be fabricated first, and then the second chip can be packaged).

Specifically, the material of the plastic sealing layer is preferably epoxy resin, which has the characteristics of light weight, high strength, good corrosion resistance, excellent electrical properties, shock absorption, etc., and can better meet the requirements of chip packaging.

Further, the redistribution component is a single-layer redistribution layer RDL, or is formed by interconnecting multiple redistribution layers; the redistribution layer is used to change the position of the originally designed chip circuit contacts through the wafer-level metal wiring process and the bump process. The location of the circuit contacts, so that the chip can be applied to different packaging forms.

Further, when the first chip and the second chip are arranged in the same direction, that is, the orientation of the first chip and the second chip are consistent, in this example, the first chip and the second chip are both facing upward, and at this time the first redistribution component It includes a horizontal redistribution layer connected to the back electrode of the first chip and the back electrode of the second chip, and a vertical redistribution layer connecting the two horizontal redistribution layers and penetrating the first plastic encapsulation layer; as an option, the vertical The redistribution layer can be a "mouth" shaped redistribution assembly with a certain thickness (equal to the thickness of the first plastic encapsulation layer), including horizontal wiring elements and vertical wiring elements; the horizontal rewiring layer connected to the back electrode of the second chip is After extending in the vertical direction, it is connected with the horizontal wiring elements, so as to realize the interconnection of the back electrodes of the first chip and the second chip; more preferably, in order to improve the production efficiency, the horizontal wiring elements in the "口"-shaped rewiring assembly can be based on A gap is reserved for the width of the horizontal redistribution layer connected to the back electrode of the second chip.

Further, when the first chip and the second chip are arranged in the same direction, the second redistribution component includes a horizontal wiring layer connected to the front electrode of the first chip, and a vertical wiring layer connected to the horizontal wiring layer; the third redistribution component It is preferably a single-layer vertical redistribution layer, and it only needs to be connected to any wiring layer in the first redistribution layer.

Further, when the first chip and the second chip are arranged in reverse, that is, one chip faces up and the other chip faces up, at this time, the first redistribution component is preferably a single-layer redistribution layer, directly realizing the first The back electrodes of the chip and the second chip are interconnected, of course, a multi-layer redistribution layer can also be selected, and the back electrodes of the first chip and the second chip are interconnected through the multi-layer redistribution layer. The second redistribution component preferably includes an interconnected horizontal redistribution layer and a vertical redistribution layer, the horizontal redistribution layer is connected to the front electrode of the second chip, and finally the front electrode of the second chip is drawn out through the vertical redistribution layer; optionally, The vertical redistribution layer may be a vertical redistribution sub-layer of multilayer interconnection. The third redistribution component is a vertical redistribution layer penetrating through the first plastic encapsulation layer, and is connected to the first redistribution component.

In one example, when the first chip and the second chip are arranged in the same direction, as shown in Figure 1, the method for preparing the packaging structure includes the following steps:

S1: Paste the second side of the first chip on the carrier board, and plastic seal the first chip to obtain the first plastic sealing layer; wherein, the carrier board 1 includes but not limited to steel plate, glass plate, etc.; Adhesive is used to paste the first chip on the carrier board. Preferably, the first wiring layer is fabricated after grinding the first plastic encapsulation layer to expose the chip electrodes.

S2: Make the first wiring layer on the first plastic packaging layer, the first wiring layer is interconnected with the back of the first chip, make the second wiring layer after removing the carrier board, and deposit the first dielectric layer; in this step, directly remove the temporary The bonding adhesive is then removed from the carrier, such as by heating to remove the bonding adhesive. Preferably, after the first wiring layer is fabricated, a third plastic encapsulation layer is fabricated on the first wiring layer, and the first wiring layer is buried inside the plastic encapsulation layer.

S3: Fabricate a third inner wiring layer in the first dielectric layer, connect the third inner wiring layer to the second wiring layer, and fabricate a third outer wiring layer passing through the first plastic encapsulation layer and the first dielectric layer;

S4: Fabricate a fourth wiring layer on the first dielectric layer, the fourth wiring layer is connected to the third outer wiring layer, and the first wiring layer, the third outer wiring layer, and the fourth wiring layer form a first rewiring component;

S5: Paste the second chip on the fourth wiring layer, connect the electrodes on the first surface of the second chip to the fourth wiring layer, and plastic-encapsulate the second chip to obtain a second plastic-encapsulation layer;

S6: Fabricate the fifth inner wiring layer and the fifth outer wiring layer passing through the second plastic encapsulation layer, the fifth inner wiring layer is connected to the third inner wiring layer, the second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer The layer forms the second redistribution component; the fifth outer wiring layer is the third redistribution component, which is connected to the third outer wiring layer;

S7: making pads on the second plastic encapsulation layer, and connecting the fifth inner wiring layer, the fifth outer wiring layer, and the electrodes on the second surface of the second chip to the pads.

In this example, the thicknesses of the third inner redistribution layer, the third outer redistribution layer, the fifth inner redistribution layer, and the fifth outer redistribution layer are all less than or equal to the thickness of the plastic encapsulation layer and less than the total height of the two chips, which reduces the penetration It is difficult to make the hole metal wiring process.

As an option, when the first chip and the second chip are arranged in the same direction, the method for preparing the packaging structure may further include the following steps:

S1': paste the first surface of the first chip on the carrier board, and plastic seal the first chip to obtain the first plastic sealing layer;

S2': depositing the first dielectric layer;

S3': making a third outer wiring layer that penetrates the first plastic encapsulation layer and the first dielectric layer;

S4': making a fourth wiring layer on the first dielectric layer, the fourth wiring layer is connected to the third outer wiring layer,

S5': Remove the carrier board, turn over the current packaging structure, prepare the first wiring layer on the first plastic packaging layer, the first wiring layer is connected to the third outer wiring layer, the first wiring layer, the third outer wiring layer, and the fourth wiring layer The layer constitutes the first redistribution component;

S6': Paste the second chip on the fourth wiring layer, connect the electrodes on the first surface of the second chip to the fourth wiring layer, and plastic-encapsulate the second chip to obtain the second plastic packaging layer, and the second plastic packaging layer is smaller than the first plastic packaging layer a plastic sealing layer to expose the outside of the second dielectric layer;

S7': making a second wiring layer in the first dielectric layer, at this time, the second chip is not aligned with the first chip, and the position corresponding to the front electrode of the first dielectric layer and the first chip is not blocked by the second plastic sealing layer;

S8': Make a third inner wiring layer in the first dielectric layer (not blocked by the second plastic sealing layer), so that the third inner wiring layer is connected to the second wiring layer;

S9': Fabricate the fifth inner wiring layer passing through the second plastic encapsulation layer, the fifth inner wiring layer is connected to the third inner wiring layer, the second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer form the second rewiring layer Wiring parts;

S10': making a fifth outer wiring layer that passes through the second plastic encapsulation layer, the fifth outer wiring layer is a third rewiring component, and is connected to the third outer wiring layer;

S11': Make pads on the second plastic encapsulation layer, and connect the fifth inner wiring layer, the fifth outer wiring layer, and the electrodes on the second surface of the second chip to the pads.

In an example, when making the third inner redistribution layer, the following sub-steps are included:

S31: Open holes in the first dielectric layer until the second wiring layer is exposed to obtain the first inner blind holes; in the present invention, laser technology can be used for opening holes, and of course it can also be realized by etching.

S32: Fabricate a third inner redistribution layer in the first inner blind hole, that is, fill the first inner blind hole with a metal layer as the third inner redistribution layer, and connect the third inner redistribution layer to the second wiring layer.

In an example, when making the third outer redistribution layer, it includes:

S33: Making a first outer through hole penetrating through the first plastic encapsulation layer and the first dielectric layer, so as to expose the first wiring layer;

S34: Fabricate a third outer redistribution layer in the first outer via hole, that is, fill the first outer via hole with a metal layer as the third outer redistribution layer, and connect the third outer redistribution layer to the first wiring layer.

In an example, when making the fifth inner redistribution layer, it includes:

S61: making holes in the second plastic sealing layer until the third inner redistribution layer is exposed, so as to obtain the second inner through hole;

S62: Fabricate the fifth inner redistribution layer in the second inner via hole, that is, fill the metal layer in the second inner via hole as the fifth inner redistribution layer, and make the fifth inner redistribution layer and the third inner redistribution layer connect.

In an example, when making the fifth outer redistribution layer, it includes:

S63: making holes on the second plastic encapsulation layer until the third outer redistribution layer is exposed, so as to obtain the second outer through hole;

S64: Fabricate the fifth outer redistribution layer in the second outer via hole, that is, fill the second outer via hole with a metal layer as the fifth outer redistribution layer, so that the fifth outer redistribution layer and the third outer redistribution layer connect.

In an example, when fabricating the third inner redistribution layer in the first inner blind hole or the third outer redistribution layer in the first outer via hole, the following sub-steps are included:

Sputtering a first seed layer on the surface of the current packaging structure, preferably a first seed layer made of Ti/Cu material;

Masking the first seed layer by using the first photoresist to expose the first seed layer corresponding to the position of the first inner blind hole or the first outer through hole;

Perform electroplating treatment on the first seed layer corresponding to the position of the first inner blind hole or the first outer through hole, preferably electroplating Cu;

removing the first photoresist and the redundant first seed layer outside the position of the first inner blind hole or the first outer through hole to obtain a third inner redistribution layer connected to the second wiring layer, or to obtain a third inner redistribution layer that penetrates the first plastic encapsulation layer, The third outer redistribution layer of the first dielectric layer; where the first photoresist is preferably removed by wet etching.

When fabricating the fifth inner redistribution layer in the second inner via hole or the fifth outer redistribution layer in the second outer via hole, the following sub-steps are included:

sputtering a second seed layer on the surface of the current packaging structure, preferably a second seed layer made of Ti/Cu;

Masking the second seed layer by using the second photoresist to expose the second seed layer corresponding to the position of the second inner through hole or the second outer through hole;

Electroplating treatment is performed on the second seed layer corresponding to the position of the second inner through hole or the second outer through hole, preferably electroplating Cu;

removing the second photoresist and the redundant second seed layer outside the position of the second inner through hole or the second outer through hole to obtain a fifth inner redistribution layer or a fifth outer redistribution layer that penetrates the second plastic encapsulation layer; wherein, The second photoresist is preferably removed by wet etching.

In an example, the second chip is plastic-encapsulated so that the second plastic-encapsulation layer is replaced by:

The fourth wiring layer and the second chip are plastic-encapsulated to obtain the second plastic-encapsulation layer, thereby reducing the volume of the entire packaging structure and improving the reliability of the packaging structure.

In one example, the second dielectric layer is fabricated on the second plastic encapsulation layer, that is, the second dielectric layer is located between the second plastic encapsulation layer and the pad, and the pad is fabricated on the second dielectric layer at this time. Wherein, the second dielectric layer is any one of epoxy resin, PBO, Al ₂ O ₃ , SiO ₂ , and SiNx.

Further, before making pads on the second plastic encapsulation layer, it also includes:

Opening holes in the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are exposed;

The pin metal is filled in the third through hole, and the pin metal is a (alloy) metal block formed by any material of Au, Ti, Al, Ni, Cu or a combination of multiple materials.

Making pads on the second dielectric layer, so that the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are connected to the pads through lead metal.

Combining the above examples, when the first chip and the second chip are arranged in the same direction, the first preferred example of the preparation method of the packaging (sub)structure includes the following steps:

S1": as shown in Figure 2, paste the front of the first chip 1 on the carrier board 3, and plastic-encapsulate the first chip 1 to obtain the first plastic packaging layer 4a, and then make the first wiring layer on the first plastic packaging layer 4a 5, and make the third plastic encapsulation layer 4c above the first wiring layer 5; wherein, the front side of the chip is etched with one side of the circuit pattern, and the other side is the back side of the chip; further, the first chip 1 can be bonded by temporary bonding glue Paste on carrier board 3.

S2": As shown in FIG. 3, the second wiring layer 6 is made after removing the carrier 3, and the first dielectric layer 7a is deposited; in this step, the carrier 3 is removed directly by removing the temporary bonding glue.

S3": as shown in Fig. 4, open a hole on the first dielectric layer 7a (corresponding to the second wiring layer 6) until the second wiring layer 6 is exposed to obtain the first inner blind hole 14; at the same time, the first plastic sealing layer 4a, the first dielectric layer 7a is opened to expose the first wiring layer 5, and the first outer through hole 15 penetrating through the first plastic packaging layer 4a and the first dielectric layer 7a is obtained;

S4": As shown in Figure 5, make the third inner redistribution layer 8a in the first inner blind hole 14, so that the third inner wiring layer is connected to the second wiring layer 6; at the same time, in the first outer through hole 15 Making a third outer redistribution layer 8b, and then connecting the third outer redistribution layer 8b to the first wiring layer 5;

S5": as shown in Figure 6, the fourth wiring layer 9 is fabricated on the first dielectric layer 7a, and the fourth wiring layer 9 is interconnected with the third outer rewiring layer 8b in the shape of "口", as shown in Figure 7;

S6": As shown in Figure 8, paste the second chip 2 on the fourth wiring layer 9, so that the back electrode of the second chip 2 is connected to the fourth wiring layer 9, and connect the second chip 2 and the fourth wiring layer 9 Perform plastic sealing to obtain the second plastic sealing layer 4b;

S7": As shown in Figure 9, holes are opened on the second plastic sealing layer 4b (corresponding to the third inner wiring layer and the third outer wiring layer) until the third inner wiring layer and the third outer wiring layer are exposed, and the same as the first wiring layer is obtained. The second inner through hole 16 corresponding to the three inner wiring layers, and the second outer through hole 17 corresponding to the third outer wiring layer;

S8 ": As shown in Figure 10, make the fifth inner redistribution layer 10a in the second inner via hole 16, so that the fifth inner wiring layer is connected to the third inner wiring layer, at this time, the fifth inner wiring layer is connected to the third inner wiring layer. The front electrode 13 (top electrode) of a chip is connected; Make the fifth outer rewiring layer 10b in the second outer through hole 17 simultaneously, and then make the fifth outer rewiring layer 10b connect with the third outer rewiring layer 8b, this When the fifth outer rewiring layer 10b is connected to the back electrode of the first chip 1 and the back electrode of the second chip 2;

S9": as shown in FIG. 11, deposit a second dielectric layer 7b on the surface of the second plastic encapsulation layer 4b, and open holes in the second dielectric layer 7b to expose the fifth inner redistribution layer 10a and the fifth outer redistribution layer 10b 1. Make the lead metal 12 on the front electrode 13 of the second chip, deposit the lead metal 12 in the through hole of the second dielectric layer 7b, make the lead metal 12 and the fifth inner redistribution layer 10a, the fifth outer redistribution layer 10b 1. The front electrode 13 of the second chip is connected;

S10": As shown in FIG. 12, make pads 11 on the second dielectric layer 7b, and connect the pads 11 to the fifth inner redistribution layer 10a, the fifth outer redistribution layer 10b, and the front electrode 13 of the second chip , and further realize the lead-out of the front electrode 13 and the back electrode of the first chip 1 and the second chip, so as to complete the preparation of the packaging substructure.

In one example, when the first chip and the second chip are set upside down, as shown in FIG. 13 , the preparation method includes the following steps:

s1: Paste the second surface of the first chip on the carrier plate, plastic-encapsulate the first chip to obtain the first plastic sealing layer, and slot the first plastic sealing layer to expose the electrodes on the first surface of the first chip; preferably, When the first plastic encapsulation layer is grooved, the size of the groove is greater than the size of the first chip.

s2: making the first wiring metal layer in the groove, the first wiring metal layer is the first rewiring component; preferably, the surface of the first wiring metal layer is equal to the surface of the first plastic encapsulation layer;

s3: making a second chip on the first wiring metal layer, so that the first wiring metal layer is connected to the first surface electrode of the second chip; preferably, welding the second chip of the second chip on the first wiring metal layer by a welding method One side, and further connect the first surface electrode of the first chip to the first surface electrode of the second chip.

s4: Plastic-encapsulate the second chip to obtain the second plastic-encapsulation layer, and make the second wiring metal layer on the second plastic-encapsulation layer, so that the electrodes on the first surface of the second chip are connected to the second wiring metal layer, and then make the fourth plastic-encapsulation layer layer and then remove the carrier plate;

s5: Turn over the current packaging structure (the packaging structure obtained in steps s1-s4), make a third wiring metal layer that runs through the first plastic packaging layer and the second plastic packaging layer, so that the third wiring metal layer is connected to the second wiring metal layer. The second wiring metal layer and the third wiring metal layer form a second rewiring component;

s6: making a fourth wiring metal layer in the first plastic encapsulation layer, so that the fourth wiring metal layer is connected to the first wiring metal layer, and the fourth wiring metal layer is the third rewiring component;

s7: Fabricate a third dielectric layer on the first plastic packaging layer, and fabricate pads on the third dielectric layer, and connect the third wiring metal layer, the fourth wiring metal layer, and the electrodes on the second surface of the first chip to the pads.

In an example, when the first chip and the second chip are arranged in reverse, the preparation method may include the following steps:

s1': Paste the first chip on the carrier board, plastic-encapsulate the first chip to obtain the first plastic-encapsulation layer, and slot the first plastic-encapsulation layer to expose the first surface electrode of the first chip; preferably, the first When the plastic encapsulation layer is grooved, the size of the groove is greater than the size of the first chip.

s2': making the first wiring metal layer in the groove, the first wiring metal layer is the first rewiring component; preferably, the surface of the first wiring metal layer is flat with the surface of the first plastic encapsulation layer;

s3': making a second chip on the first wiring metal layer, so that the first wiring metal layer is connected to the first surface electrode of the second chip; preferably, welding the second chip on the first wiring metal layer by a welding method On the first surface, the electrodes on the first surface of the first chip are further connected to the electrodes on the first surface of the second chip.

s4': Plastic-encapsulate the second chip to obtain the second plastic-encapsulation layer, and fabricate the second wiring metal layer on the second plastic-encapsulation layer, so that the electrodes on the first surface of the second chip are connected to the second wiring metal layer, and then fabricate the fourth Plastic layer and then remove the carrier board;

s5': Flip the current packaging structure (the packaging structure obtained in steps s1-s4), make a fourth wiring metal layer in the first plastic packaging layer, connect the fourth wiring metal layer to the first wiring metal layer, and make the fourth wiring metal layer For the third rewiring component;

s6': Make a third wiring metal layer that runs through the first plastic packaging layer and the second plastic packaging layer, so that the third wiring metal layer is connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form a second layer Wiring parts;

s7': Make a third dielectric layer on the first plastic packaging layer, and make pads on the third dielectric layer, the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are connected to the pads .

In one example, forming the fourth wiring metal layer in the first plastic encapsulation layer includes the following steps:

s51': Opening holes in the first plastic sealing layer until the first wiring metal layer is exposed to obtain the fourth blind hole;

s52': making a fourth wiring metal layer in the fourth blind hole, that is, filling the metal layer in the fourth blind hole as the fourth wiring metal layer, so that the fourth wiring metal layer is connected to the first wiring metal layer.

In an example, making the third wiring metal layer passing through the first plastic encapsulation layer and the second plastic encapsulation layer includes the following steps:

s61': making holes in the second plastic sealing layer and the first plastic sealing layer until the second wiring metal layer is exposed, and obtaining a fifth through hole penetrating through the second plastic sealing layer and the first plastic sealing layer;

s62': making a third wiring metal layer in the fifth through hole, that is, filling the metal layer in the fifth through hole as the third wiring metal layer, so that the third wiring metal layer is connected to the second wiring metal layer.

In an example, when fabricating the fourth wiring metal layer in the fourth blind hole or fabricating the third wiring metal layer in the fifth via hole, the following sub-steps are included:

Sputtering a third seed layer on the surface of the current packaging structure, preferably a third seed layer made of Ti/Cu material;

Masking the third seed layer by using the third photoresist to expose the third seed layer corresponding to the position of the fourth blind hole or the fifth through hole;

Electroplating is performed on the third seed layer corresponding to the position of the fourth blind hole or the fifth through hole, preferably electroplating Cu;

Remove the third photoresist and the redundant third seed layer outside the position of the fourth blind hole or the fifth through hole to obtain the fourth wiring metal layer penetrating through the second plastic encapsulation layer, or through the second plastic encapsulation layer and the first encapsulation layer The third wiring metal layer; wherein, wet etching is preferably used to remove the third photoresist.

In an example, the third wiring metal layer includes interconnected third wiring metal sublayer A and third wiring metal sublayer B, the third wiring metal sublayer A penetrates the second plastic encapsulation layer, and the third wiring metal sublayer B penetrates The first plastic encapsulation layer is thus divided into two parts for manufacturing the third wiring metal layer, which greatly reduces the difficulty of the process. Correspondingly, the preparation method at this time includes the following steps:

s1": Paste the first chip on the carrier board, plastic-encapsulate the first chip to obtain the first plastic-encapsulation layer, and slot the first plastic-encapsulation layer to expose the first surface electrode of the first chip; preferably, the first When the plastic encapsulation layer is grooved, the size of the groove is greater than the size of the first chip.

s2": make the first wiring metal layer in the groove, the first wiring metal layer is the first rewiring component; preferably the surface of the first wiring metal layer is flat with the surface of the first plastic encapsulation layer;

s3": make a second chip on the first wiring metal layer, and connect the first wiring metal layer to the first surface electrode of the second chip; preferably, weld the second chip on the first wiring metal layer by a welding method On the first surface, the electrodes on the first surface of the first chip are further connected to the electrodes on the first surface of the second chip.

S4": making the third wiring metal sub-layer B penetrating through the first plastic encapsulation layer;

S5": Plastic-encapsulate the second chip to obtain the second plastic-encapsulation layer, and fabricate the second wiring metal layer on the second plastic-encapsulation layer, so that the electrodes on the first surface of the second chip are connected to the second wiring metal layer, and then fabricate the fourth Plastic layer and then remove the carrier board;

S6": Flip the current packaging structure (the packaging structure obtained in steps s1-s4), make the fourth wiring metal layer in the first plastic packaging layer, so that the fourth wiring metal layer is connected to the first wiring metal layer, and the fourth wiring metal layer For the third rewiring component;

s6": At the corresponding position of the third wiring metal sub-layer B, the third wiring metal sub-layer A that runs through the second plastic encapsulation layer is made, and then the third wiring metal sub-layer A is connected to the third wiring metal sub-layer B, and the third wiring metal sub-layer A is obtained. Three wiring metal layers, the third wiring metal layer is connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form a second rewiring component;

s7": Make a third dielectric layer on the first plastic packaging layer, and make pads on the third dielectric layer, the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are connected to the pads .

In an example, the second chip is plastic-encapsulated so that the second plastic-encapsulation layer is replaced by:

The second chip and the first wiring metal layer are plastic-sealed to obtain the second plastic packaging layer, so as to reduce the volume of the packaging structure, and at the same time prevent the first wiring metal layer from being exposed to the air, thereby improving the packaging reliability.

In an example, a third dielectric layer is fabricated on the first plastic encapsulation layer, and before pads are fabricated on the third dielectric layer, further includes:

making a third dielectric layer on the first plastic sealing layer;

Opening holes in the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed to obtain a number of sixth through holes;

filling the pin metal in the sixth through hole;

A pad is made on the third dielectric layer, so that the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are connected to the pad through the pin metal. In this example, the pin metal is introduced through the third dielectric layer, and the connection between the third wiring metal layer, the fourth wiring metal layer, the second surface electrode of the first chip and the pad is realized through the pin metal, and the connection stability is improved. sex and reliability.

In this example, the third dielectric layer can be replaced by the interconnected fourth dielectric layer and fifth dielectric layer. At this time, before making the pad, it also includes:

Making a fourth dielectric layer on the first plastic sealing layer;

Opening holes in the fourth dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed to obtain a number of seventh through holes;

filling the fifth wiring metal layer in the seventh through hole;

making a fifth dielectric layer on the fourth dielectric layer;

Opening holes in the fifth dielectric layer until the fifth wiring metal layer is exposed, thereby obtaining a number of eighth via holes (located in the fifth dielectric layer);

filling the pin metal in the eighth through hole;

Making pads on the fifth dielectric layer, so that the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are connected to the pads through the fifth wiring metal layer and the lead metal in sequence.

Combining the above examples, when the first chip and the second chip are arranged in reverse, the second preferred example of the method for preparing the package (sub)structure includes the following steps:

s1"': As shown in Figure 14, paste the front of the first chip 1 on the carrier board 3, and plastic seal the first chip 1 to obtain the first plastic sealing layer 4a; then slot the first plastic sealing layer 4a to expose the back electrode of the first chip 1;

s2"': As shown in Figure 15, the first wiring metal layer 18 (interconnection metal block) is made in the groove, and the electroplating Cu method is preferably used to realize the first wiring metal layer 18. The first wiring metal layer 18 is the first wiring metal layer 18. A rewiring component; at this time, the surface of the first wiring metal layer 18 is flat with the surface of the first plastic encapsulation layer 4a, which is generally achieved by smoothing the first wiring metal layer 18 protruding from the surface of the first plastic encapsulation layer 4a.

s3"': As shown in FIG. 16, the second chip 2 is fabricated on the first wiring metal layer 18, and the first wiring metal layer 18 and the second chip 2 are preferably connected by welding methods such as silver glue, eutectic, and glue coating. The connection of the back electrode, and then realize the interconnection between the back electrode of the first chip 1 and the back electrode of the second chip 2;

s4"': As shown in FIG. 17, the second chip 2 is plastic-encapsulated to obtain the second plastic-encapsulation layer 4b, and the second wiring metal layer 19 is formed on the second plastic-encapsulation layer 4b, so that the front electrode 13 of the second chip is connected to the first The two wiring metal layers 19 are connected, and then the second wiring metal layer 19 is plastic-encapsulated to obtain the fourth plastic-encapsulation layer 4d, and the carrier board 3 is removed;

s5"': As shown in Figure 18, turn over the current packaging structure (the packaging structure obtained in steps s1-s4), at this time, the front electrode 13 of the first chip is facing upward, and the front electrode 13 of the second chip is facing downward; for the first Holes are opened in the plastic sealing layer 4a until the first wiring metal layer 18 is exposed to obtain a fourth blind hole 24;

s6"': As shown in FIG. 19, a metal layer is filled in the fourth blind hole 24 as the fourth wiring metal layer 21, and the fourth wiring metal layer 21 is essentially a third rewiring component, so that the fourth wiring metal layer 21 and The first wiring metal layer 18 is connected to lead out the first wiring metal layer 18;

s7"': as shown in Figure 20, open holes on the second plastic sealing layer 4b and the first plastic sealing layer 4a until the second wiring metal layer 19 is exposed, and obtain the fifth wire that runs through the second plastic sealing layer 4b and the first plastic sealing layer 4a. Through hole 25;

s8"': As shown in FIG. 21, fill the fifth through hole 25 with a metal layer as the third wiring metal layer 20, so that the third wiring metal layer 20 is connected to the second wiring metal layer 19, and the second wiring metal layer 19 , the third wiring metal layer 20 forms a second redistribution component;

s9"': As shown in FIG. 22, make a fourth dielectric layer 23a on the first plastic packaging layer 4a, and open holes in the fourth dielectric layer 23a until the third wiring metal layer 20, the fourth wiring metal layer 21, The second surface electrode of the first chip 1 obtains a plurality of seventh through holes 26;

s10"': As shown in FIG. 23, fill the fifth wiring metal layer 22 in the seventh via hole 26, then form the fifth dielectric layer 23b on the fourth dielectric layer 23a, and open holes in the fifth dielectric layer 23b until Expose the fifth wiring metal layer 22, and then obtain a number of eighth via holes 27 (located in the fifth dielectric layer 23b);

s11"': As shown in Figure 24, fill the pin metal 12 in the eighth through hole 27, and make the pad 11 on the fifth dielectric layer 23b, so that the third wiring metal layer 20, the fourth wiring metal layer 21 1. The second surface electrode of the first chip 1 is connected to the pad 11 through the fifth wiring metal layer 22 and the lead metal 12 in sequence.

The present invention also includes a chip packaging structure, including a packaging substructure, the packaging substructure is obtained according to the preparation method described in any of the above examples, including a first plastic sealing layer and a second plastic sealing layer that are stacked, and the packaging in the first plastic sealing layer There is a first chip, and a second chip is packaged in the second plastic encapsulation layer;

The second surface electrode of the first chip or the second surface electrode of the second chip is connected to the pad through the second redistribution component; when the second surface electrode of the first chip is connected to the pad through the second redistribution component, the first The electrodes on the second surface of the second chip are connected to the pads; when the electrodes on the second surface of the second chip are connected to the pads through the second rewiring element, the electrodes on the second surface of the first chip are connected to the pads;

The first surface electrode of the first chip and the first surface electrode of the second chip are connected to the pad through the first redistribution component and the third redistribution component.

Preferably, when the first chip and the second chip are arranged in the same direction, the packaging substructure is shown in Figure 12, and the packaging substructure includes the third plastic packaging layer, the first wiring layer, the first plastic packaging layer, and the second plastic packaging layer from bottom to top. A dielectric layer, a second plastic encapsulation layer, a second dielectric layer and a pad;

The first chip is packaged in the first plastic encapsulation layer, and a third outer wiring layer is formed through the first plastic encapsulation layer and the first dielectric layer, and the third outer wiring layer is in the shape of "back";

A second wiring layer is formed in the first dielectric layer, and a third inner wiring layer is formed on the second wiring layer and in the first dielectric layer;

A second chip is packaged in the second plastic package, and the first chip and the second chip are arranged in the same direction; a fourth wiring layer is also provided in the second plastic package layer, and the fourth wiring layer is arranged at the bottom of the second chip, that is, the fourth wiring layer It is connected to the back electrode of the second chip; a fifth inner wiring layer and a fifth outer wiring layer are also arranged in the second plastic encapsulation layer, and the fifth inner wiring layer and the fifth outer wiring layer penetrate the second plastic encapsulation layer;

Lead metal is formed in the second dielectric layer;

The front electrode of the first chip is connected to the pad through the second wiring layer, the third inner wiring layer, the fifth inner wiring layer, and the pin metal in sequence; the front electrode of the second chip is connected to the pad through the pin metal;

The back electrode of the first chip is connected to the pad through the first wiring layer, the third outer wiring layer, the fifth outer wiring layer, and the pin metal in sequence; the back electrode of the second chip is connected to the pad through the fourth wiring layer and the third outer wiring layer. , the fifth outer wiring layer, the lead metal and the pad are connected.

Preferably, when the first chip and the second chip are reversed, the packaging substructure is shown in Figure 24, and the packaging substructure includes the fourth plastic packaging layer, the second plastic packaging layer, the first plastic packaging layer, and the second plastic packaging layer from bottom to top. Four dielectric layers, fifth dielectric layer and pad;

A second wiring metal layer is formed in the fourth plastic packaging layer, and the second wiring metal layer is connected to the front electrode of the second chip;

A third wiring metal layer is formed through the first plastic encapsulation layer and the second plastic encapsulation layer, the third wiring metal layer is connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form a second redistribution component;

The first chip is packaged in the first plastic encapsulation layer, and the first chip and the second chip are arranged oppositely; the first wiring metal layer (first rewiring element) is also provided in the first plastic encapsulation layer, and the first wiring metal layer is arranged on The bottom of the first chip, that is, the first wiring metal layer is connected to the back electrode of the first chip; a fourth wiring metal layer is also provided in the second plastic encapsulation layer, and the fourth wiring metal layer is connected to the first wiring metal layer, and the first wiring metal layer The metal layer and the fourth wiring metal layer form a third rewiring component;

A fifth wiring metal layer is formed in the fourth dielectric layer;

Lead metal is formed in the fifth dielectric layer;

The back electrode of the first chip and the back electrode of the second chip are connected to the pad through the first wiring metal layer, the fourth wiring metal layer, the fifth wiring metal layer, and the pin metal in sequence;

The front electrode of the first chip is connected to the pad through the fifth wiring metal layer and the pin metal in turn; the front electrode of the second chip is connected to the pad through the second wiring metal layer, the third wiring metal layer, the fifth wiring metal layer, and the pin The metal is connected to the pad.

In an example, the packaging substructures prepared in the above example are horizontally spliced to obtain a multi-chip packaging structure. In this example, the packaging structure can be obtained by horizontal splicing after preparing a packaging substructure formed by two chips, or it can also be obtained during the preparation of the packaging substructure. Multiple first chips are packaged in one layer, and multiple second chips are packaged in the second plastic packaging layer. In other steps, the two chips are stacked as a group and interconnected through rewiring components, and rewiring components with the same function can be in the same The multi-chip packaging structure is prepared in this way, which simplifies the preparation process, saves packaging time, and greatly improves the packaging efficiency.

The above specific embodiment is a detailed description of the present invention, and it cannot be determined that the specific embodiment of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field of the present invention, they can also Making some simple deduction and substitution should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A preparation method of a chip packaging structure is characterized by comprising the following steps: it comprises the following steps:

packaging the first chip to obtain a first plastic sealing layer;

manufacturing a first rewiring member, wherein the first rewiring member is connected with a first surface electrode of a first chip;

packaging the second chip to obtain a second plastic sealing layer stacked on the first plastic sealing layer, wherein a first surface electrode of the second chip is connected with a first surface electrode of the first chip through a first rewiring piece; the first surface electrode of the first chip and the first surface electrode of the second chip are the same electrode;

manufacturing a second rewiring member, wherein the second surface electrode of the first chip or the second surface electrode of the second chip is connected with the bonding pad through the second rewiring member; when the second surface electrode of the first chip is connected with the bonding pad through the second rewiring member, the second surface electrode of the second chip is connected with the bonding pad; when the second surface electrode of the second chip is connected with the bonding pad through the second rewiring member, the second surface electrode of the first chip is connected with the bonding pad;

And manufacturing a third rewiring, wherein the first surface electrode of the first chip and the first surface electrode of the second chip are connected with the bonding pad through the first rewiring and the third rewiring.

2. The method for manufacturing a chip package according to claim 1, wherein: when the first chip and the second chip are arranged in the same direction, the method comprises the following steps:

adhering a first chip on a carrier plate, performing plastic package on the first chip to obtain a first plastic package layer, manufacturing a first wiring layer on the first plastic package layer, and manufacturing a third plastic package layer on the first wiring layer;

removing the carrier plate, manufacturing a second wiring layer, and depositing a first dielectric layer;

manufacturing a third inner wiring layer in the first dielectric layer, connecting the third inner wiring layer with the second wiring layer, and manufacturing a third outer wiring layer penetrating through the first plastic sealing layer and the first dielectric layer;

manufacturing a fourth wiring layer on the first dielectric layer, wherein the fourth wiring layer is connected with the third outer wiring layer, and the first wiring layer, the third outer wiring layer and the fourth wiring layer form a first re-wiring piece;

sticking a second chip on the fourth wiring layer, connecting a first surface electrode of the second chip with the fourth wiring layer, and performing plastic packaging on the second chip to obtain a second plastic packaging layer;

Manufacturing a fifth inner wiring layer and a fifth outer wiring layer which penetrate through the second plastic sealing layer, wherein the fifth inner wiring layer is connected with the third inner wiring layer, and the second wiring layer, the third inner wiring layer and the fifth inner wiring layer form a second rewiring piece; the fifth outer wiring layer is a third rewiring member and is connected with the third outer wiring layer;

and manufacturing a bonding pad on the second plastic sealing layer, wherein the fifth inner side wiring layer, the fifth outer side wiring layer and the second surface electrode of the second chip are connected with the bonding pad.

3. The method for manufacturing a chip package according to claim 2, wherein: and the second chip is subjected to plastic packaging to obtain a second plastic packaging layer, which is replaced by:

and carrying out plastic packaging on the fourth wiring layer and the second chip to obtain a second plastic packaging layer.

4. The method for manufacturing a chip package according to claim 2, wherein: the method for manufacturing the bonding pad on the second plastic sealing layer further comprises the following steps:

manufacturing a second dielectric layer on the second plastic layer;

perforating the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer and the second surface electrode of the second chip are exposed, so as to obtain a plurality of through holes;

filling pin metal in the through hole;

And manufacturing a bonding pad on the second dielectric layer, and connecting the fifth inner side wiring layer, the fifth outer side wiring layer and the second surface electrode of the second chip with the bonding pad through pin metal.

5. The method for manufacturing a chip package according to claim 1, wherein: when the first chip and the second chip are reversely arranged, the method comprises the following steps:

adhering a first chip on a carrier plate, performing plastic package on the first chip to obtain a first plastic package layer, and grooving the first plastic package layer to expose a first surface electrode of the first chip;

manufacturing a first wiring metal layer in the groove, wherein the first wiring metal layer is a first rewiring piece;

manufacturing a second chip on the first wiring metal layer, and connecting the first wiring metal layer with a first surface electrode of the second chip;

performing plastic packaging on the second chip to obtain a second plastic packaging layer, manufacturing a second wiring metal layer on the second plastic packaging layer, connecting a first surface electrode of the second chip with the second wiring metal layer, manufacturing a fourth plastic packaging layer, and removing the carrier plate;

turning over the current packaging structure, manufacturing a third wiring metal layer penetrating through the first plastic sealing layer and the second plastic sealing layer, connecting the third wiring metal layer with the second wiring metal layer, and forming a second rewiring piece by the second wiring metal layer and the third wiring metal layer;

Manufacturing a fourth wiring metal layer in the first plastic sealing layer, and connecting the fourth wiring metal layer with the first wiring metal layer, wherein the fourth wiring metal layer is a third rewiring piece;

and manufacturing a third dielectric layer on the first plastic sealing layer, manufacturing a bonding pad on the third dielectric layer, and connecting the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip with the bonding pad.

6. The method for manufacturing a chip package according to claim 5, wherein: the third wiring metal layer comprises a third wiring metal sub-layer A and a third wiring metal sub-layer B which are mutually connected, wherein the third wiring metal sub-layer A penetrates through the second plastic layer, and the third wiring metal sub-layer B penetrates through the first plastic layer.

7. The method for manufacturing a chip package according to claim 5, wherein: and the second chip is subjected to plastic packaging to obtain a second plastic packaging layer, which is replaced by:

and carrying out plastic packaging on the second chip and the first wiring metal layer to obtain a second plastic packaging layer.

8. The method for manufacturing a chip package according to claim 5, wherein: the manufacturing the bonding pad on the third dielectric layer comprises the following steps:

manufacturing a third dielectric layer on the first plastic layer;

Opening holes on the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip are exposed, so as to obtain a plurality of through holes;

filling pin metal in the through hole;

and manufacturing a bonding pad on the third dielectric layer, and connecting the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip with the bonding pad through pin metal.

9. A chip packaging structure, characterized in that: the packaging structure is obtained by the preparation method according to any one of claims 1-8, and comprises a first plastic sealing layer and a second plastic sealing layer which are arranged in a laminated manner, wherein a first chip is packaged in the first plastic sealing layer, and a second chip is packaged in the second plastic sealing layer;

the second surface electrode of the first chip or the second surface electrode of the second chip is connected with the bonding pad through the second rewiring; when the second surface electrode of the first chip is connected with the bonding pad through the second rewiring member, the second surface electrode of the second chip is connected with the bonding pad; when the second surface electrode of the second chip is connected with the bonding pad through the second rewiring member, the second surface electrode of the first chip is connected with the bonding pad;

the first surface electrode of the first chip and the first surface electrode of the second chip are connected to the bonding pad via the first rewiring member and the third rewiring member.

10. The chip package structure of claim 9, wherein: the multi-chip package structure comprises a plurality of package substructures, wherein each package substructures are horizontally spliced to obtain the multi-chip package structure.

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