CN116015249A - A Redundant Clock Automatic Detection and Switching System - Google Patents

Abstract

The invention discloses a redundant clock automatic detection and switching system, which can be effectively applied to the application scene of redundant clock automatic switching. The provided automatic detection circuit can automatically generate the clock selection control signal according to the input of the external clock, and can change the judgment threshold voltage value according to different application requirements. The provided low noise amplifier circuit can restore the power of the external clock signal under the condition of introducing very little noise. The provided two-input clock buffer circuit can not only improve the clock output drive capability when introducing less noise, but also can output multiple clocks simultaneously for system use.

Description

A Redundant Clock Automatic Detection and Switching System

technical field

The invention relates to the technical field of electronic equipment, in particular to a redundant clock automatic detection and switching system capable of detecting the health status of clock signals and performing automatic switching.

Background technique

The clock source is used to provide a square wave clock pulse signal with stable frequency and level matching for the ring pulse generator. It usually consists of a positive feedback oscillating circuit composed of a quartz crystal oscillator and a NAND gate, and its output is sent to a ring pulse generator.

The system clock signal is usually obtained from two clock sources, that is, the system internal clock source and the external input high-precision clock source. extension generated. Generally, when the system works alone, only the internal clock source is needed to make the system work stably, but if multiple similar systems are required to work synchronously, an external high-precision synchronous clock signal is required.

In the prior art, the required clock source is usually selected through program control or switch control multiplexer. This method has many disadvantages, for example, it cannot automatically detect whether the clock source is healthy or not. At the same time, the required clock source cannot be automatically selected according to the health status of the clock. Additionally, noise is introduced as the clock signal passes through the multiplexer.

Therefore, how to provide a system that can detect the health status of the clock signal and perform automatic switching is a technical problem that urgently needs to be solved by those skilled in the art.

Contents of the invention

In view of the above problems, the present invention provides a redundant clock automatic detection and switching system for overcoming the above problems or at least partially solving the above problems.

The present invention provides following scheme:

A redundant clock automatic detection and switching system, comprising:

a connector, the connector is used to receive a first clock signal input by a first clock source;

a power divider, the power divider is connected to the connector, and the power divider is used to divide the first clock signal into two;

A detection circuit, the detection circuit is connected to the power divider, and the detection circuit is used to generate a clock selection control signal according to the result of comparing the identification voltage with the target decision threshold voltage; the identification voltage is based on the first A voltage signal with different amplitudes generated by the strength of the clock signal;

a low-noise amplifier, the low-noise amplifier is connected to the power divider, and the low-noise amplifier is used to restore the power of the first clock signal whose power is halved to the first clock signal at the input end of the power divider. The power of the clock signal;

A clock buffer, the detection circuit, the low-noise amplifier and the second clock source are respectively connected to the clock buffer; the clock buffer includes multiple clock output terminals; the clock buffer is used for according to the The clock selection control signal determines the first clock source or the second clock source as the system clock.

Preferably: the first clock source is an external clock source, and the second clock source is an internal clock source.

Preferably: the detection circuit includes a wave detector; the wave detector is connected to the power divider; the wave detector is used to generate the identification voltage with different amplitudes according to the strength of the first clock signal.

Preferably: the detection circuit further includes a voltage comparator, the voltage comparator is respectively connected to the clock buffer and the detector; the voltage comparator is used to compare the identification voltage with the target decision threshold A voltage comparison generates the clock selection control signal.

Preferably: the detection circuit further includes a reference voltage source connected to the voltage comparator, and the reference voltage source is used to provide a target decision threshold voltage for the voltage comparator.

Preferably: the target decision threshold voltage is determined according to application scenario requirements.

Preferably: the buffer includes a two-input clock buffer, and the two-input clock buffer includes a clock source selection port.

Preferably: a DC blocking capacitor is provided between the connector and the power divider.

According to the specific embodiments provided by the invention, the invention discloses the following technical effects:

The redundant clock automatic detection and switching system provided by the embodiment of the present application can be effectively applied to the application scenario of redundant clock automatic switching. The provided automatic detection circuit can automatically generate the clock selection control signal according to the input of the external clock, and can change the judgment threshold voltage value according to different application requirements. The provided low noise amplifier circuit can restore the power of the external clock signal under the condition of introducing very little noise. The provided two-input clock buffer circuit can not only improve the clock output drive capability when introducing less noise, but also can output multiple clocks simultaneously for system use.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings required in the embodiments. Apparently, the drawings in the following description are only some embodiments of the present invention, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

FIG. 1 is a connection block diagram of a redundant clock automatic detection and switching system provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention belong to the protection scope of the present invention.

Referring to Fig. 1, a redundant clock automatic detection and switching system provided by an embodiment of the present invention, as shown in Fig. 1, the system may include:

A connector J1, the connector J1 is used to receive a first clock signal input by a first clock source;

A power divider U1, the power divider U1 is connected to the connector J1, and the power divider U1 is used to divide the first clock signal into two;

A detection circuit, the detection circuit is connected to the power divider U1, and the detection circuit is used to generate a clock selection control signal according to the result of comparing the identification voltage with the target decision threshold voltage; the identification voltage is based on the Voltage signals with different amplitudes generated by the strength of the first clock signal;

A low-noise amplifier U5, the low-noise amplifier U5 is connected to the power divider U1, and the low-noise amplifier U5 is used to restore the power of the first clock signal whose power is halved to the input of the power divider U1 The power level of the first clock signal at the terminal;

Clock buffer U7, the detection circuit, the low noise amplifier U5 and the second clock source U6 are respectively connected with the clock buffer U7; the clock buffer U7 includes multiple clock output terminals; the clock buffer The controller U7 is used to determine the first clock source or the second clock source as the system clock according to the clock selection control signal.

The redundant clock automatic detection and switching system provided by the embodiment of the present application can detect the health status of the clock source and form a control signal through the provided clock detection circuit. Through the formed clock selection circuit, the clock source can be automatically switched and selected according to the control signal formed by the detection circuit.

Further, the embodiment of the present application may provide that the first clock source is an external clock source, and the second clock source is an internal clock source. In the redundant clock automatic detection and switching circuit provided by the embodiment of the present application, the external clock is the main clock. If the external clock is connected to the J1 connector, the external clock is automatically switched to the system clock through this circuit, otherwise the internal clock is the system clock. ; The application of the external clock ensures the basis of synchronous clocks between different devices.

The detection circuit provided by the embodiment of the present application can monitor the health status of the first clock source connected by the connector. Specifically, the embodiment of the present application can provide that the detection circuit includes a wave detector U3; The power divider U3 is connected to the power divider U1; the wave detector U3 is used to generate the identification voltage with different amplitudes according to the strength of the first clock signal.

Further, the detection circuit also includes a voltage comparator U4, the voltage comparator U4 is respectively connected to the clock buffer U7 and the detector U3; the voltage comparator U4 is used to convert the identification voltage to The clock selection control signal is generated by comparing with the target decision threshold voltage.

Still further, the detection circuit also includes a reference voltage source U2, the reference voltage source U2 is connected to the voltage comparator U4, and the reference voltage source U2 is used to provide a target decision threshold for the voltage comparator U4 Voltage. The target decision threshold voltage is determined according to application scenario requirements. The threshold voltage can be customized by the user according to the needs.

The buffer provided in the embodiment of the present application can take various forms. For example, in an implementation manner, the embodiment of the present application can provide that the buffer includes a two-input clock buffer, and the two-input clock buffer includes a clock source Select a port.

In order to further prevent the large DC component of the first clock signal from damaging the rear internal circuit, the embodiment of the present application may provide that a DC blocking capacitor C1 is provided between the connector J1 and the power divider U1 .

The system provided by the embodiment of the present application will be described in detail below with reference to FIG. 1 .

The redundant clock automatic detection and switching system provided by the embodiment of the present application may include J1, C1, U1-U7, and complete external clock splitting into two, external clock detection, clock signal amplification, and automatic clock switching; the external clock is the main Clock, if the external clock is connected to the J1 connector, the external clock will be automatically switched to the system clock through this circuit, otherwise the internal clock will be the system clock; the application of the external clock ensures the basis of synchronous clocks between different devices.

J1 connector is an external clock input connector through which the first clock source (external clock source) inputs the external clock signal; C1 is a DC blocking capacitor to prevent the large DC component of the external clock signal from damaging the rear internal circuit.

U1 power divider divides the input external clock signal into two, one way enters the automatic detection circuit, and the other enters the low noise amplifier.

U2, U3, and U4 form an automatic detection circuit, U3 is a detector, which generates identification voltage signals of different amplitudes according to the signal strength of the input external clock; U2 is a reference voltage source, which provides a decision threshold voltage for the U4 voltage comparator, The decision threshold voltage can be set to different voltage values according to different application scenarios; U4 is a voltage comparator, which compares the identification voltage generated by the U3 detector with the decision threshold voltage to generate a clock selection control signal.

U5 is a low-noise amplifier. After the external clock is divided into two by the U1 power divider, the power of the external clock signal entering the U5 low-noise amplifier is halved. The power is restored to the power of the external clock signal at the input end of the U1 power divider.

U6 is the second clock source (internal clock source), which is used as the system clock in the absence of external clock input, ensuring that the device does not rely on the external clock source and works independently;

U7 is a two-input clock buffer. The buffer has two clock input sources and a clock source selection port. The first clock input source or the second clock input source can be selected as the system clock through the clock selection control signal generated in step 3. ; The clock buffer has an excellent noise suppression function, which can not only improve the output drive capability of the clock while introducing less noise, but also output multiple clocks for the system at the same time.

In a word, the redundant clock automatic detection and switching system provided by the present application can be effectively applied to the application scenario of redundant clock automatic switching. The provided automatic detection circuit can automatically generate the clock selection control signal according to the input of the external clock, and can change the judgment threshold voltage value according to different application requirements. The provided low noise amplifier circuit can restore the power of the external clock signal under the condition of introducing very little noise. The provided two-input clock buffer circuit can not only improve the clock output drive capability when introducing less noise, but also can output multiple clocks simultaneously for system use.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

It can be known from the above description of the implementation manners that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the essence of the technical solution of this application or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in storage media, such as ROM/RAM, disk , CD, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments of the present application.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to the part of the description of the method embodiment. The systems and system embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is It can be located in one place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without creative effort.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (8)

1. A redundant clock automatic detection and switching system, characterized in that, comprising: a connector, the connector is used to receive a first clock signal input by a first clock source; a power divider, the power divider is connected to the connector, and the power divider is used to divide the first clock signal into two; A detection circuit, the detection circuit is connected to the power divider, and the detection circuit is used to generate a clock selection control signal according to the result of comparing the identification voltage with the target decision threshold voltage; the identification voltage is based on the first A voltage signal with different amplitudes generated by the strength of the clock signal; a low-noise amplifier, the low-noise amplifier is connected to the power divider, and the low-noise amplifier is used to restore the power of the first clock signal whose power is halved to the first clock signal at the input end of the power divider. The power of the clock signal; A clock buffer, the detection circuit, the low-noise amplifier and the second clock source are respectively connected to the clock buffer; the clock buffer includes multiple clock output terminals; the clock buffer is used for according to the The clock selection control signal determines the first clock source or the second clock source as the system clock. 2. The redundant clock automatic detection and switching system according to claim 1, wherein the first clock source is an external clock source, and the second clock source is an internal clock source. 3. The redundant clock automatic detection and switching system according to claim 1, wherein the detection circuit includes a detector; the detector is connected to the power divider; The strength of the first clock signal generates the identification voltages with different amplitudes. 4. The redundant clock automatic detection and switching system according to claim 3, characterized in that, the detection circuit also includes a voltage comparator, and the voltage comparator is connected to the clock buffer and the detection circuit respectively. The voltage comparator is used to compare the identification voltage with the target decision threshold voltage to generate the clock selection control signal. 5. The redundant clock automatic detection and switching system according to claim 4, wherein the detection circuit also includes a reference voltage source, the reference voltage source is connected to the voltage comparator, and the reference voltage source is connected to the voltage comparator. The voltage source is used to provide the target decision threshold voltage for the voltage comparator. 6 . The redundant clock automatic detection and switching system according to claim 5 , wherein the target decision threshold voltage is determined according to application scenario requirements. 7 . 7. The redundant clock automatic detection and switching system according to claim 1, wherein the buffer comprises two input clock buffers, and the two input clock buffers comprise a clock source selection port. 8. The redundant clock automatic detection and switching system according to claim 1, wherein a DC blocking capacitor is arranged between the connector and the power divider.

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