CN115939215A - A VDMOS device - Google Patents

Abstract

The invention discloses a VDMOS device, comprising: a substrate layer; an epitaxial layer grown on one side of the substrate layer; a P-body layer arranged on the side of the epitaxial layer away from the substrate layer; an ohmic contact layer arranged on the side of the P-body layer far away from the substrate layer. One side of the epitaxial layer; the source electron layer, juxtaposed with the ohmic contact layer, is arranged on the side of the P-body layer away from the epitaxial layer; the first metal layer covers the ohmic contact layer and the source electron layer; the channel is arranged on Between the first metal layer and the epitaxial layer, the channel is close to the side of the source electron layer away from the ohmic contact layer; the gate polysilicon layer is arranged in the channel; the source polysilicon layer is arranged in the channel and the gate polysilicon layer is away from the first One side of a metal layer; the tail end of the source polysilicon layer is connected to the first metal layer through the second metal layer, and the second metal layer is a Schottky barrier metal; the tail end of the gate polysilicon layer passes through the third isolation layer Isolated from the tail of the source polysilicon layer. By adopting the invention, a new isolation structure is used to improve the anti-ESD capability.

Description

A VDMOS device

technical field

The invention relates to the field of semiconductors, in particular to a VDMOS device.

Background technique

The shielded gate field effect transistor is developed on the basis of the traditional trench VDMOS. It has an upper and lower polycrystalline structure. The upper polycrystalline is a gate control gate structure, which is similar to the traditional trench structure. The line is connected to the source and acts as a shield gate. Compared with the traditional trench VDMOS, it has smaller on-resistance and lower Miller capacitance under the same withstand voltage, and has faster switching speed. Due to the complexity of the actual application environment, the reliability requirements for power VDMOS are relatively high. Power device products are easily affected by ESD during their production, manufacturing, assembly and working process, resulting in internal damage and reduced reliability of the product. Power VDMOS The weak point of ESD is the breakdown of the thin gate oxide layer at the gate-source end. Because the shield gate VDMOS has a double gate structure, its failure point is also the breakdown of the oxide layer between the upper and lower polycrystalline structures. There are mainly two formation methods for the isolation of the two-layer polycrystalline structure, one is to form isolation by depositing silicon dioxide, and the other is to form dielectric isolation by thermal oxidation of polysilicon. The first type of silicon dioxide formed by deposition is not easy to control the thickness during etching, and etching is easy to cause oxide layer damage, reducing the breakdown voltage at both ends of the gate and source; the second type of oxide layer formed by thermal oxidation of polysilicon, The quality of the oxide layer is poor, and the resistance to ESD is also poor.

Contents of the invention

An embodiment of the present invention provides a VDMOS device to at least solve the problem of poor ESD resistance of the VDMOS device in the prior art.

A kind of VDMOS device proposed according to the present invention comprises:

The substrate layer is an N-type heavily doped layer;

an epitaxial layer grown on one side of the substrate layer, the epitaxial layer being an N-type lightly doped layer;

a P-body layer disposed on a side of the epitaxial layer away from the substrate layer;

an ohmic contact layer disposed on a side of the P-body layer away from the epitaxial layer;

a source electron layer, juxtaposed with the ohmic contact layer, disposed on a side of the P-body layer away from the epitaxial layer;

The first metal layer covers the ohmic contact layer and the source electron layer, and is electrically connected to both the ohmic contact layer and the source electron layer;

a channel, disposed between the first metal layer and the epitaxial layer, the channel is close to the side of the source electron layer away from the ohmic contact layer;

The gate polysilicon layer is arranged in the channel, and is isolated from the first metal layer, the P-body layer, and the source electron layer by a first isolation layer;

a source polysilicon layer disposed on a side of the gate polysilicon layer away from the first metal layer, and isolated from the epitaxial layer by a second isolation layer;

The head end of the gate polysilicon layer is flush with the head end of the source polysilicon layer, and the tail end of the source polysilicon layer is connected to the first metal layer through a second metal layer, and the second metal layer layer is a Schottky barrier metal; the tail end of the gate polysilicon layer is isolated from the tail end of the source polysilicon layer by a third isolation layer, and the third isolation layer is between the first metal layer and the substrate layer The depth of the direction is greater than the depth of the gate polysilicon layer.

According to some embodiments of the present invention, the thickness of the first isolation layer is smaller than the thickness of the second isolation layer.

According to some embodiments of the present invention, the thickness of the first isolation layer is 30-150 nm.

According to some embodiments of the present invention, the thickness of the second isolation layer is 0.1-0.8um.

According to some embodiments of the present invention, the gate polysilicon layer is a P-type heavily doped layer, and the source polysilicon layer is an N-type lightly doped layer.

According to some embodiments of the present invention, the doping impurity of the gate polysilicon layer is boron or aluminum.

According to some embodiments of the present invention, the doping impurity of the source polysilicon layer is phosphorus or arsenic, and the doping concentration is 1E15-1E17 cm ⁻³ .

According to some embodiments of the present invention, the Schottky barrier metal is titanium or nickel.

By adopting the technical scheme of the embodiment of the present invention, the oxide layer between the traditional double-layer polycrystalline structure is converted into a new type of PN junction isolation, and at the same time, the connection between the source polysilicon layer and the source metal of the first metal layer adopts Schottky potential The barrier metal is connected, so that a PN junction diode and a Schottky diode are formed between the gate and the source. While achieving the effect of reducing Miller capacitance, it can also cause the diode to be broken down first when the static electricity is discharged, directly from the gate A parasitic diode between the sources releases energy, further improving ESD immunity.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the embodiments. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. In the attached picture:

Fig. 1 is the structural representation of VDMOS device in the embodiment of the present invention;

FIG. 2 is a schematic diagram of an equivalent circuit of a VDMOS device in an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

An embodiment of the present invention proposes a VDMOS device, referring to FIG. 1, including:

The substrate 1 is an N-type heavily doped layer.

The epitaxial layer 2 is grown on one side of the substrate layer 1, and the epitaxial layer 2 is an N-type lightly doped layer.

The P-body layer 3 is disposed on the side of the epitaxial layer 2 away from the substrate layer 1, and this layer is a P-type lightly doped layer.

The ohmic contact layer 4 is disposed on the side of the P-body layer 3 away from the epitaxial layer 2 , and this layer is a P-type heavily doped layer for providing an ohmic contact.

The source electron layer 5 is juxtaposed with the ohmic contact layer 4 and is arranged on the side of the P-body layer 3 away from the epitaxial layer 2. This layer is an N-type heavily doped layer and is used for device operation Provides source electrons.

The first metal layer 6 covers the ohmic contact layer 4 and the source electron layer 5 , and is electrically connected to the ohmic contact layer 4 and the source electron layer 5 .

A channel is disposed between the first metal layer 6 and the epitaxial layer 3 , the channel is close to the side of the source electron layer 5 away from the ohmic contact layer 4 . The channel occupies part of the space of the epitaxial layer 2 , which can be obtained by etching or processing the epitaxial layer 2 in the production process.

The gate polysilicon layer 7 is disposed on the channel, and is isolated from the first metal layer 6 , the P-body layer 3 , and the source electron layer 5 by a first isolation layer 9 . The first isolation layer 9 is mainly used to provide electrical isolation between gate and source.

The source polysilicon layer 8 is disposed on the side of the gate polysilicon layer 7 away from the first metal layer 6 , and is isolated from the epitaxial layer 2 by the second isolation layer 10 .

The head end of the gate polysilicon layer 7 is flush with the head end of the source polysilicon layer 8, and the tail end of the source polysilicon layer 8 is connected to the first metal layer 6 through the second metal layer 11, The second metal layer 11 is Schottky barrier metal. The tail end of the gate polysilicon layer 7 is isolated from the tail end of the source polysilicon layer 8 by the third isolation layer 12, and the depth of the third isolation layer 12 in the direction from the first metal layer 6 to the substrate layer 2 is It should be greater than the depth of the gate polysilicon layer 7, that is, the bottommost position of the third isolation layer 12 should be lower than the bottommost position of the gate polysilicon layer 7, so as to achieve the effect of electrical isolation.

On the basis of the above-mentioned embodiments, various modified embodiments are further proposed. It should be noted here that, for the sake of brevity, only differences from the above-mentioned embodiments are described in each modified embodiment.

According to some embodiments of the present invention, the thickness of the first isolation layer 9 is smaller than the thickness of the second isolation layer 10 .

According to some embodiments of the present invention, the thickness of the first isolation layer 9 is 30-150 nm, which is mainly adjusted according to the requirement of the threshold voltage of the device.

According to some embodiments of the present invention, the thickness of the second isolation layer 10 is 0.1-0.8 um, because it needs to bear a relatively large withstand voltage, so a relatively thick thickness is required.

According to some embodiments of the present invention, the first isolation layer 9 and the second isolation layer 10 are gate oxide layers.

According to some embodiments of the present invention, the source wiring of the source polysilicon layer and the oxide layer of the third isolation layer 12 are formed by HDP deposition.

According to some embodiments of the present invention, the gate polysilicon layer 7 is a P-type heavily doped layer, and the source polysilicon layer 8 is an N-type lightly doped layer.

According to some embodiments of the present invention, the doping impurity of the gate polysilicon layer 7 is boron or aluminum.

According to some embodiments of the present invention, the doping impurity of the source polysilicon layer is phosphorus or arsenic, and the doping concentration is 1E15-1E17cm ^-3 , by controlling the doping concentration, the integrated PN junction diode and Schottky diode can be regulated The breakdown voltage ensures that the breakdown voltage is lower than the voltage of the first isolation layer.

According to some embodiments of the present invention, the Schottky barrier metal can be one of titanium, nickel, vanadium, platinum or other suitable metals, and generally low barrier metals are used to ensure that the source polysilicon layer and the source The connection resistance of the pole metal layer (the first metal layer) is the lowest, so as to achieve the shielding effect on the grid.

According to some embodiments of the present invention, the contact area between the Schottky barrier metal and the first metal layer can be adjusted, and the larger the contact area, the greater the anti-ESD effect of the device.

According to some embodiments of the present invention, the above embodiments are all N-channel devices, and for P-channel VDMOS devices, it is only necessary to form the corresponding N-type and P-type regions, which will not be described in detail here.

The VDMOS device of the present invention will be described in detail in a specific embodiment with reference to FIG. 1 below. It should be understood that the following description is only an illustration rather than a specific limitation to the present invention. All similar structures and similar changes of the present invention should be included in the protection scope of the present invention.

In this embodiment, the VDMOS device includes: a substrate 1 which is an N-type heavily doped layer. The epitaxial layer 2 is grown on one side of the substrate layer 1, and the epitaxial layer 2 is an N-type lightly doped layer. The P-body layer 3 is disposed on the side of the epitaxial layer 2 away from the substrate layer 1, and this layer is a P-type lightly doped layer. The ohmic contact layer 4 is disposed on the side of the P-body layer 3 away from the epitaxial layer 2 , and this layer is a P-type heavily doped layer for providing an ohmic contact. The source electron layer 5 is juxtaposed with the ohmic contact layer 4 and is arranged on the side of the P-body layer 3 away from the epitaxial layer 2. This layer is an N-type heavily doped layer and is used for device operation Provides source electrons. The first metal layer 6 covers the ohmic contact layer 4 and the source electron layer 5 , and is electrically connected to the ohmic contact layer 4 and the source electron layer 5 . A channel is disposed between the first metal layer 6 and the epitaxial layer 3 , the channel is close to the side of the source electron layer 5 away from the ohmic contact layer 4 . The channel occupies part of the space of the epitaxial layer 2 , which can be obtained by etching or processing the epitaxial layer 2 in the production process. The gate polysilicon layer 7 adopts a P-type heavily doped structure, and an in-situ doping process can be used, and the doped impurity is boron. The gate polysilicon layer 7 is arranged in the channel, and is connected to the first metal layer 6 and the Both the P-body layer 3 and the source electron layer 5 are isolated by the first isolation layer 9, and the thickness of the first isolation layer is 30-150 nm. The first isolation layer 9 is mainly used to provide electrical isolation between gate and source. The source polysilicon layer 8 adopts an N-type lightly doped structure, doped with phosphorus as an impurity, and is doped by ion implantation with a doping concentration of 1E15-1E17cm ^-3 , and the source polysilicon layer 8 is arranged on the gate The side of the polysilicon layer 7 away from the first metal layer 6 is isolated from the epitaxial layer 2 by a second isolation layer 10, the thickness of the second isolation layer is 0.1-0.8um. The head end of the gate polysilicon layer 7 is flush with the head end of the source polysilicon layer 8, and the tail end of the source polysilicon layer 8 is connected to the first metal layer 6 through the second metal layer 11, The second metal layer 11 is a Schottky barrier metal, and the Schottky barrier metal is titanium. The tail end of the gate polysilicon layer 7 is isolated from the tail end of the source polysilicon layer 8 by the third isolation layer 12, and the depth of the third isolation layer 12 in the direction from the first metal layer 6 to the substrate layer 2 is It should be greater than the depth of the gate polysilicon layer 7, that is, the bottommost position of the third isolation layer 12 should be lower than the bottommost position of the gate polysilicon layer 7, so as to achieve the effect of electrical isolation.

Using the technical solution of this embodiment, the gate polysilicon diode is integrated in the trench, and the oxide layer isolation of the traditional structure is transformed into a new type of PN junction isolation, wherein the gate polysilicon layer adopts a P+ type structure, and the source polysilicon layer adopts N -type structure, and at the same time, a Schottky barrier contact is used at the connection between the source polysilicon layer and the first metal layer, which prevents direct conduction between the gate and the source. Its equivalent circuit is shown in Figure 2, between the gate G and the source S there is a PN junction diode D1 formed by the gate polysilicon layer and the source polysilicon layer, and a Schottky barrier metal formed by the source polysilicon layer. Tertky diode S1, in this way, when a forward voltage is applied between GS, the Schottky diode S1 reverses the cut-off effect of gate-source electrical isolation, and when a reverse voltage is applied between GS, the PN junction diode D1 reverses the cut-off function of the gate-source Electrical isolation effect, and when the device is in the blocking state, the gate-source poles are short-circuited. Due to the high potential of the drain D, the PN junction diode D1 and the Schottky diode S1 are both in the cut-off state, and the Schottky leakage is larger than the PN leakage. About 3 orders of magnitude make the connection resistance between the gate polysilicon layer and the source electrode smaller, and achieve the effect of reducing the Maitreya capacitance.

When the diode structure reverses breakdown, the current rises very fast, so the current leakage capability of the diode is significantly stronger than that of the dielectric oxide layer, and because the breakdown of the oxide layer has damage characteristics, as time accumulates, the damage position is connected to form a leakage channel , the device is damaged, and the diode can break down repeatedly, and the anti-ESD ability of the diode is obviously stronger than that of the dielectric oxide layer. In the embodiment of the present invention, the breakdown voltage of the integrated PN junction diode D1 and Schottky diode S1 is lower than the breakdown voltage of the gate oxide layer. When ESD comes, the diode D1 or S1 breaks down first, and the energy is directly transferred from the parasitic between the gate and source. The diode is released, which can effectively improve the anti-ESD capability of the shielded gate VDMOS.

It should be noted that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

It should be noted that, in the description of this specification, well-known methods, structures and technologies are not shown in detail, so as not to obscure the understanding of this specification.

Claims (8)

1. A VDMOS device, comprising:

the substrate layer is an N-type heavily doped layer;

the epitaxial layer grows on one side of the substrate layer, and is an N-type lightly doped layer;

the P-body layer is arranged on one side of the epitaxial layer, which is far away from the substrate layer;

the ohmic contact layer is arranged on one side of the P-body layer, which is far away from the epitaxial layer;

the source electrode electronic layer is parallel to the ohmic contact layer and is arranged on one side, away from the epitaxial layer, of the P-body layer;

the first metal layer covers the ohmic contact layer and the source electrode electronic layer and is electrically connected with the ohmic contact layer and the source electrode electronic layer;

the channel is arranged between the first metal layer and the epitaxial layer and is close to one side, far away from the ohmic contact layer, of the source electrode electronic layer;

the grid polycrystalline silicon layer is arranged in the channel and is isolated from the first metal layer, the P-body layer and the source electrode electronic layer through a first isolation layer;

the source polycrystalline silicon layer is arranged on one side of the grid polycrystalline silicon layer, which is far away from the first metal layer, and is isolated from the epitaxial layer through a second isolation layer;

the head end of the grid polycrystalline silicon layer is flush with the head end of the source polycrystalline silicon layer, the tail end of the source polycrystalline silicon layer is connected with the first metal layer through a second metal layer, and the second metal layer is Schottky barrier metal; the tail end of the grid polycrystalline silicon layer is isolated from the tail end of the source polycrystalline silicon layer through a third isolation layer, and the depth of the third isolation layer in the direction from the first metal layer to the substrate layer is larger than that of the grid polycrystalline silicon layer.

2. The VDMOS device of claim 1, wherein a thickness of the first isolation layer is less than a thickness of the second isolation layer.

3. The VDMOS device of claim 2, wherein the first isolation layer has a thickness of 30-150nm.

4. The VDMOS device of claim 2, wherein the second isolation layer has a thickness of 0.1-0.8um.

5. The VDMOS device of claim 1, wherein the gate polysilicon layer is a heavily P-doped layer and the source polysilicon layer is a lightly N-doped layer.

6. The VDMOS device of claim 5, wherein the doping impurity of the gate polysilicon layer is boron or aluminum.

7. The VDMOS device of claim 5, wherein the source polysilicon layer is doped with phosphorus or arsenic at a concentration of 1E15-1E17cm ^-3 。

8. The VDMOS device of claim 1, wherein the schottky barrier metal is titanium or nickel.

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