CN115935878A - Multi-bit data computing circuit, chip and computing device based on analog signal - Google Patents

Abstract

The embodiment of the disclosure discloses a multi-bit data calculation circuit, a chip and a calculation device based on analog signals, wherein the circuit comprises: a preset number of computing unit groups and a preset number of adding unit groups; for each computing unit group in a preset number of computing unit groups, the computing unit group corresponds to the target adding unit group and has corresponding accumulated weight, and the output end of each computing unit is connected with the input end of the corresponding adding unit; the target addition unit group is used for distributing corresponding digit weight for each calculation unit in the calculation unit group, accumulating the calculation result signals output by each calculation unit according to the corresponding digit weight, and outputting the accumulation result signals through the signal output end of the addition unit group; the addition unit groups in the preset number of addition unit groups each comprise different proportion relations of characteristic metric values of the addition units. The embodiment of the disclosure is beneficial to reducing the area and power consumption of the whole computing circuit.

Description

Multi-bit data computing circuit, chip and computing device based on analog signal

technical field

The present disclosure relates to the technical field of integrated circuit design, in particular to a multi-bit data computing circuit, chip and computing device based on analog signals.

Background technique

The integrated storage and calculation array based on the analog signal domain plays an important role in the multiply-accumulate (MAC, Multiply Accumulate) operation. This calculation method is often used in deep neural network algorithms to perform intensive multiply-accumulate operations, and this calculation The method has the advantages of high parallelism and low power consumption. Signals in the analog signal domain include current domain, charge domain, and time domain. At present, the commonly used analog signal in the storage and calculation integrated array is the charge domain signal. This is because the processing precision of the capacitor in the integrated circuit is high. Compared with the other two analog signals, the calculation method of the charge domain using the capacitor has a relatively good linearity.

The currently adopted charge-domain multiplication-accumulation scheme including capacitors, the capacitance values of multiple capacitors corresponding to each single-bit storage data (such as a bit in the weight data in the neural network scenario) are in accordance with 1:2:4:8 ..., so that, according to the principle of capacitive voltage division, the same single-bit stored data is multiplied by each single-bit of the multi-bit input data, and then superposition of the products is realized according to the corresponding weight.

Contents of the invention

An embodiment of the present disclosure provides a multi-bit data computing circuit based on an analog signal, the circuit includes: a preset number of computing unit groups and a preset number of adding unit groups; for each of the preset number of computing unit groups A calculation unit group, the calculation unit group corresponds to the target addition unit group, and has a corresponding cumulative weight, the output end of each calculation unit in the calculation unit group is connected to the input end of the corresponding addition unit; the target addition unit group It is used to assign a corresponding digital weight to each computing unit in the computing unit group, and accumulate the calculation result signal output by each computing unit according to the corresponding digital weight, and output the accumulated result signal through the signal of the adding unit group Terminal output, wherein, the digital weight corresponding to each calculation unit is determined based on the characteristic measurement value and cumulative weight of each addition unit in the target addition unit group; each addition unit group in the preset number of addition unit groups includes each The scaling relationship of the characteristic measures of the summing unit is different.

In some embodiments, the circuit also includes a preset number of analog-to-digital converters and shift accumulators, wherein each analog-to-digital converter in the preset number of analog-to-digital converters corresponds to an adding unit group; preset Each of the number of analog-to-digital converters is used to receive the accumulation result signal output by the corresponding adding unit group, generate a digital signal according to the received accumulation result signal, and send the obtained digital signal to the shift accumulator ; The shift accumulator is used to perform shift and accumulation operations on the received second preset number of digital signals respectively according to the corresponding accumulation weights to obtain multi-bit accumulation result data.

In some embodiments, for a computing unit group in a preset number of computing unit groups, each computing unit included in the computing unit group corresponds to a storage unit, the storage unit is used to store single-bit storage data, and each computing unit uses The calculation is performed on the single-bit data in the corresponding storage unit and the input single-bit input data, and the calculation result signal is input to the corresponding addition unit.

In some embodiments, the computing unit groups in the preset number of computing unit groups are composed of multipliers, and the multipliers are used to perform multiplication calculations on the single-bit storage data in the corresponding storage units and the input single-bit input data, and output calculations result signal.

In some embodiments, the multiplier includes a first switch and a second switch, and the first switch is used to use the input single-bit input data as the first data when the single-bit storage data in the storage unit corresponding to the multiplier is the first data. The result signal is output, and the second switch is used to output the preset level as the calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the second data.

In some embodiments, for the adding unit groups in the preset number of adding unit groups, the adding unit included in the adding unit group is the capacitance value of the capacitor, and the characteristic measurement value of the adding unit is the capacitance value; or, the adding unit The adding unit included in the group is a transistor, and the characteristic measure value of the adding unit is a transconductance parameter of the transistor.

In some embodiments, for the adding unit groups in the preset number of adding unit groups, if the adding unit group is composed of capacitors, the accumulated result signal output by the adding unit group is a voltage signal, and the modulus corresponding to the adding unit group The converter is used to convert the voltage signal into a digital signal; if the adding unit group is composed of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used to convert the current signal into a digital signal Signal.

According to another aspect of an embodiment of the present disclosure, a chip is provided, and the chip includes the above-mentioned multi-bit data calculation circuit based on an analog signal.

According to another aspect of the embodiments of the present disclosure, there is provided a computing device, the computing device including the above-mentioned chip.

The multi-bit data computing circuit, chip and computing device based on analog signals provided by the above-mentioned embodiments of the present disclosure have a preset number of computing unit groups and a preset number of adding unit groups in the circuit, and each computing unit group corresponds to one addition The unit group, the addition unit group assigns a corresponding digital weight to each calculation unit in the corresponding calculation unit group, and accumulates the calculation result signal output by each calculation unit according to the corresponding digital weight, and outputs the accumulated result signal through the signal terminal output, the digital weight corresponding to each calculation unit is determined based on the characteristic measurement value and cumulative weight of each addition unit in the corresponding addition unit group, and each addition unit group in the preset number of addition unit groups includes each The scaling relationship of the characteristic measures of the summing unit is different. Compared with the current multi-bit data multiplication and accumulation circuit based on analog signals, the embodiment of the present disclosure does not need to distribute the addition units in each addition unit group according to the same proportional relationship, and realizes multi-bit storage data and multi-bit Based on the calculation and accumulation of the input data, the sum of the special measurement values of the addition unit is reduced, avoiding the problem of exponential growth of the characteristic measurement value of the addition unit with the increase of the bit width of the calculation data, which in turn helps to reduce the overall Calculate the area and power dissipation of the circuit.

The technical solution of the present disclosure will be described in further detail below with reference to the drawings and embodiments.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the present disclosure, and do not constitute limitations to the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

Fig. 1 is the structural representation of the existing multi-bit data multiplication and accumulation circuit based on analog signals;

Fig. 2 is a schematic structural diagram of a multi-bit data calculation circuit based on an analog signal provided by an exemplary embodiment of the present disclosure;

Fig. 3 is a schematic diagram of calculation rules for multiplying four-bit stored data and four-bit input data provided by an exemplary embodiment of the present disclosure;

Fig. 4 is another schematic structural diagram of an analog signal-based multi-bit data calculation circuit provided by an exemplary embodiment of the present disclosure;

Fig. 5 is another schematic structural diagram of an analog signal-based multi-bit data calculation circuit provided by an exemplary embodiment of the present disclosure;

Fig. 6 is a schematic diagram of the connection relationship between the storage unit, the calculation unit and the addition unit provided by an exemplary embodiment of the present disclosure;

Fig. 7 is a schematic structural diagram of a multiplication unit provided by an exemplary embodiment of the present disclosure;

Fig. 8 is another schematic structural diagram of an analog signal-based multi-bit data calculation circuit provided by an exemplary embodiment of the present disclosure.

Detailed ways

Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited by the exemplary embodiments described here.

It should be noted that relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc. necessary logical sequence.

It should also be understood that in the embodiments of the present disclosure, "plurality" may refer to two or more than two, and "at least one" may refer to one, two or more than two.

It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more unless there is a clear limitation or a contrary suggestion is given in the context.

In addition, the term "and/or" in the present disclosure is only an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B may indicate: A exists alone, and A and B exist simultaneously , there are three cases of B alone. In addition, the character "/" in the present disclosure generally indicates that the contextual objects are an "or" relationship.

It should also be understood that the description of the various embodiments in the present disclosure emphasizes the differences between the various embodiments, and the same or similar points can be referred to each other, and for the sake of brevity, details are not repeated here.

At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

The following description of at least one exemplary embodiment is merely illustrative in nature and in no way intended as any limitation of the disclosure, its application or uses.

Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the description.

It should be noted that like numerals and letters denote like items in the following figures, therefore, once an item is defined in one figure, it does not require further discussion in subsequent figures.

FIG. 1 shows an exemplary schematic diagram of a current multiply-accumulate operation circuit based on analog signals. As shown in Figure 1, K four-bit weight data and four-bit input data are multiplied and accumulated. The SRAM (Static Random-Access Memory, Static Random-Access Memory) unit in the figure stores single-bit weight data W _i [3:0], i is the row number. The weight data of the same rank is stored in the same column, and the multiplication and addition results of different columns have different digital weights (satisfying the binary proportional relationship 1:1/2:1/4:1/8).

The multiplication unit in the figure is used to realize the multiplication of input data I _i [3:0] and weight data W _i [3:0]. The output end of each multiplication unit is connected to a capacitor, and the capacitance value satisfies the binary proportional relationship to realize the weight relationship of the input data. For example, for four-bit input data, the capacitance ratios of the capacitors corresponding to the four are 8:4:2:1. According to the principle of capacitor voltage division, such capacitor arrangement can make the multiplication and addition result expressed as I _i [3 ]×W×8/16+ I _i [2]×W×4/16+ I _i [1]×W×2/16+ I _i [0]×W×1/16, thus realizing the multiplication result according to The weights corresponding to the four bits of data are accumulated. The capacitor not connected to the multiplication unit in the figure is a dummy capacitor, and the function of this capacitor is to cooperate with other capacitors to adjust the digital weight.

It can be seen from Figure 1 that the current multiplication and accumulation operation circuit based on analog signals has the following disadvantages:

1. Using the binary proportional relationship of capacitance to realize the weight of multi-bit input data, it will face the problem of exponential growth of capacitance value when processing high-bit-width input, thus limiting the bit-width of input data.

2. The total capacitance of the capacitors in this solution is relatively large, which increases the area and power consumption of the computing array, and reduces the area efficiency and energy efficiency of the integrated storage and computing array. Taking the four-bit data operation in Figure 1 as an example, when each row implements four-bit data multiplication, the required capacitance is 4×(8C+4C+2C+1C+1C)=64C (C is the capacitance of a unit capacitance).

The embodiment of the present disclosure aims to solve the above problems, and proposes a multi-bit data calculation circuit based on an analog signal. The proportional relationship of the characteristic measurement value of the unit is different. For example, when calculating and accumulating four-bit data, it is not necessary to distribute each addition unit group according to the proportional relationship of 8:4:2:1, so as to solve the problem of high bit width data calculation. The problem of exponential growth of the characteristic measure value improves the area utilization efficiency and energy utilization efficiency of the circuit.

exemplary structure

Fig. 2 is a schematic structural diagram of an analog signal-based multi-bit data calculation circuit provided by an exemplary embodiment of the present disclosure. The various components included in the circuit can be integrated into one chip, or can be arranged in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

As shown in Figure 2, the circuit includes: a preset number of computing unit groups (including 201, 203, 205, 207, 209) and a preset number of adding unit groups (including 202, 204, 206, 208, 210). Wherein, each calculation unit group corresponds to an addition unit group. The preset number can be set as required. As shown in Figure 2, when performing multiplication operation on four-bit input data I _i [3:0] and four-bit storage data W _i [3:0], the number of calculation units required is 16, 16 calculation units and The corresponding adding units are divided into 5 columns, and each column includes a plurality of computing units and a plurality of adding units corresponding to a group of computing units and a group of adding units, that is, the preset number is five.

The calculation units included in the calculation unit group can perform any type of calculation as required. For example, the computing unit may be a multiplier, configured to perform multiplication operations on input single-bit input data and single-bit stored data. Optionally, the calculation unit can also perform calculations such as addition, exclusive OR, and exclusive OR.

The addition unit group is used for accumulating the calculation result signals output by the corresponding calculation units in the analog signal domain. The adding units included in the adding unit group can be composed of any type of devices, as shown in FIG. 2 , the adding units are capacitors.

It should be noted that the number of calculation units and the number of addition units included in the corresponding calculation unit group and the addition unit group can be the same or different, as shown in Figure 2, in order to assign weights to the calculation result signals of the calculation unit group, A dummy capacitor can be added, that is, a capacitor with one end connected to the ground and the other end connected to the signal output terminal as shown in the figure.

In this embodiment, for each computing unit group in the preset number of computing unit groups, the computing unit group corresponds to the target adding unit group and has a corresponding accumulation weight, and each computing unit in the computing unit group The output terminal of is connected with the input terminal of the corresponding adding unit.

Wherein, the target adding unit group is one of the preset number of adding unit groups, as shown in FIG. 2 , for computing unit group 201 , its corresponding target adding unit group is 202 . The accumulative weight corresponding to the calculation unit group means that after the corresponding addition unit group outputs the accumulation result signal, the data represented by the accumulation result signal is multiplied by the corresponding accumulation weight, so that the accumulation data corresponding to the calculation unit group can be obtained.

As shown in FIG. 2 , the accumulated weights corresponding to the five computing unit groups are 1, 1/2, 1/4, 1/8, and 1/16 respectively. It should be noted that the accumulation weights shown in Figure 2 are relative weights, that is, the accumulation weights corresponding to the signal output terminals of two adjacent adding unit groups can satisfy the relationship of 2 times. In the controller, the absolute weight can be set according to actual needs, so as to complete the calculation of the actual scene.

The above-mentioned target addition unit group is used to assign corresponding digital weights to each calculation unit in the corresponding calculation unit group, and accumulate the calculation result signal output by each calculation unit according to the corresponding digital weight, and pass the accumulated result signal through the The signal output terminal of the adding unit group outputs, wherein the digital weight corresponding to each calculation unit is determined based on the characteristic measurement value and the accumulation weight of each adding unit in the target adding unit group.

As an example, as shown in FIG. 2, when the adding unit is a capacitor, the characteristic measurement value of the adding unit is the capacitance of the capacitor, and 1C, 2C, etc. shown in FIG. 2 represent the capacitance of the capacitor. For a computing unit in a certain computing unit group, its corresponding digital weight is determined by the ratio of the capacitance of the capacitor connected to it to the total capacitance of the corresponding adding unit group. For example, for the calculation unit 2011 in the calculation unit group 201 in FIG. 2, its corresponding digital weight is 8C/(8C+4C+2C+1C+1C)=1/2. For the calculation unit 2012 in FIG. 2, The corresponding digital weight is 4C/(8C+4C+2C+1C+1C)=1/4.

In this embodiment, the proportional relationship of the characteristic measure values of the adding units included in each adding unit group of the preset number of adding unit groups is different.

As shown in Figure 2, for the addition unit group 202, the proportional relation of the characteristic measure value of each addition unit wherein is 8:4:2:1:1, for the addition unit group 204, the characteristic measure value of each addition unit wherein The ratio relationship is 2:1:1. Similarly, the proportional relationships of the characteristic measure values of the respective adding units in other adding unit groups are 1:1:1:1, 1:1:1:1, 2:2:1:3 respectively.

Compared with the existing analog signal-based multiplication and accumulation calculation circuit shown in Figure 1, each column also includes a calculation unit group (composed of multiplication units) and an addition unit group (composed of capacitors), as shown in Figure 1 The proportional relationship of the characteristic measurement values of each adding unit in the adding unit group is equal, which is 8:4:2:1:1. The total characteristic measure of the summing unit required for the circuit shown in Figure 1 is 4 x (8C + 4C + 2C + 1C + 1C) = 64C. However, in this embodiment, by reorganizing the positions of the calculation unit and the addition unit, and redistributing the proportional relationship of each addition unit group, the total characteristic measurement value can be reduced. The circuit provided by this embodiment as shown in Figure 2 has a total characteristic The measured value is (8C+4C+2C+1C+1C)+ (2C+1C+1C)+(1C+1C+1C+1C)+ (1C+1C+1C+1C) +(2C+2C+1C+ 3C)=36C, compared to the circuit shown in Figure 1, the overall characteristic measure is greatly reduced.

Next, based on the principle of multiplying the four-bit input data and the four-bit weight data, the principle of allocating the capacitance values of the capacitors in the circuit shown in FIG. 2 will be described. As shown in FIG. 3 , it shows a calculation rule for multiplying four-bit stored data W _i [3:0] and four-bit input data I _i [3:0]. Each column of values (that is, single-bit product) shown in Figure 3 corresponds to a product weight, and the final product of W _i [3:0] and I _i [3:0] is the multiplication of each single-bit product by the corresponding product weight Then add them up. The product weight corresponding to each single-bit product shown in FIG. 3 is equal to the digital weight of the corresponding adding unit in FIG. 2 multiplied by the corresponding accumulation weight.

For example, for I _i [3]*W _i [3], the corresponding digital weight is 1/2, and the corresponding cumulative weight is 1, then the corresponding product weight is 1/2;

For I _i [2]*W _i [2], the corresponding digital weight is 1/4, the corresponding cumulative weight is 1/2, and the corresponding product weight is 1/8;

For I _i [1]*W _i [1], the corresponding digital weight is 1/4, the corresponding accumulation weight is 1/8, and the corresponding product weight is 1/16.

It should be noted that the distribution of each calculation unit and each addition unit shown in FIG. 2 is only an example. Optionally, when multi-bit data is multiplied and calculated, the multi-bit calculation rule shown in FIG. 3 is satisfied, and the multi-bit calculation rule shown in FIG. On the basis that the columns shown in 3 are arranged in a binary manner, the distribution of each calculation unit and each addition unit can be adjusted as required. For example, the computing units and capacitors corresponding to I _i [0] and W _i [3] in Figure 2 can be set in the third column (that is, the column with a cumulative weight of 1/4), and the virtual The capacitor is deleted, and the capacitance of the virtual capacitor grounded in the first column is set to 2C, then the product weight corresponding to I _i [0] and W _i [3] is still 1/4 * 1/4 = 1/16.

The circuits provided by the above-mentioned embodiments of the present disclosure are provided with a preset number of computing unit groups and a preset number of adding unit groups, each computing unit group corresponds to an adding unit group, and the adding unit group is each of the corresponding computing unit groups The corresponding digital weights are assigned to each calculation unit, and the calculation result signal output by each calculation unit is accumulated according to the corresponding digital weight, and the accumulated result signal is output through the signal output terminal, and the corresponding digital weight of each calculation unit is based on the corresponding addition. The characteristic measurement value and accumulation weight of each adding unit in the unit group are determined, and the proportional relationship of the characteristic measurement value of each adding unit included in each adding unit group in the preset number of adding unit groups is different. Compared with the current multi-bit data multiplication and accumulation circuit based on analog signals, the embodiment of the present disclosure does not need to distribute the addition units in each addition unit group according to the same proportional relationship, and realizes multi-bit storage data and multi-bit Based on the calculation and accumulation of the input data, the sum of the special measurement values of the addition unit is reduced, avoiding the problem of exponential growth of the characteristic measurement value of the addition unit with the increase of the bit width of the calculation data, which in turn helps to reduce the overall Calculate the area and power dissipation of the circuit.

In some optional implementation manners, as shown in FIG. 4 , the circuit further includes a preset number of analog-to-digital converters 211 and shift accumulators 212 . Wherein, each analog-to-digital converter in the preset number of analog-to-digital converters 211 corresponds to one adding unit group.

Each analog-to-digital converter in the preset number of analog-to-digital converters 211 is used to receive the accumulation result signal output by the corresponding adding unit group, generate a digital signal according to the received accumulation result signal, and send the obtained digital signal to the mobile station. bit accumulator 212 .

The shift accumulator 212 is configured to perform shift and accumulation operations on the second preset number of received digital signals respectively according to corresponding accumulation weights to obtain multi-bit accumulation result data.

As an example, as shown in FIG. 2, for the accumulation result signal output by the addition unit group 202, the signal represents the accumulation of the calculation results (such as multiplication calculation results) output by each calculation unit in the calculation unit group 201, and the corresponding modulus A converter can convert this analog signal to a digital signal.

Each digital signal corresponds to an accumulation weight respectively. According to the calculation rules of multi-bit multiplication shown in FIG. 1, 1/2, 1/4, 1/8, 1/16) are multiplied (for example, by shifting), and then the products are added together to obtain a multi-bit input data and a multi-bit storage data product of . For example, the multi-bit accumulation result data shown in FIG. 2 is the product of I _i [3:0]*W _i [3:0].

In this embodiment, by setting an analog-to-digital converter and a shift accumulator, the accumulation result signal of the analog signal domain output by each adding unit group is converted into a digital signal, and the digital signal is accumulated according to the corresponding accumulation weight to obtain a digital signal. The multi-bit accumulation result signal in the signal domain helps to further process the multi-bit accumulation result signal in the digital signal domain, and expands the application field of the multi-bit data calculation circuit.

Optionally, as shown in Figure 5, the circuit shown in Figure 2 can be set to multiple groups, according to the circuit shown in Figure 5, a plurality of computing unit groups and adding unit groups corresponding to the same accumulation weight are set to A column, the output terminals of all the adding unit groups of the column are connected to the same accumulation line, thereby realizing the calculation and accumulation of multiple multi-bit input data and multi-bit storage data.

As shown in Figure 5, the accumulation result signal output by the same accumulation line represents the accumulation of the calculation results output by K+1 computing unit groups respectively, and the accumulation result signal output by each accumulation line is input to the corresponding analog-to-digital converter to obtain a digital Each digital signal is then input into the shift accumulator, and the shift accumulator calculates the multi-bit accumulation result data of multiple multi-bit input data and multi-bit stored data according to the corresponding accumulation weight, that is, when the calculation unit is used to execute a single During bit multiplication calculation, the multi-bit accumulation result data output by the circuit shown in Figure 5 is W ₀ [3:0]* I ₀ [3:0]+ W ₁ [3:0]* I ₁ [3:0]+ …+W _K [3:0]* I _K [3:0].

The circuit shown in Figure 5 can be applied to an integrated storage and calculation array, thereby realizing the calculation of multiple multi-bit data and helping to reduce the area and power consumption of the integrated storage and calculation array.

In some optional implementation manners, for a computing unit group in a preset number of computing unit groups, each computing unit included in the computing unit group corresponds to a storage unit, and the storage unit is used to store single-bit storage data, each The calculating unit is used for calculating the single-bit data in the corresponding storage unit and the input single-bit input data, and inputting the calculation result signal into the corresponding adding unit.

As shown in Figure 6, one input end of the calculation unit is connected to the storage unit, the storage unit is used to store a single-bit storage data, such as W _i [0], and the other input end of the calculation unit is used to receive a single-bit input data , such as I _i [0], the calculation unit outputs the calculation result signal to the addition unit.

In this embodiment, by arranging the storage unit, the storage unit and the calculation unit can be configured as a storage and calculation unit, thereby realizing a storage and calculation unit array. Since the storage and calculation unit array includes the circuit shown in FIG. 2, this embodiment can reduce the storage and calculation unit array. Calculate the area and power consumption of the cell array.

In some optional implementations, the computing unit groups in the preset number of computing unit groups are composed of multipliers, and the multipliers are used to perform multiplication calculations on the single-bit storage data in the corresponding storage unit and the input single-bit input data , output the calculation result signal.

Among them, the multiplier can be realized by circuits with various structures. For example, the multiplier is implemented by circuits such as double N-type field effect transistors, N-type P-type combined field effect transistors, and the like. The working process of the multiplier is: when the single-bit storage data (such as W _i [0]) in the storage unit is 1, the multiplier is turned on, and the input single-bit input data (such as I _i [0]) is directly output to the corresponding addition unit; when the single-bit storage data in the storage unit is 0, the output terminal of the multiplier is connected to the preset level (such as low level), that is, the output represents the level of digital 0 to the corresponding addition unit.

In this embodiment, by setting the calculation unit as a multiplier, each calculation unit can perform multiplication calculation of single-bit storage data and single-bit input data, and the accumulation result signal output by each addition unit group is the multiplication and accumulation result signal, and then To realize multi-bit data multiplication and accumulation calculation based on analog signals, the circuit structure of this embodiment is simple and effective, and helps to efficiently perform multi-bit data multiplication and accumulation calculation on the basis of reducing the area and power consumption of the multiplication and accumulation calculation circuit.

In some optional implementation manners, the multiplier includes a first switch and a second switch, and the first switch is used to input the input single bit when the single-bit storage data in the storage unit corresponding to the multiplier is the first data The data is output as a calculation result signal, and the second switch is used to output a preset level as a calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the second data.

Wherein, the first data may be 1, the second data may be 0, and the preset level may be low level. As shown in FIG. 7 , a calculation unit is a multiplier composed of a first switch 701 and a second switch 702 . Both the first switch 701 and the second switch 702 are N-type MOS transistors, the gates of the first switch 701 and the second switch 702 are respectively connected to the Q terminal and the QB terminal of the storage unit 703, and the Q terminal outputs the stored single-bit data , the QB terminal outputs the inverted data of the single-bit data.

The specific working process is: when Q is 1, QB is 0, the first switch 701 is turned on, the second switch 702 is turned off, and the input single-bit input data (such as I _i [0]) is directly output to the addition unit 704; When Q is 0, QB is 1, the first switch 701 is turned off, and the second switch 702 is turned on. Since the drain of the second switch 702 is grounded, the signal input to the adding unit 704 is a low-level signal, thereby realizing Multiplication calculation of single-bit stored data and single-bit input data.

It should be noted that the multiplier composed of two N-type MOS transistors shown in FIG. 7 is only an example. On the premise that the multiplication calculation can be realized, the types of the first switch and the second switch can be set arbitrarily, for example Can be triode.

In this embodiment, the first switch and the second switch are configured to form a multiplier, which can realize the multiplication calculation of single-bit storage data and single-bit input data through a simple circuit, and the circuit is easier to implement and the circuit operation is more stable.

In some optional implementation manners, for an adding unit group in the preset number of adding unit groups, the adding unit included in the adding unit group is a capacitance value of a capacitor, and the characteristic measurement value of the adding unit is a capacitance value; or, The adding unit included in the adding unit group is a transistor, and the characteristic measurement value of the adding unit is a transconductance parameter of the transistor.

The adding units in the circuit shown in Figure 2-Figure 5 include all adding units that are capacitors, through which the proportional superposition of the charge domain (that is, voltage) can be realized at the signal output terminal.

As shown in FIG. 8 , it shows a schematic diagram of a multi-bit data calculation circuit in which the addition unit is a transistor. The adding unit in FIG. 8 is an N-type MOS transistor, and the output signal terminal can be superimposed in the current domain through the transconductance parameter of the MOS transistor. The transconductance parameters of each MOS transistor in FIG. 8 are expressed as 8k, 4k, 2k, and 1k, which realizes the distribution of weights for the calculation result signals in the current domain. As shown in Figure 8, the cumulative result signal output by the signal output terminals of each adding unit group is a current signal. For an adding unit group composed of MOS transistors, the current output by the adding unit group is equivalent to the calculation of the output of each calculation unit The superposition of the product of the result signal and the shunt ratio (that is, the digital weight) (I _sum4 , I _sum3 , I _sum2 , I _sum1 , I _sum0 ), the shunt ratio is the transconductance parameter of a single MOS transistor and the total transconductance parameter of each MOS transistor Ratio.

As an example, for the first row of MOS tubes 801, the corresponding accumulation weight is 1, the digital weights corresponding to each MOS tube are 8/15, 4/15, 2/15, 1/15, and the corresponding product weights are 8 /15, 4/15, 2/15, 1/15.

For the second row of MOS tubes 802, the corresponding accumulation weight is 8/15, the digital weights corresponding to each MOS tube are 2/4, 1/4, 1/4, and the corresponding product weights are 4/15, 2/ 15, 2/15;

For the third row of MOS tubes 803, the corresponding cumulative weight is 1/5, the digital weights corresponding to each MOS tube are 1/3, 1/3, 1/3, and the corresponding product weights are 1/15, 1/3, respectively. 15, 1/15;

For the fourth row of MOS tubes 804, the corresponding cumulative weight is 1/10, the digital weights corresponding to each MOS tube are 1/3, 1/3, 1/3, and the corresponding product weights are 1/30, 1/3 30, 1/30;

For the fifth row of MOS tubes 805, the corresponding cumulative weight is 1/24, the digital weights corresponding to each MOS tube are 2/5, 2/5, 1/5, and the corresponding product weights are 1/60, 1/5 60, 1/120.

Based on the above example, combined with the calculation rules for multiplying the four-bit stored data W _i [3:0] and the four-bit input data I _i [3:0] shown in Figure 3, it can be seen that each multiplication in Figure 3 The factor corresponds to each data in Figure 8, and the product weight between the columns in Figure 3 is still 2 times. In the analog-to-digital converter and shift accumulator, the absolute weight can be set according to actual needs, so as to complete the actual Scenario calculations.

For example, for I _i [3]*W _i [2], the corresponding digital weight is 2/4, the corresponding cumulative weight is 8/15, and the corresponding product weight is 4/15;

For I _i [2]*W _i [2], the corresponding digital weight is 1/4, the corresponding cumulative weight is 8/15, and the corresponding product weight is 2/15;

For I _i [1]*W _i [2], the corresponding digital weight is 1/3, the corresponding cumulative weight is 3/15, and the corresponding product weight is 1/15.

In this embodiment, by using capacitors or transistors as the addition unit, the superposition of analog signals in the charge domain or current domain is realized. On the basis of reducing the area and power consumption of the circuit, the flexibility of circuit design is further improved, and the application is expanded. Scenes.

In some optional implementations, for the adding unit groups in the preset number of adding unit groups, if the adding unit group is composed of capacitors, the cumulative result signal output by the adding unit group is a voltage signal, and the adding unit group corresponds to The analog-to-digital converter is used to convert the voltage signal into a digital signal;

If the adding unit group is composed of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used to convert the current signal into a digital signal.

In this embodiment, different types of analog-to-digital converters are set according to different types of accumulated result signals, which further improves the flexibility of circuit design, so that multi-bit computing circuits based on different types of analog signals can reduce the area and power consumption of the circuit , expanding the application field of the circuit.

Embodiments of the present disclosure also provide a chip on which a multi-bit data calculation circuit based on an analog signal is integrated. The technical details of the multi-bit data calculation circuit based on an analog signal are shown in FIGS. 1-8 and related descriptions. No further description here.

Embodiments of the present disclosure also provide a computing device, which includes the chip described in the above embodiments. In addition, the computing device may also include an input device, an output device, and necessary memory. Wherein, the input device may include, for example, a mouse, a keyboard, a touch screen, a communication network connector, etc., and is used for inputting multi-bit input data, multi-bit stored calculation data, and the like. The output device may include, for example, a display, a printer, a communication network and a remote output device connected thereto, etc., for outputting multi-bit accumulation result data and the like. The memory is used to store the data input by the above-mentioned input device, and the data generated during the operation of the multi-bit data calculation circuit based on the analog signal. Memory may include volatile memory and/or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like.

The basic principles of the present disclosure have been described above in conjunction with specific embodiments, but it should be pointed out that the advantages, advantages, effects, etc. mentioned in the present disclosure are only examples rather than limitations, and these advantages, advantages, effects, etc. Various embodiments of the present disclosure must have. In addition, the specific details disclosed above are only for the purpose of illustration and understanding, rather than limitation, and the above details do not limit the present disclosure to be implemented by using the above specific details.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other.

The block diagrams of devices, devices, devices, and systems involved in the present disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, devices, systems may be connected, arranged, configured in any manner. Words such as "including", "comprising", "having" and the like are open-ended words meaning "including but not limited to" and may be used interchangeably therewith. As used herein, the words "or" and "and" refer to the word "and/or" and are used interchangeably therewith, unless the context clearly dictates otherwise. As used herein, the word "such as" refers to the phrase "such as but not limited to" and can be used interchangeably therewith.

It is possible to implement the circuits of the present disclosure in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order of the above specific description, unless otherwise specified. Furthermore, in some embodiments, the present disclosure can also be implemented as programs recorded in recording media including machine-readable instructions for realizing the functions of the circuits according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the functions of the circuit according to the present disclosure.

It should also be pointed out that in the circuit of the present disclosure, each component or each step can be decomposed and/or reassembled. These decompositions and/or recombinations should be considered equivalents of the present disclosure.

The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the disclosed embodiments to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims (9)

1. A multi-bit data computing circuit based on an analog signal, comprising: a preset number of computing unit groups and a preset number of adding unit groups; For each computing unit group in the preset number of computing unit groups, the computing unit group corresponds to the target adding unit group and has a corresponding accumulation weight, and the output terminal of each computing unit in the computing unit group is connected to the The input terminal of the corresponding addition unit is connected; The target addition unit group is used to assign corresponding digital weights to each calculation unit in the calculation unit group, and to accumulate the calculation result signals output by each calculation unit according to the corresponding digital weights, and pass the accumulated result signals through the The signal output terminal of the adding unit group outputs, wherein the digital weight corresponding to each calculation unit is determined based on the characteristic measurement value of each adding unit in the target adding unit group and the accumulation weight; Each of the adding unit groups included in the preset number of adding unit groups has a different proportional relationship of characteristic measure values of each adding unit. 2. The circuit according to claim 1, wherein the circuit further comprises a preset number of analog-to-digital converters and a shift accumulator, wherein each analog-to-digital converter in the preset number of analog-to-digital converters The converter corresponds to an addition unit group; Each of the preset number of analog-to-digital converters is used to receive the accumulation result signal output by the corresponding adding unit group, generate a digital signal according to the received accumulation result signal, and send the obtained digital signal to said shift accumulator; The shift accumulator is used to perform shift and accumulation operations on the received second preset number of digital signals respectively according to corresponding accumulation weights to obtain multi-bit accumulation result data. 3. The circuit according to claim 1, wherein, for a computing unit group in the preset number of computing unit groups, each computing unit included in the computing unit group corresponds to a storage unit, and the storage unit is used for Store single-bit storage data, and each calculation unit is used to perform calculations on the single-bit data in the corresponding storage unit and the input single-bit input data, and input the calculation result signal to the corresponding addition unit. 4. The circuit according to claim 3, wherein the computing unit groups in the preset number of computing unit groups are composed of multipliers, and the multipliers are used for storing data and inputting the single bit in the corresponding storage unit The single-bit input data is multiplied, and the calculation result signal is output. 5. The circuit according to claim 4, wherein the multiplier comprises a first switch and a second switch, and the first switch is used for storing data of a single bit in the storage unit corresponding to the multiplier as the first When there is one data, the input single-bit input data is output as a calculation result signal, and the second switch is used to set the preset level Output as a calculation result signal. 6. The circuit according to claim 1, wherein, for the adding unit groups in the preset number of adding unit groups, the adding unit included in the adding unit group is the capacitance of a capacitor, and the characteristic measurement value of the adding unit is is a capacitance value; or, the adding unit included in the adding unit group is a transistor, and the characteristic measurement value of the adding unit is a transconductance parameter of the transistor. 7. The circuit according to claim 6, wherein, for the adding unit groups in the preset number of adding unit groups, if the adding unit group is composed of capacitors, the cumulative result signal output by the adding unit group is a voltage signal , the analog-to-digital converter corresponding to the adding unit group is used to convert the voltage signal into a digital signal; If the adding unit group is composed of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used to convert the current signal into a digital signal. 8. A chip, characterized by comprising the multi-bit data calculation circuit based on an analog signal according to any one of claims 1-7. 9. A computing device comprising the chip according to claim 8.

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