CN115881540B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structureInfo
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- CN115881540B CN115881540B CN202111138938.6A CN202111138938A CN115881540B CN 115881540 B CN115881540 B CN 115881540B CN 202111138938 A CN202111138938 A CN 202111138938A CN 115881540 B CN115881540 B CN 115881540B
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Abstract
一种半导体结构的形成方法，包括：提供衬底，所述衬底包括基底、位于部分所述基底表面的鳍部，以及位于所述鳍部顶部表面的硬掩膜层；去除所述硬掩膜层；去除所述硬掩膜层后，采用外延生长工艺在所述鳍部表面形成第一保护层；形成所述第一保护层后，在所述衬底表面形成隔离结构层，所述隔离结构层位于部分所述鳍部侧壁，且所述隔离结构层顶部表面低于所述鳍部顶部表面。在形成第一保护层前，去除硬掩膜层，使所述鳍部表面具有均匀的第一保护层材料的外延生长点，利于提高所形成的第一保护层的均匀性，且避免了外延生长工艺中可能引入的刻蚀过程给所述鳍部带来的刻蚀损伤，从而提高了工艺窗口。
A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base, a fin located on a portion of the surface of the base, and a hard mask layer located on the top surface of the fin; removing the hard mask layer; after removing the hard mask layer, forming a first protective layer on the surface of the fin using an epitaxial growth process; after forming the first protective layer, forming an isolation structure layer on the surface of the substrate, the isolation structure layer being located on a portion of the sidewall of the fin, and the top surface of the isolation structure layer being lower than the top surface of the fin. Removing the hard mask layer before forming the first protective layer allows for uniform epitaxial growth points of the first protective layer material on the surface of the fin, which improves the uniformity of the formed first protective layer and avoids etching damage to the fin that may be introduced during the epitaxial growth process, thereby improving the process window.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
In the existing semiconductor field, a fin field effect transistor (FinFET) is an emerging multi-gate device, and compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger working current, and is widely applied to various semiconductor devices.
With the continuous development of semiconductor technology, the gate size of the fin field effect transistor is also continuously reduced. At this time, the distribution width of the boron and phosphorus doped ions becomes an important factor affecting the Short Channel Effect (SCE) of the fin field effect transistor.
The performance of semiconductor structures formed using existing fin field effect transistors is in need of improvement.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, removing a hard mask layer, forming a first protection layer on the surface of a fin portion by adopting an epitaxial growth process after the hard mask layer is removed, and forming an isolation structure layer on the surface of the substrate after the first protection layer is formed, wherein the isolation structure layer is positioned on part of the side wall of the fin portion, and the top surface of the isolation structure layer is lower than the top surface of the fin portion.
Optionally, the method for removing the hard mask layer comprises the steps of forming a cover layer on the surface of the substrate, wherein the cover layer exposes the top of the hard mask layer, taking the cover layer as a mask, removing the hard mask layer, and removing the cover layer after the hard mask layer is removed.
Optionally, before forming the cover layer, forming a second protective layer on the surface of the substrate.
Optionally, the material of the second protective layer includes a dielectric material, where the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Optionally, the material of the second protective layer includes a carbonaceous material, wherein the percentage concentration of carbon atoms ranges from 15% to 80%.
Optionally, the forming process of the second protective layer includes an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the cover layer also exposes a part of the second protection layer on the surface of the hard mask layer, and after the cover layer is formed and before the hard mask layer is removed, the method further comprises removing the exposed second protection layer to expose a part of the surface of the hard mask layer.
Optionally, the process of removing the second protective layer exposed by the capping layer includes one or a combination of a dry etching process and a wet etching process.
Optionally, the process for removing the second protective layer exposed by the covering layer comprises a plasma etching process, wherein the process parameters of the plasma etching process comprise that etching gas comprises carbon fluoride, oxygen and carbon hydrofluoride, no bias voltage or low-frequency bias voltage is adopted, and the power range of the low-frequency bias voltage is lower than or equal to 100 watts.
Optionally, after removing the cover layer and before forming the first protective layer, removing the second protective layer on the surface of the substrate to expose the surface of the fin portion.
Optionally, the process of removing the second protective layer of the substrate surface includes one or a combination of a dry etching process and a wet etching process.
Optionally, the process for removing the second protective layer on the surface of the substrate comprises a plasma etching process, wherein the process parameters of the plasma etching process comprise that etching gas comprises first etching gas, and the first etching gas comprises fluorine-containing gas, chlorine-containing gas and bromine-containing gas.
Optionally, the etching gas further comprises a second etching gas, wherein the second etching gas comprises one or more of sulfur oxide, oxygen, argon, helium and carbon dioxide.
Optionally, the material of the cover layer is different from the material of the hard mask layer, and the material of the cover layer includes spin-coated carbon and bottom anti-reflection material.
Optionally, the material of the cover layer is different from the material of the hard mask layer, the material of the cover layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Optionally, the forming method of the covering layer comprises the steps of forming a dielectric material layer on the surface of the substrate, wherein the top surface of the dielectric material layer is higher than the top surface of the hard mask layer, planarizing the dielectric material layer until the top surface of the hard mask layer is exposed, and etching back the dielectric material layer after the planarization process.
Optionally, the process of removing the hard mask layer includes one or a combination of a dry etching process and a wet etching process.
Optionally, the etching selection ratio of the process for removing the hard mask layer to the hard mask layer and the fin portion is greater than 10:1.
Optionally, the process of removing the hard mask layer includes a remote plasma process.
Optionally, the forming process of the first protective layer comprises a selective epitaxial growth process, wherein the selective epitaxial growth process comprises a plurality of film forming processes, and each film forming process comprises a material film forming process and an etching process after the material film is formed.
Optionally, the fin material includes one or a combination of silicon and silicon germanium.
Optionally, the material of the first protective layer includes silicon.
Optionally, after the isolation structure layer is formed, the method further comprises the step of oxidizing the surface of the first protection layer to form a protection material layer and a gate oxide layer positioned on the protection material layer, wherein the thickness of the protection material layer ranges from 1 angstrom to 15 angstrom.
Optionally, the first protection layer comprises a protection material layer and a sacrificial layer positioned on the protection material layer, the material of the protection material layer comprises silicon, and the material of the sacrificial layer comprises a dielectric material, wherein the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, before the first protective layer is formed, the hard mask layer is removed, and as the hard mask layer is removed to expose the top surface of the fin part, in the process of forming the first protective layer on the surface of the fin part by adopting an epitaxial growth process, the surface of the fin part is provided with uniform epitaxial growth points of the first protective layer material, so that the uniformity of the formed first protective layer is improved, and etching damage to the fin part due to an etching process possibly introduced in the epitaxial growth process is avoided, thereby improving a process window.
Further, before the covering layer is formed, a second protective layer is further formed on the surface of the substrate, and the second protective layer is used for protecting the surface of the fin portion, so that etching damage to the fin portion when the covering layer is removed is reduced.
Further, the process for removing the hard mask layer comprises a remote plasma process, which is beneficial to reducing etching damage to the surface of the fin part.
Further, the process for removing the second protective layer exposed by the covering layer comprises a plasma etching process, and the plasma etching process adopts no bias voltage or low-frequency bias voltage, so that etching damage to the surface of the fin part is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure forming process;
FIG. 2 is a schematic cross-sectional view of another semiconductor structure formation process;
Fig. 3 to 9 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background, performance enhancement is needed for semiconductor structures formed using existing FinFET technology. Analysis will now be described in connection with a semiconductor structure.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure forming process.
Referring to fig. 1, a substrate is provided, wherein the substrate includes a base 100, a fin portion located on a portion of a surface of the base 100, and a hard mask layer 103 located on a top surface of the fin portion, the fin portion includes a bottom structure 101 and a channel layer 102 located on the bottom structure 101, and a protection layer 104 is formed on the surface of the fin portion by a non-selective epitaxy process.
In the above method, the material of the bottom structure 101 of the fin portion is silicon, the material of the channel layer 102 is germanium silicon or silicon, and the material of the protection layer 104 is monocrystalline silicon. In the non-selective epitaxial process, since the lattice matching rate of the silicon material with the fin portion is high and the lattice of the silicon material is not matched with the lattice of the hard mask layer 103, a single crystal silicon thin film layer is formed on the surface of the fin portion, and a large amount of amorphous silicon thin film layers are formed on the surface of the hard mask layer 103, wherein the forming speed of the amorphous silicon thin film layers is higher than that of the single crystal silicon thin film layers. In addition, the amorphous silicon thin film layer on the sidewall of the hard mask layer 103 is difficult to be etched later, so that a residual amorphous silicon material is formed on the sidewall of the hard mask layer 103, thereby generating a defect a shown in fig. 1, which affects the performance of the formed device, such as causing leakage of the device.
In order to reduce the occurrence of the defect a, in another embodiment, the protection layer is formed by a non-selective epitaxy process, refer to fig. 2.
Fig. 2 is a schematic cross-sectional view of another semiconductor structure formation process.
Referring to fig. 2, a substrate is provided, wherein the substrate includes a base 200, a fin portion located on a portion of the surface of the base 200, and a hard mask layer 203 located on a top surface of the fin portion, the fin portion includes a bottom structure 201 and a channel layer 202 located on the bottom structure 201, and a protective layer 204 is formed on the surface of the fin portion by using a selective epitaxy process.
The present embodiment is different from the previous embodiment in that the protection layer 204 is formed by a selective epitaxy process. The selective epitaxy process comprises a plurality of film forming processes, wherein each film forming process comprises a material film forming process and an etching process after the material film is formed.
In the selective epitaxy process, the amorphous silicon thin film layer on the surface of the hard mask layer 203 can be removed by an etching process after the material film is formed, however, the fin portion is also easily etched by the etching process, so that a fillet B (shown in fig. 2) phenomenon is generated at the top corner of the fin portion, and the roughness of the surface of the side wall of the fin portion is higher.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, in which before forming a first protection layer, a hard mask layer is removed, and the hard mask layer is removed to expose the top surface of a fin portion, so that in the process of forming the first protection layer on the surface of the fin portion by using an epitaxial growth process, the surface of the fin portion has an epitaxial growth point of a uniform first protection layer material, which is beneficial to improving the uniformity of the formed first protection layer, and avoiding etching damage to the fin portion due to an etching process possibly introduced in the epitaxial growth process, thereby improving a process window.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 9 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate is provided, and the substrate includes a base 200, a fin 201 located on a portion of a surface of the base 200, and a hard mask layer 202 located on a top surface of the fin 201.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The fin 201 is formed by providing an initial substrate (not shown), forming a channel epitaxial material layer (not shown) on the initial substrate, forming a hard mask layer 202 on the surface of the channel epitaxial material layer, exposing a part of the surface of the channel epitaxial material layer, etching the channel epitaxial material layer and the initial substrate by taking the hard mask layer 202 as a mask, forming a substrate 200 and the fin 201 on the surface of the substrate, wherein the fin 201 comprises a bottom structure I and an epitaxial layer II on the bottom structure I, forming the epitaxial layer II by the epitaxial material layer, and forming the substrate 200 and the bottom structure I by the initial substrate.
The material of the fin 201 includes one or a combination of silicon and silicon germanium. The fin 201 is used to form a channel of the device. Specifically, in this embodiment, the material of the epitaxial layer II is silicon germanium, and the material of the bottom structure I is silicon.
The material of the hard mask layer 202 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the hard mask layer 202 is silicon nitride.
Subsequently, the hard mask layer 202 is removed. In this embodiment, please refer to fig. 4 to 7 for a method of removing the hard mask layer 202.
Referring to fig. 4, a cover layer 203 is formed on the surface of the substrate, and the cover layer 203 exposes the top of the hard mask layer 202.
The material of the cover layer 203 is different from the material of the hard mask layer 202. The cover layer 203 is used for protecting the substrate during the etching process of removing the hard mask layer 202, so as to reduce the etching damage to the bottom.
In this embodiment, the material of the cover layer 203 includes spin-on carbon and bottom anti-reflection material.
In this embodiment, the material of the cover layer 203 is spin-coated carbon, and the cover layer 203 has good fluidity and can well cover the surface of the substrate.
In other embodiments, the material of the capping layer is different from the material of the hard mask layer, and the material of the capping layer includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In other embodiments, the method for forming the covering layer includes forming a first dielectric material layer on the surface of the substrate, wherein the top surface of the first dielectric material layer is higher than the top surface of the hard mask layer, planarizing the first dielectric material layer until the top surface of the hard mask layer is exposed, and etching back the first dielectric material layer after the planarization process.
In this embodiment, before forming the cover layer 203, a second protective layer 204 is further formed on the surface of the substrate. The material of the second protective layer 204 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
The second protection layer 204 is used for protecting the surface of the fin 201, so as to reduce etching damage to the fin 201 when the cover layer 203 is removed later.
The material of the second protective layer 204 includes a carbon-containing material, wherein the percentage concentration of carbon atoms ranges from 15% to 80%.
The second protective layer 204 is formed by an atomic layer deposition process or a chemical vapor deposition process. The atomic layer deposition process or the chemical vapor deposition process has better conformality and is beneficial to forming uniform material films.
In this embodiment, the cover layer 203 further exposes a portion of the second protection layer 204 on the surface of the hard mask layer 202.
In this embodiment, before removing the hard mask layer 202, please refer to fig. 5.
Referring to fig. 5, after the cover layer 203 is formed and before the hard mask layer 202 is removed, the exposed second protection layer 204 is also removed, so that a portion of the surface of the hard mask layer 202 is exposed.
The process of removing the second protective layer 204 exposed by the capping layer 203 includes one or a combination of a dry etching process and a wet etching process.
In this embodiment, the process of removing the second protection layer 204 exposed by the cover layer 203 includes a plasma etching process, and the process parameters of the plasma etching process include that the etching gas includes carbon fluoride, oxygen, and carbon hydrofluoride, and no bias voltage or low-frequency bias voltage is provided, and the power range of the low-frequency bias voltage is less than or equal to 100 watts. The plasma etching process adopts bias-free voltage or low-frequency bias voltage, which is beneficial to reducing etching damage to the surface of the fin part.
Referring to fig. 6, the hard mask layer 202 is removed by using the cover layer 203 as a mask.
The process of removing the hard mask layer 202 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of removing the hard mask layer 202 is a wet etching process. In the wet etching process, the etching liquid comprises phosphoric acid.
The etching selectivity of the process for removing the hard mask layer 202 to the hard mask layer 202 and the fin 201 is greater than 10:1. The purpose of selecting the etching selection ratio range is to reduce etching damage to the fin 201 during the process of removing the hard mask layer 202.
In another embodiment, the process of removing the hard mask layer includes a remote plasma process. The remote plasma process is beneficial to reducing etching damage to the fin surface.
Referring to fig. 7, after removing the hard mask layer 202, the cover layer 203 is removed.
In this embodiment, the process of removing the cover layer 203 is a gray hair process. In other embodiments, the process of removing the capping layer 203 includes one or a combination of a dry etching process and a wet etching process.
Subsequently, after the cover layer 203 is removed, a first protection layer is formed on the surface of the fin 201.
In this embodiment, after removing the cover layer 203 and before forming the first protective layer, the second protective layer 204 on the surface of the substrate is also removed, so as to expose the surface of the fin 201.
The process of removing the second protective layer 204 of the substrate surface includes one or a combination of a dry etching process and a wet etching process.
In this embodiment, the process of removing the second protective layer 204 on the substrate surface includes a plasma etching process, and the process parameters of the plasma etching process include that the etching gas includes a first etching gas, and the first etching gas includes a gas containing fluorine, chlorine and bromine.
In other embodiments, the etching gas further comprises a second etching gas comprising one or more of sulfur oxide, oxygen, argon, helium, carbon dioxide.
Referring to fig. 8, after removing the hard mask layer 202, an epitaxial growth process is used to form a first protection layer 205 on the surface of the fin 201.
In this embodiment, specifically, after the second protection layer 204 on the surface of the substrate is removed, an epitaxial growth process is used to form a first protection layer 205 on the surface of the fin 201.
Because the hard mask layer 202 is removed before the first protective layer 205 is formed, the top surface of the fin 201 is exposed, and in the process of forming the first protective layer 205 on the surface of the fin 201 by adopting the epitaxial growth process, the surface of the fin 201 has uniform epitaxial growth points of the first protective layer 205 material, which is favorable for improving the uniformity of the formed first protective layer 205, and avoids the etching damage to the fin 201 caused by the etching process possibly introduced in the epitaxial growth process, thereby improving the process window.
In this embodiment, the first protection layer 205 is formed by a selective epitaxial growth process including a plurality of film forming processes, each of which includes forming a material film and etching after forming the material film.
In another embodiment, the first protection layer 205 is formed by a non-selective epitaxial growth process.
The material of the first protective layer 205 includes silicon.
In this embodiment, the first protection layer 205 is a single layer. The first protection layer 205 is used to reduce the surface state density of the fin 201 and improve the performance of the device. Meanwhile, the first protection layer 205 also provides a material for forming a gate oxide layer later. In other embodiments, the first protective layer may be a plurality of layers.
In another embodiment, the first protective layer comprises a protective material layer and a sacrificial layer positioned on the protective material layer, the material of the protective material layer comprises silicon, and the material of the sacrificial layer comprises a dielectric material, wherein the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. The sacrificial layer is used for protecting the protective material layer in the subsequent etching process of forming the isolation structure layer. The protective material layer is used for reducing the surface state density of the fin part and improving the performance of the device.
Referring to fig. 9, after the first protection layer 205 is formed, an isolation structure layer 206 is formed on the surface of the substrate, the isolation structure layer 206 is located on a portion of the sidewalls of the fin 201, and the top surface of the isolation structure layer 206 is lower than the top surface of the fin 201.
The material of the isolation structure layer 206 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the isolation structure layer 206 is silicon oxide.
The method for forming the isolation structure layer 206 includes forming a second dielectric material layer on the surface of the substrate, wherein the dielectric material layer is higher than the top surface of the fin 201, planarizing the second dielectric material layer until the top surface of the fin 201 is exposed, and etching back the second dielectric material layer after the planarization process until the top surface of the second dielectric material layer is lower than the top surface of the fin 201. Specifically, in this embodiment, the top surface of the isolation structure layer 206 is higher than the top surface of the bottom structure I and lower than the top surface of the epitaxial layer II.
In this embodiment, after the isolation structure layer 206 is formed, the surface of the first protection layer 205 is oxidized to form a protection material layer (not shown) and a gate oxide layer (not shown) on the protection material layer, where the thickness of the protection material layer ranges from 1 angstrom to 15 angstrom. Specifically, the protection material layer is used to reduce the surface state density of the fin 201, so as to improve the performance of the device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (24)
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| CN109427684A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and method |
| CN110890279A (en) * | 2018-09-11 | 2020-03-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
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| DE102017126435B4 (en) * | 2017-08-31 | 2022-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FIN FIELD EFFECT TRANSISTOR DEVICE AND METHOD |
| US10622475B2 (en) * | 2018-07-19 | 2020-04-14 | International Business Machines Corporation | Uniform bottom spacer for VFET devices |
| CN112017960B (en) * | 2019-05-28 | 2024-09-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN109427684A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and method |
| CN110890279A (en) * | 2018-09-11 | 2020-03-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
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