CN115863183B - Manufacturing method of micro-flow channel with measurable flow for heat dissipation of three-dimensional integrated wafer system - Google Patents

Abstract

The invention discloses a manufacturing method of a micro-flow channel with measurable flow for heat dissipation of a three-dimensional integrated wafer system, which comprises the following steps: the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of the silicon wafer on the insulator, and constructing a force-sensitive resistor and a temperature measuring resistor; releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide of the oxygen-buried layer below the release hole by a wet method to form a micro-channel; a release hole electroplated copper sealing step: depositing seed layer metal on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel; and (3) carrying out inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro-channel by using a chemical method.

Description

Flow-measurable microfluidic fabrication method for heat dissipation in 3D integrated wafer systems

technical field

The present application relates to the field of electronic technology, in particular to a method for manufacturing a flow-measureable microfluidic channel for heat dissipation of a three-dimensional integrated wafer system.

Background technique

In the "post-Moore era", with the development of advanced packaging technology, different chips can be integrated through high-density three-dimensional stacking, which greatly improves the performance of the system. However, a high-density integrated system will generate a lot of heat, which seriously affects the normal operation of the chip. In recent years, people have begun to use microfluidic channels loaded with cooling fluid to dissipate heat inside three-dimensionally integrated chips. A traditional method is to etch the groove structure of the microchannel on the back of the chip, and then align and bond with another silicon wafer or glass sheet with the groove structure of the microchannel etched to form the microchannel. Closed pipeline; Another common practice is to coat the back of the chip with organic polymer and etch the groove structure of the microfluidic channel, and then bond it with other linings to form a closed microfluidic pipeline. Traditional methods require the introduction of additional substrates and bonding processes, which not only increases the complexity of the process but also increases the thickness of the chip.

Contents of the invention

In view of the problems existing in the prior art, the purpose of the embodiment of this application is to provide a method for preparing a wafer cooling microfluidic channel with a piezoresistive flow detection function, which is developed based on a silicon-on-insulator (SOI, Silicon-On-Insulator) wafer The silicon dioxide buried oxide layer sacrificial release process has been implemented, which does not need to be filled with organic polymers, and only relies on the device layer silicon, buried oxide layer silicon dioxide, and substrate layer silicon of the SOI wafer to form a closed microfluidic channel; the development The electroplating copper sealing process and the selective electroless copper plating process on the inner wall are adopted, and the formed copper column heat sink and metallized copper layer on the inner wall greatly improve the heat dissipation capacity of the micro-channel; at the same time, the invention also integrates piezoresistive in the micro-channel The flowmeter can detect the flow rate and temperature of the coolant microfluid in real time.

According to the first aspect of the embodiment of the present application, there is provided a method for manufacturing a microfluidic channel with measurable flow rate for heat dissipation of a three-dimensional integrated wafer system, including:

Manufacturing steps of the piezoresistive flowmeter: constructing a first force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer and constructing a force-sensitive resistor and a temperature-measuring resistor;

The silicon dioxide buried oxide layer release step: etching a release hole on the upper surface of the silicon-on-insulator wafer, and etching the silicon dioxide buried oxide layer below the release hole by a wet method to form a microfluidic channel;

Release hole electroplating copper sealing step: deposit seed layer metal on the upper surface of the silicon-on-insulator wafer and the sidewall of the release hole, and form copper pillars to seal the upper surface of the microchannel based on the seed layer copper plating ;

The step of inorganic copper plating on the inner wall of the micro-channel: using a chemical method to plate a copper heat dissipation layer on the upper and lower surfaces of the inner wall of the micro-channel.

Further, the silicon-on-insulator wafer is the backside of an active integrated circuit or a backside of a silicon wafer interposer with completed silicon vertical vias and a rewiring layer.

Further, the manufacturing steps of the piezoresistive flowmeter include:

Forming a first force-sensitive strain structure by photolithography etching on the upper surface of the silicon-on-insulator wafer, and the first force-sensitive strain structure is a cantilever beam, a folded beam-plate or a film with holes;

forming a semiconductor force sensitive resistor on the first force sensitive strain structure by ion implantation;

forming a temperature measuring resistor by depositing metal near the force sensitive resistor;

Chromium/gold is sputtered to form the ohmic contact electrode of the force sensitive resistor and the interconnection line of the temperature measuring resistor, and the first passivation layer silicon dioxide is deposited by plasma enhanced chemical vapor deposition.

Further, the step of releasing silicon dioxide from the buried oxide layer includes:

Photoetching release holes and coolant inlet and outlet holes on the upper surface of the silicon-on-insulator wafer;

Coating a thick photoresist on the outer sidewall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper surface of the silicon-on-insulator, wherein the thickness of the thick photoresist is ≥ 10 microns;

The silicon dioxide buried oxide layer under the release hole is wet-etched through the release hole and the cooling liquid inlet and outlet holes to form a micro flow channel for the cooling liquid to flow in the horizontal direction.

Further, the release hole electroplating copper sealing step includes:

Depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the sidewalls of the release holes;

growing copper in the release hole by electroplating to form a copper pillar heat sink;

peeling off the thick photoresist on the surface, wherein the thickness of the thick photoresist is ≥ 10 microns;

A second passivation layer silicon dioxide is deposited on the lower surface of the silicon-on-insulator wafer.

Further, the step of inorganic copper plating on the inner wall of the microchannel comprises:

Immersing the silicon-on-insulator wafer into the electroless copper plating solution forms an upper surface copper deposition layer and a lower surface copper deposition layer on the upper and lower surfaces of the inner wall of the micro flow channel.

Further, the electroless copper plating solution includes an activation solution and a reaction solution, the silicon-on-insulator wafer is first immersed in the activation solution for activation, and then immersed in the reaction solution for copper plating, wherein the composition of the activation solution Comprising deionized water, hydrofluoric acid and palladium chloride, the components of the reaction solution include copper sulfate and formaldehyde.

Further, a vibration compensation step is also included, the vibration compensation step is arranged before the buried oxide layer silicon dioxide release step, and this step includes:

On the outside of the micro-flow channel, a second force-sensitive strain structure is constructed on the upper surface of the silicon-on-insulator wafer, so as to eliminate errors caused by vibrations in fluid pressure measurement.

Further, after the step of inorganic copper plating on the inner wall of the micro-channel, the silicon dioxide of the second passivation layer is removed.

According to the second aspect of the embodiment of the present application, there is provided an application of the microfluidic channel with measurable flow rate for the heat dissipation of the three-dimensional integrated wafer system manufactured according to the method described in the first aspect, which is used to prepare a silicon vertical Silicon wafer interposer with via or redistribution layers for 3D vertical stack integration of multilayer integrated circuit chips or wafers.

The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

First, this application directly manufactures microfluidic channels on the back of the wafer based on SOI wafers, without bonding with other silicon wafers or glass sheets with microchannels to form microchannels, which reduces the complexity of the process;

Second, the present application skillfully developed a sacrificial release process based on SOI wafer buried oxide layer silicon dioxide, which does not need to be filled with organic polymers, but only relies on the device layer silicon, buried oxide layer silicon dioxide and liner of SOI wafer. The underlying silicon can form a microfluidic closed circuit;

Thirdly, this application has skillfully developed the copper electroplating sealing process and the selective electroless copper plating process on the inner wall. The copper plating process can deposit a copper layer on the upper and lower surfaces of the inner wall of the microchannel to further improve the heat dissipation capacity of the inner wall of the microchannel;

Fourth, the present application has developed a piezoresistive flowmeter integrated with the microchannel crystal, and has the functions of temperature compensation and vibration compensation, and can monitor the flow rate and temperature of the cooling liquid in real time.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

Fig. 1 is a flow chart of a method for manufacturing a microfluidic channel with measurable flow rate for heat dissipation in a three-dimensional integrated wafer system according to an exemplary embodiment, wherein (a) in Fig. 1 - (h) in Fig. 1 are Schematic diagram of the structure of each process in the flow-measurable microfluidic channel manufacturing method for the heat dissipation of the three-dimensional integrated wafer system.

Fig. 2 is a schematic diagram of a vibration compensation structure according to an exemplary embodiment.

Fig. 3 is a schematic top view of a flow-measurable microfluidic channel used for heat dissipation in a three-dimensional integrated wafer system according to an exemplary embodiment.

Fig. 4 is a schematic diagram of an embodiment of a flow-measurable microfluidic channel used for heat dissipation of a three-dimensional integrated wafer system in the field of three-dimensional integration application according to an exemplary embodiment.

In the figure: 1. SOI wafer; 2. The first force-sensitive strain structure; 3. Force-sensitive resistor; 4. Temperature measuring resistor; 5. The first passivation layer silicon dioxide; 6. Release hole; 7. Buried oxygen layer of silicon dioxide; 8. Coolant inlet and outlet holes; 9. Thick photoresist; 10. Micro flow channel; 11. Closed cylinder; 12. Second passivation layer of silicon dioxide; 13. Copper deposition layer on the upper surface; 14. Copper deposition layer on the lower surface; 15. Second force-sensitive strain structure; 16. Integrated circuit chip; 17. Micro-bump; 18. Rewiring layer; 19. Silicon vertical via.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application.

The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word "if" as used herein may be interpreted as "at" or "when" or "in response to a determination."

Fig. 1 is a flow chart of a method for manufacturing a microfluidic channel with measurable flow rate for heat dissipation in a three-dimensional integrated wafer system according to an exemplary embodiment. As shown in Fig. 1 , the method may include the following steps:

Manufacturing steps of the piezoresistive flowmeter: constructing a first force-sensitive strain structure 2 on the upper surface of the silicon-on-insulator wafer and constructing a force-sensitive resistor 3 and a temperature-measuring resistor 4;

Buried oxide layer silicon dioxide 7 release step: etching the release hole 6 on the upper surface of the silicon-on-insulator wafer, and wet etching the buried oxide layer silicon dioxide 7 below the release hole 6 to form a microfluidic channel 10;

Release hole 6 electroplating copper sealing step: deposit a seed layer metal on the upper surface of the silicon-on-insulator wafer and the sidewall of the release hole 6, and form copper pillars to seal the microchannel 10 based on the seed layer copper plating the upper surface of

Inorganic copper plating step on the inner wall of the micro-channel 10 : plating a copper heat dissipation layer on the upper and lower surfaces of the inner wall of the micro-channel 10 by chemical method.

From the above embodiments, it can be seen that the present application directly manufactures microfluidic passages on the back of the wafer based on the SOI wafer 1, and does not need to be bonded with other silicon wafers or glass sheets with microchannels 10 to form microchannels 10, which reduces the complexity of the process. Ingeniously developed a sacrificial release process based on the buried oxide layer silicon dioxide 7 of the SOI wafer 1, which does not need to be filled with organic polymers, but only relies on the device layer silicon of the SOI wafer 1, the buried oxide layer silicon dioxide 7 and The substrate layer silicon can form the micro-channel 10 closed pipeline; the electroplating copper sealing process and the inner wall selective electroless copper plating process have been skillfully developed, wherein the electroplated copper column structure can not only close the micro-channel 10 side wall, but also form a thermal The sinking structure improves the heat dissipation capability; the selective electroless copper plating process on the inner wall can deposit a copper layer on the upper and lower surfaces of the inner wall of the microchannel 10, further improving the heat dissipation capacity of the inner wall of the microchannel 10; Resistance flowmeter, and has the function of temperature compensation and vibration compensation, which can monitor the flow rate and temperature of coolant in real time.

In the specific implementation of the piezoresistive flowmeter manufacturing steps, the first force-sensitive strain structure 2 is constructed on the upper surface of the silicon-on-insulator (SOI) wafer, and the force-sensitive resistor 3 and the temperature-measuring resistor 4 are constructed;

As shown in FIG. 1 , microfluidic channels 10 are fabricated starting from a silicon-on-insulator (SOI) wafer ((a) in FIG. 1 ), which may already have active integrated circuits The backside of the silicon wafer interposer can also be the backside of the silicon wafer interposer on which the through-silicon vertical vias 19 (TSV) and the redistribution layer 18 (RDL) have been completed. This step can specifically include the following processes:

Form the first force-sensitive strain structure 2 by photolithography etching on the upper surface of the silicon wafer on insulator, and the first force-sensitive strain structure 2 is a cantilever beam, a folded beam-flat plate or a film with holes; A semiconductor force sensitive resistor 3 is formed by ion implantation on a force sensitive strain structure 2; a temperature measuring resistor 4 is formed by depositing metal near the force sensitive resistor 3; an ohmic contact of the force sensitive resistor 3 is formed by sputtering chromium/gold For electrodes and interconnection lines, the first passivation layer silicon dioxide 5 is deposited by plasma enhanced chemical vapor deposition. In a specific implementation, it is preferable to sputter chromium/platinum to form the temperature measuring resistor 4, and it is preferable to sputter chromium/gold to form the ohmic contact electrodes and interconnection lines of the force sensitive resistor 3, preferably plasma enhanced chemical vapor deposition (PECVD) deposition The first passivation layer is silicon dioxide 5 ((b) in FIG. 1 ).

Before the silicon dioxide 17 release step of the buried oxide layer, the method may also include a vibration compensation step, which may include:

On the outside of the micro-channel 10, a second force-sensitive strain structure 15 is constructed on the upper surface of the silicon-on-insulator wafer to eliminate errors caused by vibrations in fluid pressure measurement.

FIG. 2 shows the vibration compensation structure of the micro-channel 10 of the micro-channel 10 capable of measuring flow velocity, pressure and temperature according to the present invention. Since the first force-sensitive strain structure 2 has a certain degree of vibration sensitivity, in order to eliminate the error caused by vibration to the measurement of fluid pressure, it can be fabricated at a nearby position outside the micro-channel 10 that is similar to the first force-sensitive strain structure 2 . Structure 2 has a second force-sensitive strain structure 15 with the same mechanically sensitive structure. The second force-sensitive strain structure 15 also has a force-sensitive resistor 3 and a temperature-measuring resistor 4. The specific formation process is the same as that of the piezoresistive flowmeter. The steps are the same and will not be repeated here. The force-sensitive resistor 3 on the second force-sensitive strain structure 15 only feels the change of the piezoresistive resistance value caused by the vibration without being affected by the microfluid, so that the piezoresistive resistance value measured by the two force-sensitive resistors 3 can be used to calculate Eliminate vibration effects.

In the specific implementation of the step of releasing the buried oxide layer silicon dioxide 7, the release hole 6 is etched on the upper surface of the silicon-on-insulator wafer, and the buried oxide layer silicon dioxide 7 below the release hole 6 is etched by a wet method , forming a microchannel 10;

Specifically, the release hole 6 and the cooling liquid inlet and outlet hole 8 are photoetched on the upper surface of the silicon-on-insulator wafer; A thick photoresist 9 is coated on the passivation layer silicon dioxide 5, wherein the thickness of the thick photoresist 9 is more than or equal to 10 microns. In specific implementation, the thickness of the photoresist depends on the thickness of the steps. The wall thickness of the flow channel generally selects a device layer SOI wafer greater than 5 microns, so the thickness of the thick photoresist 9 of the present application is preferably 10 microns; The buried oxide layer silicon dioxide 7 below the 6 is wet-etched to form a micro-channel 10 for the cooling liquid to flow in the horizontal direction. In a specific implementation, the first passivation layer silicon dioxide 5 and the silicon on the upper surface of the SOI wafer 1 are etched by photolithography to form buried oxide layer release holes 6 ((c) in FIG. 1 ), and photolithography Etching the silicon on the upper surface of the SOI wafer 1 and the buried oxide layer of silicon dioxide 7 to form coolant inlet and outlet holes 8 ((d) in FIG. 1 ), and coating a thick photoresist 9 by spin coating or spray coating , photolithography forms a structure in which only the inner sidewall and inner bottom of the microfluidic inlet and outlet hole are exposed, while the outer sidewall and outer surface are protected by photoresist ((e) in FIG. 1 ). The buried oxide layer silicon dioxide 7 of the SOI wafer 1 is released by a wet process, preferably hydrofluoric acid, to form a microchannel 10 .

In the specific implementation of the copper electroplating sealing step of the release hole 6, a seed layer metal is deposited on the upper surface of the silicon-on-insulator wafer and the sidewall of the release hole 6, and the copper pillar is formed by electroplating copper on the seed layer to form a closed hole. The upper surface of the micro flow channel 10;

Specifically, a chromium/copper seed layer is deposited on the upper surface of the silicon-on-insulator wafer and the sidewall of the release hole 6; copper is grown in the release hole 6 by electroplating to form a copper pillar heat sink, and the A thick photoresist 9 on the surface; a second passivation layer silicon dioxide 12 is deposited on the lower surface of the silicon-on-insulator wafer. In specific implementation, it is preferable to sputter chromium/copper to form a seed layer on the side wall and outer surface of the release hole 6, and perform copper electroplating to form a closed column 11, which not only serves to close the upper side of the microchannel 10 The wall acts as a heat sink. After the electroplating is completed, the thick photoresist 9 coated on the outer sidewall of the cooling liquid inlet and outlet hole 8 and the first passivation layer silicon dioxide 5 on the upper surface of the silicon-on-insulator is peeled off. Finally, a second passivation layer silicon dioxide 12 is deposited on the lower surface of the SOI wafer 1 by PECVD ((f) in FIG. 1 ).

In the specific implementation of the inorganic copper plating step on the inner wall of the micro-channel 10 , a copper heat dissipation layer is plated on the upper and lower surfaces of the inner wall of the micro-channel 10 by using a chemical method.

Specifically, by immersing the silicon-on-insulator wafer into an electroless copper plating solution, an upper surface copper deposition layer 13 and a lower surface copper deposition layer 14 are formed on the upper and lower surfaces of the inner wall of the micro-channel 10 . In a specific implementation, when the SOI wafer 1 is immersed in an electroless copper plating solution, copper deposits are formed on the silicon surface, but there is no copper deposit on the inactive silicon oxide surface. In this way, the upper surface copper deposition layer 13 and the lower surface copper deposition layer 14 are also formed on the upper and lower surfaces of the inner wall of the micro-channel 10, which further improves the heat dissipation capability of the micro-channel 10 ((g) in FIG. 1 ). . The method of electroless metal plating includes but not limited to copper, gold, nickel. Taking electroless copper plating as an example, the electroless copper plating solution includes an activation solution and a reaction solution. The silicon-on-insulator wafer is first immersed in the activation solution for activation, and then immersed in the reaction solution for copper plating, wherein the activation The composition of the liquid includes but not limited to deionized water, hydrofluoric acid and palladium chloride, and the composition of the reaction solution includes but not limited to copper sulfate and formaldehyde.

After the step of inorganic copper plating on the inner wall of the micro-channel 10 , the second passivation layer silicon dioxide 12 is removed ((h) in FIG. 1 ).

(a) in FIG. 3 is a schematic top view of a wafer cooling microchannel 10 with a piezoresistive flow detection function. The measurement principle of the microfluidic flow rate is piezoresistive. During operation, the flow of coolant will drive the first force-sensitive strain structure 2 of the cantilever beam structure to produce elastic deformation, causing the resistance value of the force-sensitive resistor 3 to change. By detecting the resistance value The corresponding flow rate and flow rate of coolant can be obtained by changing. Since the resistance value of the force sensitive resistor 3 is sensitive to temperature, a platinum temperature measuring resistor 4 is arranged near the force sensitive resistor 3 in the present invention for compensating the temperature drift of the force sensitive resistor 3 . Fig. 3(b) shows an embodiment of the first force-sensitive strain structure 2 based on the beam-plate structure of the present invention.

The present application also provides an application of a flow measurable microfluidic channel for the heat dissipation of a three-dimensional integrated wafer system manufactured according to the above method, which is used to prepare a silicon wafer transfer with a silicon vertical via hole or a rewiring layer boards for three-dimensional vertical stack integration of multilayer integrated circuit chips or wafers. FIG. 4 shows an embodiment of the flow-measurable microfluidic channel for heat dissipation of a three-dimensional integrated wafer system in the application field of three-dimensional integration. The integrated circuit chip 16 is bonded to the silicon wafer adapter plate with the redistribution layer 18 and the heat dissipation microchannel 10 through the micro-bump 17, and the signal is drawn from the bottom through the silicon vertical via 19 (TSV), which can effectively improve the three-dimensional Integrated system cooling capabilities.

Other embodiments of the present application will readily occur to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any modification, use or adaptation of the application, these modifications, uses or adaptations follow the general principles of the application and include common knowledge or conventional technical means in the technical field not disclosed in the application .

It should be understood that the present application is not limited to the precise constructions which have been described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims (9)

1. The manufacturing method of the micro-flow channel with measurable flow for heat dissipation of the three-dimensional integrated wafer system is characterized by comprising the following steps of:

the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of the silicon wafer on the insulator, and constructing a force-sensitive resistor and a temperature measuring resistor;

releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide of the oxygen-buried layer below the release hole by a wet method to form a micro-channel;

a release hole electroplated copper sealing step: depositing seed layer metal on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel;

and (3) carrying out inorganic copper plating on the inner wall of the micro-channel: plating copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro-channel by using a chemical method;

wherein, the step of releasing the silicon dioxide of the buried oxide layer comprises the following steps:

photoetching a release hole and a cooling liquid inlet and outlet hole on the upper surface of the silicon wafer on the insulator;

coating thick photoresist on the outer side wall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper surface of the insulator, wherein the thickness of the thick photoresist is more than or equal to 10 microns;

and wet etching the silicon dioxide of the oxygen-buried layer below the release hole through the release hole and the cooling liquid inlet and outlet hole to form a micro-channel for the cooling liquid to flow in the horizontal direction.

2. The method of claim 1, wherein the silicon-on-insulator wafer is a backside of a silicon wafer interposer with active integrated circuits or completed silicon vertical vias and re-wiring layers.

3. The method of claim 1, wherein the piezoresistive flow meter manufacturing step comprises:

photoetching and etching the upper surface of the silicon-on-insulator wafer to form a first force-sensitive strain structure, wherein the first force-sensitive strain structure is a cantilever beam, a folding beam-flat plate or a film with holes;

forming a semiconductor force sensitive resistor on the first force sensitive strain structure by ion implantation;

forming a temperature measuring resistor by depositing metal near the force sensing resistor;

sputtering chromium/gold to form an ohmic contact electrode of the force-sensitive resistor and an interconnection line of the temperature-measuring resistor, and depositing a first passivation layer silicon dioxide by plasma enhanced chemical vapor deposition.

4. The method of claim 1, wherein the release hole electroplated copper closing step comprises:

depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the sidewalls of the release holes;

growing copper in the release holes by an electroplating method to form copper column heat sinks;

stripping thick photoresist on the surface, wherein the thickness of the thick photoresist is more than or equal to 10 microns;

and depositing a second passivation layer silicon dioxide on the lower surface of the silicon-on-insulator wafer.

5. The method of claim 1, wherein the micro-fluidic channel inner wall inorganic copper plating step comprises:

and immersing the silicon wafer on the insulator into an electroless copper plating solution to form an upper surface copper deposition layer and a lower surface copper deposition layer on the upper surface and the lower surface of the inner wall of the micro-channel.

6. The method of claim 5, wherein the electroless copper plating solution comprises an activation solution and a reaction solution, the silicon-on-insulator wafer is activated by immersing in the activation solution, and then copper plating is performed by immersing in the reaction solution, wherein the activation solution comprises deionized water, hydrofluoric acid, and palladium chloride, and the reaction solution comprises copper sulfate and formaldehyde.

7. The method of claim 1, further comprising a shock compensation step disposed prior to the buried oxide layer silicon dioxide release step, the step comprising:

and constructing a second force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer outside the micro-channel so as to eliminate errors generated by vibration on fluid pressure measurement.

8. The method of claim 4, wherein the second passivation layer silicon dioxide is removed after the micro-fluidic channel inner wall inorganic copper plating step.

9. Use of a flow-measurable micro-fluidic channel for heat dissipation of a three-dimensional integrated wafer system manufactured according to the method of any of claims 1-8 for the preparation of a silicon wafer interposer with vertical through-silicon vias or redistribution layers for three-dimensional vertical stack integration of multilayer integrated circuit chips or wafers.

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