CN115801005A - Analog-to-digital conversion calibration circuit, multi-path analog-to-digital conversion circuit, chip and computing device - Google Patents
Analog-to-digital conversion calibration circuit, multi-path analog-to-digital conversion circuit, chip and computing device Download PDFInfo
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Abstract
The embodiment of the disclosure discloses an analog-to-digital conversion calibration circuit, a multi-channel analog-to-digital conversion circuit, a chip and a computing device, wherein the analog-to-digital conversion calibration circuit comprises: the digital-to-analog converter comprises a logic control unit; the analog-to-digital converter is used for outputting a digital mismatch signal when an analog input signal is a preset value in a calibration mode; the logic control unit generates a digital calibration signal according to the digital mismatch signal and stores the digital calibration signal into a digital register; the digital-to-analog converter converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the analog-to-digital converter; the analog-to-digital converter is further used for converting the analog calibration signal into a digital output signal; the logic control unit is further used for adjusting the digital calibration signal in the digital register to enable the digital output signal to reach a preset expected digital output signal. The embodiment of the disclosure simplifies the structure of the calibration circuit and reduces the area and power consumption of the calibration circuit.
Description
Technical Field
The disclosure relates to the technical field of integrated circuit design, and in particular to an analog-to-digital conversion calibration circuit, a multi-path analog-to-digital conversion circuit, a chip and a computing device.
Background
Analog-to-Digital converters (ADC) are used to convert Analog signals into Digital signals, and can be applied in many fields. However, due to various factors such as manufacturing processes and material differences, the analog-to-digital converter usually has more or less mismatch phenomena, that is, when the input analog signal is zero, the output digital signal is not zero.
In some applications, mismatch phenomena of the analog-to-digital converter should be avoided as much as possible. For example, a storage and computation integrated processing architecture based on analog signals or analog-digital mixed signals has a high energy efficiency advantage when realizing Multiply-Accumulate (MAC) computation in a medium-low precision computation scenario (e.g., a medium-low precision deep learning scenario). The integrated analog-to-digital computation is performed by analog signals, and in order to realize a universal interface, an analog-to-digital converter with high parallelism is usually required to digitize the signals. Mismatch between the multiple ADCs will compromise the linearity of the entire memory array.
In the current calibration scheme for the digital-to-analog converter, a digital calibration circuit is usually added behind the digital-to-analog converter, and the digital calibration circuit executes a calibration algorithm to calibrate a digital signal output by the digital-to-analog converter, so that the influence caused by a mismatch phenomenon is reduced.
Disclosure of Invention
An embodiment of the present disclosure provides an analog-to-digital conversion calibration circuit, including: the digital-to-analog converter comprises a logic control unit; the analog-to-digital converter is used for outputting a digital mismatch signal when an analog input signal is a preset value in a calibration mode; the logic control unit is used for generating a digital calibration signal according to the digital mismatch signal and storing the digital calibration signal into the digital register; the digital-to-analog converter is used for converting the digital calibration signal into an analog calibration signal and sending the analog calibration signal to the analog-to-digital converter; the analog-to-digital converter is further used for converting the analog calibration signal into a digital output signal; the logic control unit is further used for adjusting the digital calibration signal in the digital register to enable the digital output signal to reach a preset expected digital output signal.
In some embodiments, the digital-to-analog converter is further configured to: when the current mode of the circuit is a normal application mode, reading a digital calibration signal in a digital register, and converting the digital calibration signal into an analog calibration signal; the analog-to-digital converter is further configured to: receiving an analog input signal, and superposing an analog calibration signal and the analog input signal to obtain a calibrated analog signal; and converting the calibrated analog signal into a calibrated digital signal and outputting the calibrated digital signal.
In some embodiments, the analog-to-digital converter further comprises a comparator and a digital-to-analog conversion unit, wherein a first input terminal of the comparator is configured to receive the analog reference signal output by the digital-to-analog conversion unit, and a second input terminal of the comparator is configured to receive the calibrated analog signal obtained by superimposing the analog input signal and the analog calibration signal.
In some embodiments, the bit width of the digital register is the same as the bit width of the analog-to-digital converter.
In some embodiments, the analog-to-digital converter is further to: entering a calibration mode in response to a circuit startup; the calibration mode is exited in response to the digital output signal reaching the desired digital output signal.
In some embodiments, the analog-to-digital converter is further to: entering a calibration mode in response to receiving a mode select signal indicating entry into the calibration mode; the calibration mode is exited in response to the digital output signal reaching the desired digital output signal.
According to another aspect of the embodiments of the present disclosure, there is provided a multiplexing analog-to-digital conversion circuit, including: the system comprises a preset number of analog-to-digital converters, a preset number of digital registers and a plurality of paths of digital-to-analog converters; the multichannel digital-to-analog converter is a resistance digital-to-analog converter and comprises a preset number of single-channel digital-to-analog converters, and each single-channel digital-to-analog converter in the preset number of single-channel digital-to-analog converters comprises a common resistance network and a decoding unit; each analog-to-digital converter in a preset number of analog-to-digital converters corresponds to one digital register and one single-path digital-to-analog converter; the analog-to-digital conversion calibration circuit is formed by the analog-to-digital converter, the digital register and the single-path digital-to-analog converter which are mutually corresponding.
In some embodiments, the multiplexer and the predetermined number of digital registers are disposed between the predetermined number of analog-to-digital converters.
According to another aspect of the embodiments of the present disclosure, there is provided a chip including the above analog-to-digital conversion calibration circuit or the above multi-channel analog-to-digital conversion circuit.
According to another aspect of an embodiment of the present disclosure, there is provided a computing device including the above chip.
The analog-to-digital conversion calibration circuit, the multiple analog-to-digital conversion circuits, the chip and the computing device provided by the embodiments of the present disclosure are configured with an analog-to-digital converter, a digital-to-analog converter and a digital register, where an analog input signal is a preset value, the analog-to-digital converter outputs a digital mismatch signal, the logic control unit generates a digital calibration signal according to the digital mismatch signal and stores the digital calibration signal in the digital register, the digital-to-analog converter converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the analog-to-digital converter, the analog-to-digital converter converts the analog calibration signal into a digital output signal, and the logic control unit is further configured to adjust the digital calibration signal in the digital register so that the digital output signal reaches a preset expected digital output signal.
The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally indicate like parts or steps;
fig. 1 is a schematic structural diagram of an analog-to-digital conversion calibration circuit provided in an exemplary embodiment of the present disclosure;
fig. 2 is another schematic structural diagram of an analog-to-digital conversion calibration circuit provided in an exemplary embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a multi-channel analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are only some of the embodiments of the present disclosure, and not all of the embodiments of the present disclosure, and it is to be understood that the present disclosure is not limited by the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.
It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.
It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.
In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.
It should also be understood that the description of the embodiments in the present disclosure emphasizes the differences between the embodiments, and the same or similar parts may be referred to each other, and are not repeated for brevity.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Summary of the application
In the current calibration scheme for the digital-to-analog converter, a digital calibration circuit is usually added after the digital-to-analog converter, and the digital calibration circuit executes a calibration algorithm to calibrate a digital signal output by the digital-to-analog converter, so that the influence caused by a mismatch phenomenon is reduced.
However, the existing digital calibration circuit is independent of the analog-to-digital converter, and the digital calibration circuit usually needs to occupy a larger area, and has a larger power consumption overhead in high-speed operation, which results in larger power consumption and larger area occupation in the integrated storage and computation scene with larger ADC parallelism.
Exemplary Structure
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion calibration circuit according to an exemplary embodiment of the present disclosure. The various components of the circuit may be integrated into a single chip or may be arranged in different chips or circuit boards that establish data communication links between them.
As shown in fig. 1, the circuit includes: analog-to-digital converter 101, digital-to-analog converter 102 and digital register 103, analog-to-digital converter 101 includes logic control unit 1011.
In this embodiment, the analog-to-digital converter 101 is configured to output a digital mismatch signal when the analog input signal is a preset value in the calibration mode. The preset value can be set arbitrarily, and usually, the preset value is zero. The digital mismatch signal is a signal having a certain error with an expected signal when the analog input signal is a preset value. For example, when the analog input signal is zero, the expected digital output signal of the mode converter is zero, but due to factors such as the manufacturing process of the analog-to-digital converter 101, the actually output digital signal is not zero, and the actually output digital signal is the digital mismatch signal.
The logic control unit 1011 is used for providing logic control signals for the analog-to-digital converter 101. For example, the type of the analog-to-digital converter 101 may be a SAR-ADC (Successive Approximation Register ADC) including a logic control unit 1011 for successively generating a digital signal, converting the digital signal into an analog signal, comparing the analog signal with an analog input signal, and outputting the digital signal bit by bit according to the comparison result.
In this embodiment, the logic control unit 1011 is configured to generate a digital calibration signal according to the digital mismatch signal and store the digital calibration signal into the digital register 103. In addition to the logic control unit 1011 for performing logic control and outputting digital signals when the analog-to-digital converter 101 is in normal operation, the present embodiment may also be multiplexed into the calibration circuit, i.e. generate digital calibration signals and store the digital calibration signals into the digital register 103. Generally, the digital calibration signal is gradually changed from an initial signal (e.g. 0), and the logic control unit 1011 can detect the value of the digital signal output by the analog-to-digital converter 101 in real time, and when the desired digital output signal (e.g. 0) is reached, the digital calibration signal stops changing.
In the present embodiment, a Digital-to-Analog Converter (DAC) 102 is used for converting the Digital calibration signal into an Analog calibration signal and sending the Analog calibration signal to the Analog-to-Digital Converter 101. The type of the digital-to-analog converter 102 may be various types, such as a resistive DAC, a capacitive DAC, and the like.
In this embodiment, the analog-to-digital converter 101 is further configured to convert the analog calibration signal into a digital output signal. Since the current analog input signal is a fixed preset value, the digital output signal at this time represents the magnitude of the analog calibration signal.
In this embodiment, the logic control unit 1011 is further configured to adjust the digital calibration signal in the digital register 103 to make the digital output signal reach the preset desired digital output signal. The logic control unit 1011 may monitor the value of the digital output signal in real time, and if the digital output signal does not reach the desired digital output signal, adjust the digital calibration signal and store the adjusted digital calibration signal in the digital register 103. If the digital output signal reaches the desired digital output signal, updating of the digital output signal stored in the digital register 103 is stopped. Subsequently, when the analog-to-digital converter 101 normally operates, the digital-to-analog converter 102 continuously outputs an analog calibration signal to the analog-to-digital converter 101 according to the digital calibration signal that is updated last time in the digital register 103, so as to cancel out the digital mismatch signal, thereby achieving the purpose of calibrating the analog-to-digital converter 101.
In this embodiment, the analog-to-digital converter implements various functions in the calibration mode. That is, in the calibration mode, the logic control unit of the mode converter generates and stores a digital calibration signal into the digital register, and adjusts the digital calibration signal so that the digital output signal reaches a desired value. Optionally, the analog-to-digital conversion calibration circuit provided in this embodiment may be applied to a calculation integrated circuit based on an analog signal, that is, multiple sets of circuits provided in this embodiment are repeatedly arranged to implement calibration of an analog-to-digital converter in a calculation unit array, so as to reduce the area and power consumption of the calibratable calculation integrated circuit.
The circuit provided by the above embodiment of the present disclosure includes an analog-to-digital converter, a digital-to-analog converter, and a digital register, where the analog-to-digital converter outputs a digital mismatch signal when an analog input signal is a preset value, the logic control unit generates a digital calibration signal according to the digital mismatch signal and stores the digital calibration signal in the digital register, the digital-to-analog converter converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the analog-to-digital converter, the analog-to-digital converter converts the analog calibration signal into a digital output signal, and the logic control unit is further configured to adjust the digital calibration signal in the digital register so that the digital output signal reaches a preset expected digital output signal.
In some optional implementations, the analog-to-digital converter 101 is further configured to:
entering a calibration mode in response to the circuit being enabled;
the calibration mode is exited in response to the digital output signal reaching the desired digital output signal.
After the circuit is started each time, the calibration mode is automatically entered, the analog-digital converter is calibrated, and after the calibration is finished, the calibration mode is exited.
In the embodiment, after each start, the analog-to-digital converter automatically enters the calibration mode, so that the analog-to-digital converter can more accurately eliminate the mismatch phenomenon of output data during normal application, and the conversion precision of the analog-to-digital converter is improved.
In some optional implementations, the analog-to-digital converter 101 is further configured to:
entering a calibration mode in response to receiving a mode select signal indicating entry into the calibration mode;
in response to the digital output signal reaching the desired digital output signal, the calibration mode is exited.
The mode selection signal may be sent by an external controller, i.e. the analog-to-digital converter is calibrated under the control of the external controller.
According to the embodiment, the analog-to-digital converter is controlled to enter the calibration mode through the receiving mode selection signal, so that the analog-to-digital converter can be more flexibly controlled to be calibrated, and the convenience of operating the circuit is improved.
Optionally, the digital register 103 may be a volatile register, and when the circuit is started each time, because the volatile register cannot store data stored before the circuit is started, the circuit may automatically enter the calibration mode, and exit the calibration mode after the calibration is completed. The digital register 103 may also be a non-volatile register, that is, after calibration is performed once, the digital calibration signal is stored for a long time, and then the digital-to-analog converter 102 reads the digital calibration signal from the digital register 103 directly without performing calibration again. When the digital register 103 is a non-volatile type register, the analog-to-digital converter can automatically enter a calibration mode after each start-up; the calibration mode can be entered at any time under the control of the mode selection signal, and the calibration mode does not need to be entered after each start-up.
In some optional implementations, the digital-to-analog converter 102 is further configured to:
when the current mode of the circuit is the normal application mode, the digital calibration signal in the digital register 103 is read and converted into an analog calibration signal.
Specifically, the normal application mode is a mode in which the analog-to-digital converter 101 normally operates after the analog-to-digital converter 101 is calibrated. In the normal application mode, the logic control unit no longer stores the digital calibration signal into the digital register.
Optionally, the circuit may automatically enter the calibration mode after being started, execute the calibration procedure described in the above embodiment, and automatically enter the normal application mode after the calibration is completed. Alternatively, the circuit may receive a mode selection signal sent by an external controller, that is, when the analog-to-digital converter 101 receives a mode selection signal indicating that the calibration mode is entered, the calibration process described in the above embodiment is executed; when the analog-to-digital converter 101 receives the mode selection signal indicating that the normal application mode is entered, the logic control unit 1011 stops outputting the digital calibration signal, and executes the normal analog-to-digital conversion logic.
The analog-to-digital converter 101 is further configured to:
receiving an analog input signal, and superposing an analog calibration signal and the analog input signal to obtain a calibrated analog signal;
and converting the calibrated analog signal into a calibrated digital signal and outputting the calibrated digital signal.
Specifically, the superposition of the analog calibration signal and the analog input signal may be implemented by a circuit inside the analog-to-digital converter 101, for example, an analog addition circuit that superposes the analog signal is provided inside the analog-to-digital converter 101 to superpose the analog calibration signal and the analog input signal.
In this embodiment, when the current mode of the circuit is the normal application mode, the digital-to-analog converter continuously outputs the analog calibration signal to the analog-to-digital converter directly according to the digital calibration signal in the digital register, so that the digital mismatch signal output by the analog-to-digital converter is cancelled out, and thus, the high-precision calibrated digital signal is further output on the basis of reducing the area and power consumption of the calibration circuit.
In some optional implementations, as shown in fig. 2, the analog-to-digital converter 101 further includes a comparator 1012 and a digital-to-analog conversion unit 1013, where a first input end of the comparator is configured to receive the analog reference signal output by the digital-to-analog conversion unit, and a second input end of the comparator is configured to receive the calibrated analog signal obtained by superimposing the analog input signal and the analog calibration signal.
As shown in fig. 2, according to the principle of successive approximation register ADC, the logic control unit 1011 inputs digital signals to the digital-to-analog conversion unit 1013 by successive shifting, the digital-to-analog conversion unit 1013 outputs analog reference signals successively, the comparator 1012 is configured to compare the calibrated analog signals with the analog reference signals, and the logic control unit 1011 obtains one-bit digital signals according to the comparison result, and obtains digital output signals through multiple shifting, converting, and comparing.
In this embodiment, after the analog input signal and the analog calibration signal are superimposed, they are compared with the analog reference signal generated inside the analog-to-digital converter, so that the structure of the analog-to-digital converter itself can be utilized to the maximum extent to output the calibrated digital signal, which is helpful to improve the area utilization rate of the calibration circuit and further simplify the structure of the calibration circuit.
In some alternative implementations, the bit width of the digital register 103 is the same as the bit width of the analog-to-digital converter 101. The bit width of the analog-to-digital converter 101 is the bit width of the digital signal output by the analog-to-digital converter 101. The bit width of the digital register 103 is the bit width of the data stored in the digital register 103.
In this embodiment, the bit width of the digital register and the bit width of the analog-to-digital converter are set to be the same, so that the digital register can be used to directly store the digital calibration signal generated by the logic control unit, and the structure of the analog-to-digital converter is further fully utilized, which is helpful to further improve the integration level of the calibration circuit and reduce the area and power consumption of the calibration circuit.
Fig. 3 is a schematic structural diagram of a multi-channel analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure. The various components of the circuit may be integrated into a single chip or may be arranged in different chips or circuit boards that establish data communication links between them.
As shown in fig. 3, the circuit includes: a preset number of analog-to-digital converters 301, a preset number of digital registers 302 and a multi-path digital-to-analog converter 303;
the multi-way digital-to-analog converter 303 is a resistance digital-to-analog converter, and the multi-way digital-to-analog converter 303 includes a preset number of single-way digital-to-analog converters, and each single-way digital-to-analog converter in the preset number of single-way digital-to-analog converters includes a common resistance network and a decoding unit. As shown in fig. 3, the common resistor network 3031 and the decoding unit 3032 form a one-way digital-to-analog converter, and the common resistor network 3031 and the decoding unit 3033 form another one-way digital-to-analog converter.
Each of a preset number of analog-to-digital converters 301 corresponds to one digital register and one single-channel digital-to-analog converter; the analog-to-digital converter, the digital register and the one-way digital-to-analog converter which correspond to each other constitute the analog-to-digital conversion calibration circuit described in the above embodiment.
According to the principle of the resistor-type digital-to-analog converter, the decoding unit is used for receiving the digital calibration signal output by the corresponding analog-to-digital converter, the decoding unit may include a plurality of switches, the number of the switches is the same as the number of bits of the digital calibration signal, and each switch is connected to a different node of the resistor network. The decoding unit sets the on-off state of each switch according to each bit included in the digital calibration signal, and then outputs a corresponding analog calibration signal by using the voltage division effect of the resistor network.
The preset number can be set arbitrarily, and usually the preset number is 2, that is, as shown in fig. 3, two analog-to-digital converters, two digital registers, and one multi-way digital-to-analog converter are set as a group of analog-to-digital conversion circuits.
As shown IN fig. 3, a multi-channel digital-to-analog converter 303 is disposed between two analog-to-digital converters (i.e., 3011 and 3012), the multi-channel digital-to-analog converter 303 includes a common resistor network 3031, the multi-channel digital-to-analog converter includes two single-channel digital-to-analog converters capable of reading digital calibration signals CD0 and CD1 from two digital registers, respectively, that is, one single-channel digital-to-analog converter composed of the decoding unit 3032 and the common resistor network 3031 performs digital-to-analog conversion on CD1 and outputs an analog calibration signal CA0, and the other single-channel digital-to-analog converter composed of the decoding unit 3033 and the common resistor network 3031 performs digital-to-analog conversion on CD2 and outputs an analog calibration signal CA1, and the two analog-to-analog converters receive the analog calibration signals respectively, superimpose the analog calibration signals IN0 and IN1 and output calibrated digital signals D0 and D1.
Optionally, the multi-channel analog-to-digital conversion circuit provided in this embodiment may be applied to a calculation integrated circuit based on an analog signal, that is, multiple sets of circuits provided in this embodiment are repeatedly arranged, so as to reduce the area and power consumption of the calculation integrated circuit that can be calibrated.
According to the circuit provided by the embodiment of the disclosure, one multi-path digital-to-analog converter is shared by the multi-path analog-to-digital converters, and the multi-path digital-to-analog converters output multi-path analog calibration signals through the common resistance network and the preset number of decoding units, so that the integration level of the multi-path analog-to-digital conversion circuit with the calibration function is improved, and the area and the power consumption of the multi-path analog-to-digital conversion circuit are favorably reduced.
In some alternative implementations, the plurality of digital-to-analog converters and the predetermined number of digital registers are disposed between the predetermined number of analog-to-digital converters. As shown in fig. 3, a multiplexer 303 and a predetermined number of digital registers 302 are provided between the analog-to- digital converters 3011 and 3012.
In this embodiment, the multiple digital-to-analog converters and the preset number of digital registers are arranged between the preset number of analog-to-digital converters, so that the multiple analog-to-digital converters share one multiple digital-to-analog converter for calibration, and the distances between the multiple digital-to-analog converters and the multiple analog-to-digital converters are as close as possible, thereby further improving the integration level of the circuit and contributing to reducing the area of the circuit.
Embodiments of the present disclosure also provide a chip, on which an analog-to-digital conversion calibration circuit, or multiple analog-to-digital conversion circuits, are integrated, and the technical details of the analog-to-digital conversion calibration circuit and the multiple analog-to-digital conversion circuits are shown in fig. 1 to fig. 3 and related description, and will not be further described herein.
Embodiments of the present disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include input devices, output devices, and necessary memory, etc. The input device may include a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting an analog input signal. The output means may include devices such as a display, a printer, and a communication network and remote output devices connected thereto, and the like, for outputting digital output signals, calculation results calculated based on the digital output signals, and the like. The memory is used for storing the data input by the input device and the data generated in the operation process of the analog-to-digital conversion calibration circuit or the multi-path analog-to-digital conversion circuit. The memory may include volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, etc.
The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure will be described in detail with reference to specific details.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other.
The block diagrams of devices, apparatuses, devices, systems involved in the present disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by one skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. As used herein, the words "or" and "refer to, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
The circuitry of the present disclosure may be implemented in a number of ways. For example, the circuitry of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described order of steps for a method in a circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, the program including machine-readable instructions for implementing the functions of the circuit according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the functions of the circuit according to the present disclosure.
It is further noted that in the circuits of the present disclosure, components or steps may be decomposed and/or recombined. Such decomposition and/or recombination should be considered as equivalents of the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. An analog-to-digital conversion calibration circuit comprising: the digital-to-analog converter comprises a logic control unit;
the analog-to-digital converter is used for outputting a digital mismatch signal when an analog input signal is a preset value in a calibration mode;
the logic control unit is used for generating a digital calibration signal according to the digital mismatch signal and storing the digital calibration signal into a digital register;
the digital-to-analog converter is used for converting the digital calibration signal into an analog calibration signal and sending the analog calibration signal to the analog-to-digital converter;
the analog-to-digital converter is further configured to convert the analog calibration signal to a digital output signal;
the logic control unit is further configured to adjust the digital calibration signal in the digital register so that the digital output signal reaches a preset desired digital output signal.
2. The circuit of claim 1, wherein the digital-to-analog converter is further configured to:
when the current mode of the circuit is a normal application mode, reading a digital calibration signal in the digital register, and converting the digital calibration signal into an analog calibration signal;
the analog-to-digital converter is further configured to:
receiving an analog input signal, and superposing the analog calibration signal and the analog input signal to obtain a calibrated analog signal;
and converting the calibrated analog signal into a calibrated digital signal and outputting the calibrated digital signal.
3. The circuit of claim 1, wherein the analog-to-digital converter further comprises a comparator and a digital-to-analog conversion unit, wherein a first input terminal of the comparator is configured to receive the analog reference signal output by the digital-to-analog conversion unit, and a second input terminal of the comparator is configured to receive the calibrated analog signal obtained by superimposing the analog input signal and the analog calibration signal.
4. The circuit of claim 1, wherein the digital register has a same bit width as the analog-to-digital converter.
5. The circuit of any of claims 1-4, wherein the analog-to-digital converter is further to:
entering the calibration mode in response to the circuit being enabled;
exiting the calibration mode in response to the digital output signal reaching the desired digital output signal.
6. The circuit of any of claims 1-4, wherein the analog-to-digital converter is further to:
entering a calibration mode in response to receiving a mode select signal indicating entry into the calibration mode;
exiting the calibration mode in response to the digital output signal reaching the desired digital output signal.
7. A multi-channel analog-to-digital conversion circuit comprising: the device comprises a preset number of analog-to-digital converters, a preset number of digital registers and a plurality of paths of digital-to-analog converters;
the multichannel digital-to-analog converter is a resistance digital-to-analog converter and comprises a preset number of single-channel digital-to-analog converters, and each single-channel digital-to-analog converter in the preset number of single-channel digital-to-analog converters comprises a common resistance network and a decoding unit;
each analog-to-digital converter in the preset number of analog-to-digital converters corresponds to one digital register and one single-path digital-to-analog converter; the analog-to-digital converter, the digital register and the one-way digital-to-analog converter which correspond to each other constitute the analog-to-digital conversion calibration circuit of any one of claims 1 to 6.
8. The circuit of claim 7, wherein the multiplexer digital-to-analog converter and the predetermined number of digital registers are disposed between the predetermined number of analog-to-digital converters.
9. A chip comprising an analog-to-digital conversion calibration circuit according to any one of claims 1 to 6, or a multi-channel analog-to-digital conversion circuit according to any one of claims 7 to 8.
10. A computing device comprising a chip according to claim 9.
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| CN202211435064.5A CN115801005A (en) | 2022-11-16 | 2022-11-16 | Analog-to-digital conversion calibration circuit, multi-path analog-to-digital conversion circuit, chip and computing device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118801884A (en) * | 2024-09-06 | 2024-10-18 | 杭州神络医疗科技有限公司 | Analog-to-digital conversion device, digital signal calibration method and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118801884A (en) * | 2024-09-06 | 2024-10-18 | 杭州神络医疗科技有限公司 | Analog-to-digital conversion device, digital signal calibration method and device |
| CN118801884B (en) * | 2024-09-06 | 2025-02-07 | 杭州神络医疗科技有限公司 | Analog-to-digital conversion device, digital signal calibration method and device |
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