CN115714637A - Message transmission device and method based on SRIO time division multiplexing and demultiplexing - Google Patents

Abstract

The invention discloses a message transmission device and method based on SRIO time division multiplexing and demultiplexing, and relates to the technical field of high-speed data communication. The device is realized by adopting two single-board circuits provided with FPGA chips, wherein the FPGA chips comprise a local end chip FPGA1 and an opposite end chip FPGA2; the invention also provides a message transmission method based on SRIO time division multiplexing and demultiplexing, which comprises the steps of caching the data of the input channels in the FIFO memory back and forth in sequence, polling and dynamically adjusting the priority by using the writing completion marks of the input channels of the polling counter corresponding to the FIFO memory, completing the interaction with the SRIO interface protocol of the opposite end, and demultiplexing the SRIO bus data. On the premise of saving SRIO interface resources, the invention can solve the problems of CS chip selection channel conflict and a large amount of packet loss, and simultaneously ensures the real-time performance of each service channel data and the reliability of each control channel data.

Description

A message transmission device and method based on SRIO time division multiplexing and demultiplexing

technical field

The invention relates to the technical field of high-speed data communication, in particular to a message transmission device and method based on SRIO time division multiplexing and demultiplexing.

Background technique

In the field of high-speed data communication, SRIO (Serial Rapid IO) bus technology has become a commonly used high-speed control bus, which can support inter-chip and inter-board communication, and is increasingly used in communication systems.

With the development of communication technology and embedded systems, in the SRIO link part of the FPGA solution design of the existing communication transmission system, an SRIO link often needs: 1. Transmission of multi-service channels with high real-time requirements and large data volume ; 2. Multi-control channels with high transmission reliability requirements and small data volume; 3. Ensure that various functions can be performed simultaneously without interfering with each other. In a multi-channel SRIO bus environment, if CS (Chip Select) is used, only one SRIO bus can be selected each time. If multiple SRIO buses are required to transmit messages at the same time, there will be conflicts during chip selection. , a large number of packet loss occurs, and simultaneous transmission of multiple SRIO buses cannot be realized, which does not meet the use requirements.

Contents of the invention

The object of the present invention is to provide a message transmission device and method based on SRIO time-division multiplexing and demultiplexing, so as to solve the problems raised in the above-mentioned background technology.

In order to solve the above technical problems, the present invention provides the following technical solutions:

A message transmission device based on SRIO time-division multiplexing and demultiplexing, said device is realized by two single-board circuits equipped with FPGA chips;

The total number of input channels of the device is L, the number of service channels is n, and the number of control channels is m;

Described FPGA chip comprises this end chip FPGA1 and opposite end chip FPGA2, and described local end chip FPGA1 and described opposite end chip FPGA2 internal structure are identical, and internal connection mode is identical, and placement direction is opposite; The local chip FPGA1 is connected to the n-way service channel and the m-way control channel; the opposite-end chip FPGA2 is connected to the local-end chip FPGA1;

Described local chip FPGA1 comprises time-division multiplexing module MUX, SRIO sending module SRIO_TX, SRIO receiving module SRIO_RX and demultiplexing module DEMUX;

The output of the time-division multiplexing module MUX of the local chip FPGA1 is connected with the input of the SRIO transmission module SRIO_TX of the local chip FPGA1; the output of the SRIO transmission module SRIO_TX of the local chip FPGA1 is connected with the The input of the SRIO receiving module SRIO_RX of the opposite chip FPGA2 is connected; the output of the SRIO receiving module SRIO_RX of the opposite chip FPGA2 is connected with the input of the demultiplexing module DEMUX of the opposite chip FPGA2; The output end of the demultiplexing module DEMUX of the opposite end chip FPGA2 is connected with the input end of the time division multiplexing module MUX of the opposite end chip FPGA2; the output end of the time division multiplexing module MUX of the opposite end chip FPGA2 Be connected with the input end of the SRIO sending module SRIO_TX of described opposite end chip FPGA2; The output end of the SRIO sending module SRIO_TX of described opposite end chip FPGA2 is connected with the input end of the SRIO receiving module SRIO_RX of described local end chip FPGA1; The output terminal of the SRIO receiving module SRIO_RX of the local chip FPGA1 is connected to the input terminal of the demultiplexing module DEMUX of the local chip FPGA1.

According to the above technical solution, the time-division multiplexing module MUX includes a cache unit, an unpacking unit, a register unit, a write clock, a read clock and a polling unit;

The buffer unit is used to send the SRIO interface data input by the L-way input channel into the FIFO memory for buffering and perform ping-pong buffering for two asynchronous FIFO memories;

The unpacking unit is used to unpack the n-way service channel data in the SRIO interface data input by the L-way input channel;

The register unit is used to store the write completion flag wr_done_flag corresponding to the FIFO memory of each L input channel into the write completion flag register wr_done_reg from right to left;

The write clock is the rate corresponding to each L input channel;

The read clock is the user clock log_clk of SRIO;

The polling unit is used to use the polling counter to poll whether the write completion flag wr_done_flag of the channel is valid, and when there are two or more channels with the write completion flag wr_done_flag valid, the priority dynamic adjustment mode is started.

According to the above technical solution, the SRIO sending module SRIO_TX includes a grouping unit and a sending unit;

The grouping unit is used to complete the grouping of the SRIO interface protocol;

The sending unit is used to send the timing design, and send the time-division multiplexing signal srio_mux to the peer chip FPGA2.

According to the above technical solution, the SRIO receiving module SRIO_RX includes an analysis unit and a transmission unit;

The analysis unit is used to analyze the time-division multiplexing signal srio_mux "' sent by the internal SRIO of the opposite chip FPGA2;

The transmitting unit is used to transmit the analyzed time-division multiplexing signal srio_mux"' to the demultiplexing module.

According to the above technical solution, the demultiplexing module DEMUX includes an identification unit, a selection unit, a writing clock, a reading clock and a demultiplexing unit;

The identification unit is used to identify the channel number according to the frame header of the SRIO protocol;

The selection unit is used to select the corresponding asynchronous dual-port ram storage according to the channel number;

The write clock corresponds to the read clock log_clk of the time-division multiplexing module;

The read clock is the rate corresponding to each L input channel;

The demultiplexing unit is used to complete demultiplexing from channel 1 to channel L, and restore the SRIO interface data of channel L.

A kind of message transmission method based on SRIO time-division multiplexing and demultiplexing, the step of described method comprises:

S1: Send the SRIO interface data input from the L-channel input channel into the FIFO memory for buffering and perform ping-pong buffering on two asynchronous FIFO memories, and disassemble the n-channel service channel data in the SRIO interface data input from the L-channel input channel Bag;

S2: the write completion flag wr_done_flag corresponding to the FIFO memory of each L road input channel is stored in the write completion flag register wr_done_reg from right to left, and the write completion flag of each L road input channel corresponding to the FIFO memory is polled by using the polling counter cnt1 query and priority dynamic adjustment;

S3: Complete the SRIO interface protocol interaction with the opposite end, that is, send the multiplexing signal srio_mux output by the time-division multiplexing module MUX to the SRIO transmission module SRIO_TX, complete the grouping and timing design and convert it into a high-speed data stream txp/n, Send it to the SRIO interface of the peer chip FPGA2, and send it to the SRIO receiving module SRIO_RX of the local chip FPGA1 after the peer processing is completed. After the local end receives the high-speed data stream rxp/n, it converts it into an SRIO interface through serial conversion and parsing bus data;

S4: Demultiplex the SRIO bus data, send the srio_demux data to the demultiplexing module DEMUX, identify the channel number according to the protocol frame header, select the corresponding asynchronous dual-port ram storage according to the channel number, and complete the demultiplexing from channel 1 to channel L Multiplexing, restoring L-way SRIO interface data.

According to the above technical solution, in step S1, the L input channels include n service channels and m control channels;

Unpack the data of the n-way business channels in the L-way input channels, and set the number of bits in one package to c bits;

The number of bits in a packet can be customized according to requirements, but in order to ensure the real-time performance of this type of data, the value is generally within 200 bits.

The bit streams of the n service channels are sequentially buffered back and forth in the corresponding two FIFO memories according to small packets.

According to the above technical solution, in step S2, the polling counter cnt1 determines and accumulates the channel for selecting the read data according to the value of the polling counter cnt1 at that time, and the polling counter cnt1 polls the write data of two or more channels When the completion flag wr_done_flag is valid, the priority dynamic adjustment method is enabled.

According to the technique scheme, the specific performance of the state flow diagram of the state machine of the time-division multiplexing module MUX is as follows:

State 1: initial state, reset the polling counter cnt1 and waiting counter cnt2 and other signals at the beginning; when the polling counter cnt1 detects that the write completion flag register wr_done_reg is valid, it triggers to enter state 2, if the write completion flag register wr_done_reg is invalid, Then it keeps looping in state 1;

State 2: polling state, polling the writing completion flag of each channel; the polling method is dynamic adjustment of priority, and the priority is determined according to the value of the polling counter cnt1 at that time, and the polling counter cnt1 starts counting from 0, counting The range is 0 to p. When it is detected that the write completion flag register wr_done_reg[cnt1] is valid, the polling ends, the polling counter cnt1 stops counting, and the trigger enters state 3. If the write completion flag register wr_done_reg[cnt1] is invalid, the Loop in state 2;

State 3: Waiting state, the waiting counter cnt2 counts cyclically from 0, and the counting range is 0~q. At the same time, the frame header of each channel is added according to the interface protocol of time-division multiplexing, and the length is 1 byte. When cnt2 is detected as q , the trigger enters state 4, and if cnt2 is less than q, it keeps looping in state 3;

State 4: Read the state, pull the read enable rd[cnt1] of the FIFO memory of the corresponding channel high, read until the FIFO empty flag empty[cnt1] is valid, trigger back to state 1, and enter the next polling operation, otherwise keep Loop in state 4.

According to the above technical solution, in step S3, the SRIO interface protocol includes an initiation request ireq, an initiation response iresp, a target request treq, and a target response tresp.

Compared with the prior art, the beneficial effects achieved by the present invention are:

(1) The present invention solves the problem that the traditional CS chip selection method cannot transmit multiple SRIO buses at the same time, and proposes a complete solution for time-division multiplexing and demultiplexing by means of "speed up + polling + dynamic priority adjustment" Solution, under the premise of saving SRIO interface resources, this solution can solve the problem of CS chip selection channel conflict and a large number of packet loss, and at the same time ensure the real-time data of each service channel and the reliability of data of each control channel;

(2) The time-division multiplexing module MUX of the present invention's design and the demultiplexing module DEMUX are all equipped with L road spi bus channels inside, support the flexible configuration of n+m, only need to satisfy n+m<=L and get final product, wherein n Business data types with large data volume and high real-time requirements are preferred, and control data types with small data volume and high reliability requirements are preferred.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the attached picture:

Fig. 1 is a structure diagram of a message transmission device and method based on SRIO time-division multiplexing and demultiplexing in the present invention;

Fig. 2 is the state flowchart of time-division multiplexing module MUX of the present invention;

Fig. 3 is the interaction block diagram of local SRIO and opposite end SRIO protocol of the present invention;

FIG. 4 is a flowchart of a message transmission device and method based on SRIO time-division multiplexing and demultiplexing in the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to Fig. 1-Fig. 4, the present invention provides technical scheme:

A message transmission device based on SRIO time-division multiplexing and demultiplexing, said device is realized by two single-board circuits equipped with FPGA chips;

The total number of input channels of the device is L, the number of service channels is n, and the number of control channels is m;

Described FPGA chip comprises this end chip FPGA1 and opposite end chip FPGA2, and described local end chip FPGA1 and described opposite end chip FPGA2 internal structure are identical, and internal connection mode is identical, and placement direction is opposite; The local chip FPGA1 is connected to the n-way service channel and the m-way control channel; the opposite-end chip FPGA2 is connected to the local-end chip FPGA1;

Described local chip FPGA1 comprises time-division multiplexing module MUX, SRIO sending module SRIO_TX, SRIO receiving module SRIO_RX and demultiplexing module DEMUX;

The output of the time-division multiplexing module MUX of the local chip FPGA1 is connected with the input of the SRIO transmission module SRIO_TX of the local chip FPGA1; the output of the SRIO transmission module SRIO_TX of the local chip FPGA1 is connected with the The input of the SRIO receiving module SRIO_RX of the opposite chip FPGA2 is connected; the output of the SRIO receiving module SRIO_RX of the opposite chip FPGA2 is connected with the input of the demultiplexing module DEMUX of the opposite chip FPGA2; The output end of the demultiplexing module DEMUX of the opposite end chip FPGA2 is connected with the input end of the time division multiplexing module MUX of the opposite end chip FPGA2; the output end of the time division multiplexing module MUX of the opposite end chip FPGA2 Be connected with the input end of the SRIO sending module SRIO_TX of described opposite end chip FPGA2; The output end of the SRIO sending module SRIO_TX of described opposite end chip FPGA2 is connected with the input end of the SRIO receiving module SRIO_RX of described local end chip FPGA1; The output terminal of the SRIO receiving module SRIO_RX of the local chip FPGA1 is connected to the input terminal of the demultiplexing module DEMUX of the local chip FPGA1.

According to the above technical solution, the time-division multiplexing module MUX includes a cache unit, an unpacking unit, a register unit, a write clock, a read clock and a polling unit;

The buffer unit is used to send the SRIO interface data input by the L-way input channel into the FIFO memory for buffering and perform ping-pong buffering for two asynchronous FIFO memories;

The unpacking unit is used to unpack the n-way service channel data in the SRIO interface data input by the L-way input channel;

The register unit is used to store the write completion flag wr_done_flag corresponding to the FIFO memory of each L input channel into the write completion flag register wr_done_reg from right to left;

The write clock is the rate corresponding to each L input channel;

The read clock is the user clock log_clk of SRIO;

The polling unit is used to use the polling counter to poll whether the write completion flag wr_done_flag of the channel is valid, and when there are two or more channels with the write completion flag wr_done_flag valid, the priority dynamic adjustment mode is started.

According to the above technical solution, the SRIO sending module SRIO_TX includes a grouping unit and a sending unit;

The grouping unit is used to complete the grouping of the SRIO interface protocol;

The sending unit is used to send the timing design, and send the time-division multiplexing signal srio_mux to the peer chip FPGA2.

According to the above technical solution, the SRIO receiving module SRIO_RX includes an analysis unit and a transmission unit;

The analysis unit is used to analyze the time-division multiplexing signal srio_mux "' sent by the internal SRIO of the opposite chip FPGA2;

The transmitting unit is used to transmit the analyzed time-division multiplexing signal srio_mux"' to the demultiplexing module.

According to the above technical solution, the demultiplexing module DEMUX includes an identification unit, a selection unit, a writing clock, a reading clock and a demultiplexing unit;

The identification unit is used to identify the channel number according to the frame header of the SRIO protocol;

The selection unit is used to select the corresponding asynchronous dual-port ram storage according to the channel number;

The write clock corresponds to the read clock log_clk of the time-division multiplexing module;

The read clock is the rate corresponding to each L input channel;

The demultiplexing unit is used to complete demultiplexing from channel 1 to channel L, and restore the SRIO interface data of channel L.

A kind of message transmission method based on SRIO time-division multiplexing and demultiplexing, the step of described method comprises:

S1: Send the SRIO interface data input from the L-channel input channel into the FIFO memory for buffering and perform ping-pong buffering on two asynchronous FIFO memories, and disassemble the n-channel service channel data in the SRIO interface data input from the L-channel input channel Bag;

S2: the write completion flag wr_done_flag corresponding to the FIFO memory of each L road input channel is stored in the write completion flag register wr_done_reg from right to left, and the write completion flag of each L road input channel corresponding to the FIFO memory is polled by using the polling counter cnt1 query and priority dynamic adjustment;

S3: Complete the SRIO interface protocol interaction with the opposite end, that is, send the multiplexing signal srio_mux output by the time-division multiplexing module MUX to the SRIO transmission module SRIO_TX, complete the grouping and timing design and convert it into a high-speed data stream txp/n, Send it to the SRIO interface of the peer chip FPGA2, and send it to the SRIO receiving module SRIO_RX of the local chip FPGA1 after the peer processing is completed. After the local end receives the high-speed data stream rxp/n, it converts it into an SRIO interface through serial conversion and parsing bus data;

S4: Demultiplex the SRIO bus data, send the srio_demux data to the demultiplexing module DEMUX, identify the channel number according to the protocol frame header, select the corresponding asynchronous dual-port ram storage according to the channel number, and complete the demultiplexing from channel 1 to channel L Multiplex and restore L-channel SRIO interface data.

Unpack the data of the n-way business channels in the L-way input channels, and set the number of bits in one package to c bits;

The bit streams of the n service channels are sequentially buffered back and forth in the corresponding two FIFO memories according to small packets.

According to the above technical solution, in step S2, the polling counter cnt1 determines and accumulates the channel for selecting the read data according to the value of the polling counter cnt1 at that time, and the polling counter cnt1 polls the write data of two or more channels When the completion flag wr_done_flag is valid, the priority dynamic adjustment method is enabled.

According to the technique scheme, the specific performance of the state flow diagram of the state machine of the time-division multiplexing module MUX is as follows:

State 1: initial state, reset the polling counter cnt1 and waiting counter cnt2 and other signals at the beginning; when the polling counter cnt1 detects that the write completion flag register wr_done_reg is valid, it triggers to enter state 2, if the write completion flag register wr_done_reg is invalid, Then it keeps looping in state 1;

State 2: polling state, polling the writing completion flag of each channel; the polling method is dynamic adjustment of priority, and the priority is determined according to the value of the polling counter cnt1 at that time, and the polling counter cnt1 starts counting from 0, counting The range is 0 to p. When it is detected that the write completion flag register wr_done_reg[cnt1] is valid, the polling ends, the polling counter cnt1 stops counting, and the trigger enters state 3. If the write completion flag register wr_done_reg[cnt1] is invalid, the Loop in state 2;

State 3: Waiting state, the waiting counter cnt2 counts cyclically from 0, and the counting range is 0~q. At the same time, the frame header of each channel is added according to the interface protocol of time-division multiplexing, and the length is 1 byte. When cnt2 is detected as q , the trigger enters state 4, and if cnt2 is less than q, it keeps looping in state 3;

State 4: Read the state, pull the read enable rd[cnt1] of the FIFO memory of the corresponding channel high, read until the FIFO empty flag empty[cnt1] is valid, trigger back to state 1, and enter the next polling operation, otherwise keep Loop in state 4.

According to the above technical solution, in step S3, the SRIO interface protocol includes an initiation request ireq, an initiation response iresp, a target request treq, and a target response tresp.

In this example:

Set the total number of channels L=10, where n=5 service channels and m=5 control channels.

S1: Send the SRIO interface data input from the 10 input channels into the FIFO memory for buffering and perform ping-pong buffering on two asynchronous FIFO memories, and disassemble the 5 business channel data from the SRIO interface data input from the L input channels Bag;

S2: the write completion flag wr_done_flag corresponding to the FIFO memory of each 10-way input channel is stored in the write completion flag register wr_done_reg from right to left, and the write completion flag of each 10-way input channel corresponding to the FIFO memory is carried out by polling counter cnt1 query and priority dynamic adjustment;

S3: Complete the SRIO interface protocol interaction with the opposite end, that is, send the multiplexing signal srio_mux output by the time-division multiplexing module MUX to the SRIO transmission module SRIO_TX, complete the grouping and timing design and convert it into a high-speed data stream txp/n, Send it to the SRIO interface of the peer chip FPGA2, and send it to the SRIO receiving module SRIO_RX of the local chip FPGA1 after the peer processing is completed. After the local end receives the high-speed data stream rxp/n, it converts it into an SRIO interface through serial conversion and parsing bus data;

S4: Demultiplex the SRIO bus data, send the srio_demux data to the demultiplexing module DEMUX, identify the channel number according to the protocol frame header, select the corresponding asynchronous dual-port ram storage according to the channel number, and complete the demultiplexing of channels 1 to 10 Multiplexing, restore 10 SRIO interface data.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device.

Finally, it should be noted that: the above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, it still The technical solutions recorded in the foregoing embodiments may be modified, or some technical features thereof may be equivalently replaced. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A message transmission device based on SRIO time division multiplexing and demultiplexing is characterized in that the device is realized by adopting two single-board circuits provided with FPGA chips;

the total number of input channels of the device is L, the number of service channels is n, and the number of control channels is m;

the FPGA chip comprises a local end chip FPGA1 and an opposite end chip FPGA2, the internal structures of the local end chip FPGA1 and the opposite end chip FPGA2 are the same, the internal connection modes are the same, and the placement directions are opposite; the local end chip FPGA1 is connected with the n service channels and the m control channels; the opposite-end chip FPGA2 is connected with the local-end chip FPGA 1;

the local end chip FPGA1 comprises a time division multiplexing module MUX, an SRIO sending module SRIO _ TX, an SRIO receiving module SRIO _ RX and a demultiplexing module DEMUX;

the output end of the time division multiplexing module MUX of the local end chip FPGA1 is connected with the input end of the SRIO sending module SRIO _ TX of the local end chip FPGA 1; the output end of the SRIO sending module SRIO _ TX of the local end chip FPGA1 is connected with the input end of the SRIO receiving module SRIO _ RX of the opposite end chip FPGA2; the output end of the SRIO receiving module SRIO _ RX of the opposite end chip FPGA2 is connected with the input end of the de-multiplexing module DEMUX of the opposite end chip FPGA2; the output end of the demultiplexing module DEMUX of the opposite-end chip FPGA2 is connected with the input end of the time-sharing multiplexing module MUX of the opposite-end chip FPGA2; the output end of the time division multiplexing module MUX of the opposite end chip FPGA2 is connected with the input end of the SRIO sending module SRIO _ TX of the opposite end chip FPGA2; the output end of the SRIO sending module SRIO _ TX of the opposite-end chip FPGA2 is connected with the input end of the SRIO receiving module SRIO _ RX of the local-end chip FPGA 1; the output end of the SRIO receiving module SRIO _ RX of the local end chip FPGA1 is connected with the input end of the de-multiplexing module DEMUX of the local end chip FPGA 1.

2. The message transmission device based on SRIO time division multiplexing and demultiplexing according to claim 1, wherein: the time division multiplexing module MUX comprises a cache unit, an unpacking unit, a registering unit, a writing clock, a reading clock and a polling unit;

the buffer unit is used for sending SRIO interface data input by the L-path input channel into the FIFO memory for buffering and performing ping-pong buffer on the two asynchronous FIFO memories;

the unpacking unit is used for unpacking n paths of service channel data in SRIO interface data input by the L path of input channel;

the register unit is used for sequentially storing write completion flags wr _ done _ flag of the FIFO memory corresponding to each L-path input channel into a write completion flag register wr _ done _ reg from right to left;

the writing clock is the speed corresponding to each L-path input channel;

the read clock is a user clock log _ clk of SRIO;

the polling unit is used for polling whether a write completion flag wr _ done _ flag of a channel is effective or not by using a polling counter, and when the write completion flag wr _ done _ flag of two or more channels is effective, a priority dynamic adjustment mode is started.

3. The message transmission device based on SRIO time division multiplexing and demultiplexing according to claim 1, wherein: the SRIO sending module SRIO _ TX comprises a group packing unit and a sending unit;

the packaging unit is used for completing packaging of an SRIO interface protocol;

the sending unit is used for sending the time sequence design and sending the time division multiplexing signal srio _ mux to the opposite-end chip FPGA 2.

4. The message transmission device based on SRIO time division multiplexing and demultiplexing according to claim 1, wherein: the SRIO receiving module SRIO _ RX comprises an analysis unit and a transmission unit;

the analysis unit is used for analyzing a time division multiplexing signal SRIO _ mux' sent by an SRIO in the opposite-end chip FPGA2;

and the transmission unit is used for transmitting the analyzed time division multiplexing signal srio _ mux' "into the demultiplexing module.

5. The message transmission device based on SRIO time division multiplexing and demultiplexing according to claim 1, wherein: the DEMUX comprises an identification unit, a selection unit, a write clock, a read clock and a demultiplexing unit;

the identification unit is used for identifying the channel number according to the SRIO protocol frame header;

the selection unit is used for selecting corresponding asynchronous dual-port ram storage according to the channel number;

the write clock corresponds to a read clock log _ clk of the time division multiplexing module;

the read clock is the speed corresponding to each L-path input channel;

the demultiplexing unit is used for completing demultiplexing from the 1 path to the L path and restoring the SRIO interface data of the L path.

6. A message transmission method based on SRIO time division multiplexing and demultiplexing is characterized in that: the method comprises the following steps:

s1, SRIO interface data input by an L-path input channel is sent into an FIFO memory for caching, ping-pong caching is carried out on two asynchronous FIFO memories, and unpacking is carried out on n-path service channel data in the SRIO interface data input by the L-path input channel;

s2, sequentially storing the writing completion marks wr _ done _ flag of the FIFO memories corresponding to the L input channels from right to left into a writing completion mark register wr _ done _ reg, and polling and dynamically adjusting the priority levels of the writing completion marks of the FIFO memories corresponding to the L input channels by using a polling counter cnt 1;

s3, completing the protocol interaction with the SRIO interface of the opposite end, namely sending a multiplexing signal SRIO _ MUX output by the time division multiplexing module MUX into an SRIO sending module SRIO _ TX, sending the multiplexing signal SRIO _ MUX into an SRIO interface of an opposite end chip FPGA2 after completing the grouping and time sequence design, sending the multiplexing signal SRIO _ TX to an SRIO receiving module SRIO _ RX of a local end chip FPGA1 after completing the processing of the opposite end, and converting the multiplexing signal SRIO _ MUX into bus data of the SRIO interface by serial conversion and analysis after the local end receives the high-speed data stream rxp/n;

and S4, demultiplexing the SRIO bus data, namely sending SRIO _ DEMUX data into a demultiplexing module DEMUX, identifying a channel number according to a protocol frame header, selecting a corresponding asynchronous dual-port ram according to the channel number for storage, completing demultiplexing from 1 channel to L channels, and restoring SRIO interface data of the L channels.

7. The message transmission method based on SRIO time division multiplexing and demultiplexing according to claim 6, wherein: in step S1, the L input channels include n service channels and m control channels;

unpacking n paths of service channel data in L paths of input channels, and setting the bit number of a packet as c bits;

and the bit streams of the n paths of service channels are sequentially cached back and forth in the two corresponding FIFO memories according to the small packets.

8. The message transmission method based on SRIO time division multiplexing and demultiplexing according to claim 6, wherein: in step S2, the polling counter cnt1 determines and accumulates the channel for selecting read data according to the value of the polling counter cnt1 at that time, and when the polling counter cnt1 polls that the write completion flag wr _ done _ flag of two or more channels is valid, the priority dynamic adjustment mode is started.

9. The message transmission method based on SRIO time division multiplexing and demultiplexing according to claim 6, wherein: the state flow chart of the state machine of the time division multiplexing module MUX is specifically represented as follows:

state 1: in the initial state, signals such as a polling counter cnt1 and a waiting counter cnt2 are reset at the beginning; when the polling counter cnt1 detects that the write completion flag register wr _ done _ reg is valid, triggering to enter a state 2, and if the write completion flag register wr _ done _ reg is invalid, circulating in the state 1 all the time;

state 2: polling state, polling the write completion mark of each channel; the polling mode is priority dynamic adjustment, the priority is determined according to the value of a current polling counter cnt1, the polling counter cnt1 starts to circularly count from 0, the counting range is 0-p, when a write completion flag register wr _ done _ reg [ cnt1] is detected to be effective, the polling is finished, the polling counter cnt1 stops counting, the state 3 is triggered to enter, and if the write completion flag register wr _ done _ reg [ cnt1] is ineffective, the state 2 is always circulated;

and a state 3: waiting for the counter cnt2 to start to count circularly from 0, wherein the counting range is 0-q, and simultaneously adding frame headers of each channel according to a time division multiplexing interface protocol, the length of each frame header is 1 byte, when detecting that cnt2 is q, triggering to enter a state 4, and if cnt2 is smaller than q, circulating in a state 3 all the time;

and 4: and reading the state, pulling up the read enable rd [ cnt1] of the FIFO memory of the corresponding channel, triggering to return to the state 1 when the FIFO empty flag empty [ cnt1] is read to be effective, and entering the next polling operation, otherwise, circulating in the state 4 all the time.

10. The message transmission method based on SRIO time division multiplexing and demultiplexing according to claim 6, wherein: in step S3, the SRIO interface protocol includes an initiation request ireq, an initiation response iresp, a target request treq, and a target response tresp.

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