CN115706871A - Image sensor, reading method and electronic device - Google Patents

Abstract

The present application discloses an image sensor, an image readout method, and an electronic device, wherein the image sensor includes: a pixel array and a plurality of readout conversion circuits, and the readout conversion circuits include: a comparison circuit, and the corresponding row of pixels The output terminal is connected, and is used to compare the output signal of the column pixel with the slope signal and output the pulse signal to obtain the first output signal and the second output signal; the selection module is used for gating the comparison circuit during the first sampling count The first output signal, when sampling and counting for the second time, gates the second output signal of the comparison circuit; the counter is used for counting according to the first output signal and the second output signal of the comparison circuit, and obtains the first sampling count and the second output signal The total amount of quantization values counted by subsampling to get the actual signal quantization result based on the total amount of quantization values. The present application can increase the image readout speed of the image sensor, and the cost is low.

Description

Image sensor, readout method and electronic device

technical field

The present application relates to the field of image technology, in particular to an image sensor, an image readout method and electronic equipment.

Background technique

An image sensor is an important part of a digital camera and is a device that converts an optical image into an electrical signal. It is widely used in electronic devices such as digital cameras, mobile terminals, and portable electronic devices. Image sensors include CCD (Charge Coupled Device, Charge Coupled Device) image sensor and CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) image sensor two categories, and CMOS image sensor has high integration, low power consumption, speed Fast, low cost and other advantages, has been widely used in many products. These products include mobile phones, tablet computers, cars, and security monitoring systems.

At present, it is difficult to realize effective correlated double sampling in the pixel array readout method of the CMOS image sensor. Usually, the pixel array readout method of CMOS image sensor adopts the method of digital correlation double sampling, the first sampling is to quantize the count down of the reset signal, and the counting result is kept as the starting point of the second counting. The initial value, the second sampling is the quantization of counting up the signal, and the correlated double sampling in the digital domain is realized by counting in the opposite direction twice.

The above-mentioned sampling method needs to be switched between counting down and counting up, so that the image readout of the pixel array takes a long time and the speed is slow. In addition, additional holding circuits and switching circuits need to be added, and the cost is high.

The foregoing description is provided to provide general background information and does not necessarily constitute prior art.

Contents of the invention

The purpose of the present application is to provide an image sensor, an image readout method, and an electronic device, which can increase the image readout speed of the image sensor and have low cost.

In order to achieve the above object, the technical solution of the present application is achieved in this way:

In a first aspect, an embodiment of the present application provides an image sensor, including:

a pixel array comprising a plurality of pixels arranged in rows and columns; and

A plurality of readout conversion circuits, each of which corresponds to at least one column of pixels in the pixel array;

Wherein, the readout conversion circuit includes:

The comparison circuit is connected to the output terminal of the corresponding row of pixels, and is used to compare the output signal of the row of pixels with the ramp signal to output the pulse signal, so as to obtain the first output signal and the second output signal;

The selection module is connected with the comparison circuit, and is used for selecting the first output signal of the comparison circuit when the first sampling count is performed, and selecting the second output signal of the comparison circuit when the second sampling count is performed. output signal;

A counter, connected to the output terminal of the selection module, for counting according to the first output signal and the second output signal of the comparison circuit, to obtain the first sampling count and the second sampling count The total amount of quantized values is used to obtain an actual signal quantization result based on the total amount of quantized values.

Optionally, the counter performs counting in a manner of counting down twice or counting up twice according to the first output signal and the second output signal of the comparison circuit, so as to obtain the total amount of quantized values.

Optionally, the comparison circuit includes a comparator, a first capacitor and a second capacitor, the first input terminal of the comparator is connected to the output terminal of the pixel through the first capacitor, and the second input terminal of the comparator is connected to the output terminal of the pixel through the The second capacitor receives the ramp signal; and/or, the comparison circuit has a first output terminal and a second output terminal, the first output terminal is used to output the first output signal, and the second output terminal is used for The second output signal is output, and the first output terminal and the second output terminal of the comparator are connected to the input terminal of the selection module.

Optionally, the selection module includes a first control element and a second control element, the first control element and the second control element are controlled by an output selection control signal, wherein, when the output selection control signal is in the first When the first level is at a level, the first output signal of the comparison circuit is selected based on the first control element; when the output selection control signal is at a second level, the output signal of the comparison circuit is selected based on the second control element. Second output signal.

Optionally, the delay of the path gated based on the first control element is the same as the delay of the path gated based on the second control element.

Optionally, the selection module is also controlled based on the counting enable control signal, and the high level time period controlled by the counting enable control signal corresponds to at least the output of the first output signal and the second output signal respectively. period.

Optionally, the selection module includes a connected selector and an AND gate circuit, the selector receives the first output signal and the second output signal and forms an output signal of the first selection module; the AND gate The circuit receives the output signal of the first selection module and the count enable control signal to obtain the output signal of the second selection module, and the output signal of the second selection module is used as the output signal of the selection module.

Optionally, one input end of the counter is connected to the output end of the selection module, and the other input end receives a clock signal; the counter includes an N-bit counter.

Optionally, the image sensor further includes a storage circuit, and the signal output by the counter is input to the storage circuit for storage.

Optionally, the first sampling count corresponds to a reset signal quantization result, the second sampling count corresponds to an image signal quantization result, and the actual signal quantization result is composed of the image signal quantization result and the reset signal quantization result The difference constitutes.

Optionally, the first sampling count is performed in the first time period, the second sampling count is performed in the second time period, and it is defined that the corresponding preset quantization result within the preset time period, wherein the actual The quantization result of the reset signal is equal to the preset quantization result minus the quantization result of the first time period, so as to obtain the actual signal quantization result based on the preset quantization result and the total amount of quantization values.

Optionally, during the first sampling and counting, when the output of the selection module is the first level, the counter starts to count down or up, and the count value is codex; during the second sampling and counting, when the output of the selection module is When it is at the first level, the counter continues to count down or up on the basis of the first count, and the count value is code_total=codex+codey; wherein, the preset time period is TA, and the corresponding preset quantization result is code_TA, the quantization result of the reset signal is obtained as code_rst=code_TA-codex, and the quantization result of the actual signal is code_sig=code_total-code_TA.

In a second aspect, an embodiment of the present application provides an electronic device, including the image sensor described in any one of the above solutions.

In the third aspect, the embodiment of the present application provides an image readout method of an image sensor, wherein the readout method can be implemented based on the image sensor described in any one of the above solutions, of course, other sensors can also be used to implement . Wherein, the readout method includes:

selecting the output row based on the row selection line, and outputting the output signal of the column pixel to the comparison circuit based on the column selection line;

The comparison circuit compares the output signal of the column pixel with the slope signal and outputs the pulse signal to obtain the first output signal and the second output signal;

When sampling and counting for the first time, the first output signal of the comparison circuit is selected by the selection module, and when the second sampling and counting is performed, the second output signal of the comparison circuit is selected;

The counter counts according to the first output signal and the second output signal of the comparison circuit to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the total quantized value based on the total quantized value Actual signal quantization results.

The beneficial effects brought by the technical solutions provided by the embodiments of the present application are:

In the image sensor, image readout method and electronic equipment provided by the embodiments of the present application, the column pixel data is compared with the ramp signal through the comparison circuit to output the pulse signal; output signal, when sampling and counting for the second time, the second output signal of the gate comparison circuit; the counter counts according to the first output signal and the second output signal of the comparison circuit, and obtains the first sampling count and the The total quantized value of the second sampling count is used to obtain the actual signal quantized result based on the total quantized value, so that the quantized value of the actual signal of the image can be obtained only by two unidirectional samplings, and no additional maintenance is required The circuit and the switching circuit can increase the image readout speed of the image sensor, and the cost is low.

Description of drawings

FIG. 1 is a structural block diagram of an image sensor provided in an embodiment of the present application;

Fig. 2 is a block diagram of the read conversion circuit of Fig. 1;

Fig. 3 is a timing diagram of image sensor control when counting down is adopted;

Fig. 4 shows a schematic diagram of a counter structure.

FIG. 5 is a schematic flowchart of an image readout method of an image sensor provided by an embodiment of the present application.

Detailed ways

The technical solution of the present application will be further elaborated below in combination with the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

FIG. 1 is a structural block diagram of an image sensor provided by an embodiment of the present application. FIG. 2 is a block diagram of the readout switching circuit of FIG. 1 . Figure 3 is a timing diagram of image sensor control when counting down is adopted. Fig. 4 shows a schematic diagram of a counter structure. Please refer to FIG. 1 to FIG. 4 , the image sensor of this embodiment includes: a pixel array 110 . Pixel array 110 includes a plurality of pixels arranged in rows and columns. Each column of pixels in the pixel array 110 is turned on by a column selection line, and each row of pixels is respectively turned on by a row selection line. Each pixel has a row address and a column address. The row address of the pixel corresponds to the row selection line driven by the row decoding and driving circuit 120 , and the column address of the pixel corresponds to the column selection line driven by the column decoding and driving circuit 130 . The control circuit 140 controls the row decoding and driving circuit 120 and the column decoding and driving circuit 130 to selectively read output signals of pixels corresponding to appropriate rows and columns in the pixel array.

The output signal of the pixel includes a pixel reset signal and a pixel image signal, and the pixel reset signal represents the signal obtained by the floating diffusion region of the photosensitive device (such as a photodiode) during reset. The pixel image signal represents the signal obtained after the image-representing charge captured by the photosensitive device is transferred to the floating diffusion region. Both the pixel reset signal and the pixel image signal are read and processed by a plurality of readout conversion circuits 150, and digitalized image signals are output to obtain actual signals required.

As shown in FIG. 2 , it is a block diagram of a readout conversion circuit, each of which corresponds to at least one column of pixels in the pixel array. The readout conversion circuit includes: a comparison circuit 202 , a selection module 203 , and a counter 204 . Figure 2 only illustrates a column output line of a pixel array. In one example, the outputs of all pixels in the column in the pixel array are connected to the column output line 210. Clamp pixels etc. to the output line for that column.

The comparison circuit 202, the selection module 203, and the counter 204 jointly complete the conversion from the analog signal to the digital signal. The comparison circuit 202 is connected to the output terminal of the corresponding column pixel, and is used for comparing the output signal of the column pixel with the ramp signal to output a pulse signal, and the width of the pulse signal represents the strength of the signal. Wherein, the comparison circuit can obtain at least two output signals, that is, a first output signal and a second output signal. Optionally, the first output signal and the second output signal are respectively provided by the comparison circuit with a first An output terminal cmp_out_b and a second output terminal cmp_out output.

Specifically, in an example, the comparison circuit 202 includes a comparator, a first capacitor C1 and a second capacitor C2, the first input terminal of the comparator is connected to the output terminal of the pixel through the first capacitor C1, and the second input terminal of the comparator terminal is connected to the ramp generator 206 through the second capacitor C2 to receive the ramp signal, and the first output terminal cmp_out_b and the second output terminal cmp_out of the comparator are connected to the input terminal of the selection module 203 . It should also be noted that the comparison circuit can be realized by using any comparator in the prior art that can realize the above functions.

In one embodiment, the image sensor may further include a ramp generator 120 connected to the input terminal of the comparison circuit for outputting a ramp signal to the comparison circuit for resetting the comparator. Wherein, the slope generator can adopt the slope generator used in the pixel readout of the existing image sensor to generate the reset signal and the pulse wave of the image signal correspondingly, so as to obtain the actual demand for correlated double sampling based on it. image signal.

In one embodiment, the output terminal cmp_out_o of the selection module 203 is connected to an input terminal of the counter 204 . The counter 204 may be an N-bit counter, and the other input terminal of the counter 204 receives the clock signal count_clk_o. The counter 204 is used for counting the signal output by the selection module 203 to obtain an actual image signal. In an example, the structure of the counter can be referred to as shown in FIG. 4 .

In one embodiment, the selection module 203 is connected with the comparison circuit, and is used for gating the first output signal of the comparison circuit during the first sampling count, such as the signal output from the first output terminal of the comparison circuit; When sub-sampling is counted, the second output signal of the selection module gating comparison circuit, as can be the signal output by the second output end of the comparison circuit; the counter is connected with the output end of the selection module, and is used to Counting the signal output by the terminal and the signal output by the second output terminal to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the actual signal quantization result based on the total quantized value. It should be noted that the selection module can be implemented by any circuit in the prior art that can realize the above functions.

In one embodiment, the counter counts down or up twice according to the signal output by the first output terminal of the comparison circuit and the signal output by the second output terminal, so as to obtain the total quantized value quantity. That is, when counting for the first sampling, the counter counts in the way of counting down, such as counting down when the rising edge of the clock comes, and continues. On the basis of counting, continue to count down. Similarly, counting can also be performed in the manner of counting up twice.

In one embodiment, the selection module 203 includes a first control element (not shown in the figure) and a second control element (not shown in the figure), and both the first control element and the second control element output The selection control signal count_out_sel (as shown in FIG. 2 ) controls, and in an alternative example, the first control element and the second control element may be two switches. Wherein, when the output selection control signal is at the first level (eg, low level), the signal output from the first output terminal cmp_out_b of the comparison circuit (ie, the first output signal); when the output selection control signal is at the second level (eg, high level), the signal output by the second output terminal cmp_out of the comparison circuit is selected based on the second control element (ie, the second output signal).

In an example, the delay of the path gated based on the first control element is the same as the delay of the path gated based on the second control element.

As an example, the selection module 203 is also controlled based on the count enable control signal count_en_o, and the high level time period controlled by the count enable control signal at least corresponds to covering the output of the first output signal and the second output signal respectively. time period.

In an example, as shown in FIG. 2, the selection module includes a selector MUX connected to an AND gate circuit AND, and the selector receives the first output signal and the second output signal and forms a first Selection module output signal; the AND gate circuit receives the first selection module output signal and the count enable control signal count_en_o to obtain a second selection module output signal, and the second selection module output signal is used as the selection The output signal of the module.

In one embodiment, the image sensor may further include a storage circuit 205, which may be a SRAM, and the counter 204 is connected to the storage circuit 205, and the signal output by the counter 204 is input to the storage circuit for storage.

In order to reduce the difference due to different pixels, a double-correlation sampling technique is used to read out the signal. In one imaging, two samplings of the reset signal of the pixel and the image signal of the pixel are performed. The N-bit counter uses two-way sampling technology to perform double-correlation sampling. Digital correlation double-sampling is to quantify the reset signal and the actual signal separately and make a difference in the digital domain, which can offset the noise and mismatch of the pixel array and the readout circuit to the greatest extent. , effectively eliminates system noise.

In one embodiment, the first sampling count corresponds to a reset signal quantization result, the second sampling count corresponds to an image signal quantization result, and the actual signal quantization result obtained based on the total amount of quantized values is determined by the The difference between the quantization result of the image signal and the quantization result of the reset signal is constituted.

In one embodiment, the first sampling count is performed in a first time period, the second sampling count is performed in a second time period, and the corresponding preset quantization result is defined within a preset time period, wherein, The preset time period is equal to the sum of the reset signal counting time period and the first time period, that is, the actual quantization result of the reset signal is equal to the preset quantization result minus the quantization of the first time period As a result, the actual signal quantization result is obtained based on the preset quantization result and the total quantization value. It should be noted that, in the present invention, the actual reset signal is not quantized directly, but is calculated based on the quantization result of the first time period, so as to obtain the actual signal quantization result.

In a further example, the selection module is also controlled based on the count enable control signal count_en_o, and the count enable control signal controls the working time period of the counter to cover the preset time period, that is, the count enable control signal controls The high-level period of time covers the preset time period. Wherein, in the process controlled by the counting enable control signal count_en_o, its time sequence may include multiple high level time periods.

In one embodiment, the selection module is used to gate the path between the first output terminal of the comparator and the output terminal of the selection module when the first sampling count is performed, and the output of the selection module is the first level (eg, high level), the counter starts to count down or up, and the count value is codex, and the count corresponds to the first time period; the selection module is used to gate the first comparator when counting for the second time The path between the two output terminals and the output terminal of the selection module, and when the output of the selection module is the first level (eg, high level), the counter continues to count down or up on the basis of the first count , the count value is code_total=codex+codey, and the count corresponds to the second time period; wherein, the preset time period is TA, and the corresponding preset quantization result is code_TA, and the quantization result of the reset signal is code_rst=code_TA -codex, and the actual signal quantization result is code_sig=codey-code_rst=codey-(code_TA-codex)=codey+codex-code_TA=code_total-code_TA.

Specifically, the quantization result of the reset signal can be obtained for the first sampling count, that is, when the first sampling count is performed, the selection module 203 gates the path between the first output terminal cmp_out_b of the comparator and the output terminal cmp_out_o of the selection module 203, When the output of the first output terminal cmp_out_b of the comparator is the first level (such as high level) (at this time, the output of the selection module is also the first level), the counter can count down or up, for example, from 0 (that is, the counter counts Decrease step by step or increase the counter count step by step), the count value is codex. In addition, for the reference quantity TA, the corresponding total count value is code_TA (that is, code_TA is the corresponding preset quantization result), and TA is the preset time period; thus, the quantization result of the reset signal is code_rst=code_TA-codex.

The second sampling count can obtain the quantized result of the image signal, that is, during the second sampling count, the selection module 203 gates the path between the second output terminal cmp_out of the comparator and the output terminal cmp_out_o of the selection module 203, and the comparator When the second output terminal cmp_out of the output is the first level (for example, high level) (at this time, the output of the selection module is also the first level), the counter continues to count down or up on the basis of the first count, counting The value is code_total. In fact, since the count is based on the previous count, code_total is actually equal to codex+codey, where codey is the actual count value of the second sampling count. The quantization result of the actually output image signal is code_sig=codey-code_rst=codey-(code_TA-codex)=codey+codex-code_TA=code_total-code_TA. That is to say, the quantization result of the actually output image signal is code_sig=code_total-code_TA (that is, the difference between the count value of the second sampling count and the total count value of the first sampling count). In this way, both counts are counted down or counted up, and no additional holding circuit and switching circuit are needed, which improves the image readout speed and is low in cost.

Figure 3 is the image sensor control timing diagram when counting down, as shown in Figure 3, suitable for application to the readout conversion circuit in Figure 2, bitline represents the output signal of the pixel, vramp represents the output signal of the ramp generator, cmp_out_o _ represents the output signal of the selection module, count_clk_o represents the clock signal, count_en_o represents the count enable control signal, and comp_out_sel represents the output selection control signal.

Wherein, in an example, the starting point of the codex stage is the intersection of the output signal vramp of the ramp generator and the output signal bitline of the pixel, which corresponds to a time period when the ramp signal is smaller than the output signal of the pixel. In an example, the selected first time period has a certain time extension at the end relative to the above time period, as shown in FIG. 3 . In addition, the second time period corresponding to the second sampling count corresponds to the time period when the ramp signal is greater than the pixel output when the image signal is output. The expansion of time T, as shown in Figure 3. In addition, the preset time period TA may be a time period corresponding to a slope signal greater than the pixel output when the reset signal is output and further extended to include the first time period. In an example, the selected preset time period has an extension T of a certain time before sampling starts relative to the above time period, as shown in FIG. 3 .

In this application, the image signal is well processed by the read conversion circuit, so as to obtain the quantized value of the actual output image signal. Specifically, the comparator compares the output signal of the pixel of the pixel array with the ramp signal of the ramp signal generator, and outputs a pulse signal, the width of the pulse signal represents the strength of the signal. The pulse signal is sampled and counted down or up twice by the counter, and the quantized result of the actually output image signal is formed by the difference between the quantized result of the image signal and the quantized result of the reset signal.

Based on the same idea as the foregoing embodiments, embodiments of the present application provide an electronic device, where the electronic device includes the image sensor in the foregoing embodiments. An electronic device may be, for example, a camera, a cell phone, a personal digital assistant, a computer, a monitoring device, a machine vision device, and the like.

In summary, the image sensor and the electronic device provided by the embodiment of the present application compare the column pixel data with the ramp signal through the comparison circuit and output the pulse signal; The signal output by the output end, when sampling and counting for the second time, the signal output by the second output end of the gating comparison circuit; Counting, to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the actual signal quantization result based on the total quantized value, so that the actual signal of the image can be obtained only by two sampling The quantization value of the method does not require additional holding circuits and switching circuits, and the image readout speed of the image sensor can be improved, and the cost is low.

The following are method embodiments of the present application. For details not described in detail in the method embodiments, reference may be made to the above-mentioned corresponding device embodiments.

FIG. 5 is a schematic flowchart of an image readout method of an image sensor provided by an embodiment of the present application. Wherein, the image readout method of the image sensor is implemented based on the image sensor provided by the present invention. That is to say, before performing the first step of the method, it also includes providing the image sensor as described in any one of the above schemes; and then each step in the method is performed based on the structure of the response of the image sensor. Of course, the readout method provided by the present invention can also be realized by other sensors. Please refer to FIG. 5, the image readout method of the image sensor is applied to the image sensor and electronic equipment, and the image readout method of the image sensor described in this embodiment includes the following steps:

Step S401 , select an output row based on the row selection line, and output the output signal of the column pixel to the comparison circuit based on the column selection line.

In step S403 , the comparison circuit compares the output signal of the column pixel with the ramp signal and outputs a pulse signal, so as to obtain a first output signal and a second output signal.

Step S405, during the first sampling count, the selection module gates the first output signal of the comparison circuit, and during the second sampling count, gates the second output signal of the comparison circuit.

Step S407, the counter counts according to the first output signal and the second output signal of the comparison circuit, and obtains the total quantized value of the first sampling count and the second sampling count, so as to obtain the quantized value based on the quantized value The total amount obtains the actual signal quantization result.

Specifically, in step S407, the counter counts according to the signal output by the first output terminal of the comparison circuit and the signal output by the second output terminal, and obtains the quantization of the first sampling count and the second sampling count The total value can be subdivided into the following steps: the counter counts according to the signal output by the first output terminal of the comparison circuit and the signal output by the second output terminal by twice downward or twice upward counting, to obtain the total amount of quantized values.

Specifically, step S407 can also be refined into the following steps:

The counter counts in two down or two up ways according to the signal output by the first output terminal of the comparison circuit and the signal output by the second output terminal, so as to obtain the total amount of quantized values; or

The first sampling count is performed in the first time period, the second sampling count is performed in the second time period, and the corresponding preset quantization result is defined within the preset time period, wherein the preset time period equal to the sum of the reset signal counting time period and the first time period, so as to obtain the actual signal quantization result based on the preset quantization result and the total amount of quantization values; or

When counting for the first sampling, the selection module gates the path between the first output terminal of the comparator and the output terminal of the selection module, and when the output of the selection module is the first level, the counter starts to go down or Count up, and the count value is codex; when counting for the second time, when the output of the selection module is the first level, the counter continues to count down or up on the basis of the first count, and the count value is code_total=codex +codey; wherein, the preset time period is TA, and the corresponding preset quantization result is code_TA, the reset signal quantization result is code_rst=code_TA-codex, and the actual signal quantization result is code_sig=code_total- code_TA.

To sum up, in the image readout method of the image sensor provided by the embodiment of the present application, the comparison circuit compares the column pixel data with the ramp signal to output the pulse signal; The signal output by the first output end, when sampling and counting for the second time, the signal output by the second output end of the gating comparison circuit; The signal is counted to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the actual signal quantization result based on the total quantized value, so that an image can be obtained only by two sampling The quantized value of the actual signal does not require an additional holding circuit and switching circuit, which can increase the image readout speed of the image sensor, and has low cost.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element. In addition, different implementations of the present application Components, features, and elements with the same name in the example may have the same meaning, or may have different meanings, and the specific meaning shall be determined based on the explanation in the specific embodiment or further combined with the context in the specific embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word "if" as used herein may be interpreted as "at" or "when" or "in response to a determination". Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising", "comprising" indicate the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not exclude one or more other features, steps, operations, The existence, occurrence or addition of an element, component, item, species, and/or group. The terms "or" and "and/or" as used herein are to be construed as inclusive, or to mean either one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C" . Exceptions to this definition will only arise when combinations of elements, functions, steps or operations are inherently mutually exclusive in some way.

It should be understood that although the various steps in the flow chart in the embodiment of the present application are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figure may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order is not necessarily sequential Instead, it may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (15)

1. An image sensor, comprising:

a pixel array including a plurality of pixels arranged in rows and columns; and

a plurality of readout conversion circuits, each corresponding to at least one column of pixels in the pixel array;

wherein the readout conversion circuit includes:

the comparison circuit is connected with the output end of the corresponding column pixel and is used for comparing the output signal of the column pixel with the ramp signal and outputting a pulse signal to obtain a first output signal and a second output signal;

the selection module is connected with the comparison circuit and used for gating a first output signal of the comparison circuit during the first sampling counting and gating a second output signal of the comparison circuit during the second sampling counting;

and the counter is connected with the output end of the selection module and is used for counting according to the first output signal and the second output signal of the comparison circuit to obtain the total quantization value of the first sampling count and the second sampling count so as to obtain an actual signal quantization result based on the total quantization value.

2. The image sensor as claimed in claim 1, wherein the counter counts down twice or up twice based on the first output signal and the second output signal of the comparison circuit to obtain the total amount of the quantization value.

3. The image sensor of claim 1, wherein the comparison circuit comprises a comparator, a first capacitor, and a second capacitor, a first input of the comparator is connected to an output of the pixel through the first capacitor, and a second input of the comparator receives the ramp signal through the second capacitor; and/or the comparison circuit is provided with a first output end and a second output end, the first output end is used for outputting the first output signal, the second output end is used for outputting the second output signal, and the first output end and the second output end of the comparator are connected with the input end of the selection module.

4. The image sensor of claim 1, wherein the selection module comprises a first control element and a second control element, the first control element and the second control element controlled by an output selection control signal, wherein when the output selection control signal is at a first level, a first output signal of the comparison circuit is gated based on the first control element; gating a second output signal of the comparison circuit based on the second control element when the output select control signal is at a second level.

5. The image sensor of claim 4, wherein a delay of a path gated based on the first control element is the same as a delay of a path gated based on the second control element.

6. The image sensor of claim 1, wherein the selection module is further controlled based on a count enable control signal, the high level time period controlled by the count enable control signal corresponding to at least a time period covering the first output signal and the second output signal output, respectively.

7. The image sensor of claim 6, wherein the select module comprises a selector and an AND circuit connected, the selector receiving the first output signal and the second output signal and forming a first select module output signal; and the AND gate circuit receives the output signal of the first selection module and the counting enabling control signal to obtain an output signal of a second selection module, and the output signal of the second selection module is used as the output signal of the selection module.

8. The image sensor of claim 1, wherein one input of the counter is connected to the output of the selection module, and the other input receives a clock signal; the counter comprises an N-bit counter.

9. The image sensor of claim 1, further comprising a storage circuit to which the signal output by the counter is input for storage.

10. The image sensor of any of claims 1-9, wherein the first sample count corresponds to a reset signal quantization result and the second sample count corresponds to an image signal quantization result, the actual signal quantization result being formed by a difference between the image signal quantization result and the reset signal quantization result.

11. The image sensor as claimed in claim 10, wherein the first sampling count is performed for a first time period, the second sampling count is performed for a second time period, and a preset quantization result corresponding to a preset time period is defined, wherein a quantization result of an actual reset signal is equal to the preset quantization result minus a quantization result of the first time period, so as to obtain the actual signal quantization result based on the preset quantization result and the total amount of quantization values.

12. The image sensor of claim 11, wherein at a first sample count, when the selection module output is at a first level, the counter starts counting down or up, the count value being codex; during the second sampling counting, when the output of the selection module is at the first level, the counter continues to count downwards or upwards on the basis of the first counting, and the counting value is code _ total = code + code; the preset time period is TA, the corresponding preset quantization result is code _ TA, the obtained reset signal quantization result is code _ rst = code _ TA-code, and the actual signal quantization result is code _ sig = code _ total-code _ TA.

13. An electronic device, characterized in that it comprises an image sensor according to any one of claims 1-12.

14. An image readout method of an image sensor, comprising:

selecting an output row based on a row selection line, and outputting output signals of the row pixels to a comparison circuit based on a column selection line;

the comparison circuit compares the output signal of the column pixel with the ramp signal to output a pulse signal so as to obtain a first output signal and a second output signal;

the selection module gates a first output signal of the comparison circuit during the first sampling counting, and gates a second output signal of the comparison circuit during the second sampling counting;

and the counter counts according to the first output signal and the second output signal of the comparison circuit to obtain the total quantization value of the first sampling count and the second sampling count so as to obtain an actual signal quantization result based on the total quantization value.

15. The image readout method according to claim 14, wherein the image readout method is implemented based on the image sensor according to any one of claims 1 to 12.

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