CN115699301A - Power device, preparation method of power device, driving circuit and integrated circuit board - Google Patents
Power device, preparation method of power device, driving circuit and integrated circuit board Download PDFInfo
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- CN115699301A CN115699301A CN202180009730.6A CN202180009730A CN115699301A CN 115699301 A CN115699301 A CN 115699301A CN 202180009730 A CN202180009730 A CN 202180009730A CN 115699301 A CN115699301 A CN 115699301A
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- China
- Prior art keywords
- power device
- voltage
- conductive bump
- electrode
- gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/004—Details
- H01G9/08—Housing; Encapsulation
- H01G9/10—Sealing, e.g. of lead-in wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/02—Soldered or welded connections
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一种功率器件、功率器件的制备方法、驱动电路及集成电路板，用以解决顶层焊盘氧化导致的功率器件的导通电阻变大、导通电阻的批次不良的问题，使得功率器件的导通电阻回归正常值。其中，功率器件包括裸片，以及在裸片之上依次堆叠的第一顶层焊盘、第一氧化层、第一种子层和第一导电凸块，还包括在裸片之上依次堆叠的第二顶层焊盘、第二氧化层、第二种子层和第二导电凸块，第一顶层焊盘通过裸片与第二顶层焊盘连通。
A power device, a preparation method of the power device, a driving circuit, and an integrated circuit board are used to solve the problems of large on-resistance of the power device and poor batches of the on-resistance caused by the oxidation of the top pad, so that the power device On-resistance returned to normal value. Wherein, the power device includes a bare chip, and a first top-layer pad, a first oxide layer, a first seed layer, and a first conductive bump stacked sequentially on the bare chip, and also includes a first layer stacked sequentially on the bare chip. Two top pads, a second oxide layer, a second seed layer and a second conductive bump, the first top pad communicates with the second top pad through the die.
Description
PCT国内申请，说明书已公开。PCT domestic application, specification has been published.
Claims (20)
- A power device is characterized by comprising a bare chip, a first top layer bonding pad, a first oxidation layer, a first seed layer and a first conductive bump which are sequentially stacked on the bare chip, and a second top layer bonding pad, a second oxidation layer, a second seed layer and a second conductive bump which are sequentially stacked on the bare chip, wherein the first top layer bonding pad is communicated with the second top layer bonding pad through the bare chip.
- The power device of claim 1, wherein the first oxide layer and the second oxide layer are broken down.
- The power device according to claim 1 or 2, wherein when a first voltage that increases in steps is applied between the first conductive bump and the second conductive bump, a ratio of the first voltage to a first current flowing between the first conductive bump and the second conductive bump reaches a nominal range of an on-resistance value of the power device.
- The power device of any of claims 1-3, wherein the first conductive bump is used to form a drain of the power device and the second conductive bump is used to form a source of the power device.
- The power device of any of claims 1-4, further comprising a third top layer pad, a third oxide layer, a third sub-layer, and a third conductive bump stacked in sequence over the die, and a fourth top layer pad, a fourth oxide layer, a fourth sub-layer, and a fourth conductive bump stacked in sequence over the die, the third top layer pad in communication with the fourth top layer pad through the die.
- The power device of claim 5, wherein the third oxide layer and the fourth oxide layer are broken down.
- The power device according to claim 5 or 6, wherein, when a second voltage that increases in steps is applied between the third conductive bump and the fourth conductive bump, a ratio of the second voltage to a second current flowing between the third conductive bump and the fourth conductive bump reaches a nominal range of a ratio of a voltage applied to a gate of the power device to a current flowing therethrough.
- The power device of claim 7, wherein the third conductive bump or the fourth conductive bump is used to form a gate of the power device.
- The power device of any of claims 1-8, wherein the first conductive bump and the second conductive bump are coupled to two output terminals of a first voltage source or current source, respectively, the first voltage source or current source for outputting the first voltage.
- The power device according to any one of claims 5 to 9, wherein the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of a second voltage source for outputting the second voltage.
- A method of manufacturing a power device, the power device including a first electrode, a second electrode, and a first oxide layer and a second oxide layer between the first electrode and the second electrode, the method comprising:and applying a first voltage between the first electrode and the second electrode, so that the ratio of the first voltage to a first current reaches a calibrated range of the on-resistance value of the power device, wherein the first current is the current flowing between the first electrode and the second electrode.
- The method of claim 11, wherein a ratio of the first voltage to the first current is a sum of equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.
- The method of claim 11 or 12, wherein the power device further comprises a first gate, a second gate, and a third oxide layer and a fourth oxide layer between the first gate and the second gate, the method further comprising:and applying a second voltage between the first grid and the second grid so that the ratio of the second voltage to a second current reaches a calibrated range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid, wherein the second current is the current flowing between the first grid and the second grid.
- The method of claim 13, wherein a ratio of the second voltage to the second current is a sum of equivalent resistances of the first gate, the second gate, the third oxide layer, and the fourth oxide layer.
- The method of any one of claims 11-14, wherein applying a first voltage between the first electrode and the second electrode comprises:the first voltage is applied between the first electrode and the second electrode by a first voltage source or current source.
- The method of any of claims 13 to 15, wherein applying a second voltage between the first gate and the second gate comprises:applying the second voltage between the first gate and the second gate by a second voltage source.
- The method of any one of claims 11-16, wherein the first electrode is a drain electrode and the second electrode is a source electrode.
- The method of any one of claims 13 to 17, further comprising:and applying a control signal to the power device through the first gate or the second gate to control the power device to be switched on and off.
- A driving circuit comprising a gate driver and a power device according to any one of claims 1 to 10; wherein the third and fourth conductive bumps of the power device are coupled to a signal output of the gate driver.
- An integrated circuit board comprising a circuit board body and a power device according to any one of claims 1 to 10, or comprising a driver circuit according to claim 19; the circuit board body is provided with a pin, and the power device is electrically connected with the circuit board body through the pin.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2021/097436 WO2022252060A1 (en) | 2021-05-31 | 2021-05-31 | Power device, preparation method for power device, drive circuit, and integrated circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115699301A true CN115699301A (en) | 2023-02-03 |
Family
ID=84322624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180009730.6A Pending CN115699301A (en) | 2021-05-31 | 2021-05-31 | Power device, preparation method of power device, driving circuit and integrated circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115699301A (en) |
| WO (1) | WO2022252060A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7005752B2 (en) * | 2003-10-20 | 2006-02-28 | Texas Instruments Incorporated | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
| US8698308B2 (en) * | 2012-01-31 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structural designs to minimize package defects |
| US8957694B2 (en) * | 2012-05-22 | 2015-02-17 | Broadcom Corporation | Wafer level package resistance monitor scheme |
| CN104241102A (en) * | 2014-08-26 | 2014-12-24 | 南通富士通微电子股份有限公司 | Under bump metal layer sputtering method |
| CN105006437B (en) * | 2015-07-28 | 2018-06-26 | 江阴长电先进封装有限公司 | A kind of manufacturing method of high density projection cube structure |
| US10026707B2 (en) * | 2016-09-23 | 2018-07-17 | Microchip Technology Incorportated | Wafer level package and method |
-
2021
- 2021-05-31 CN CN202180009730.6A patent/CN115699301A/en active Pending
- 2021-05-31 WO PCT/CN2021/097436 patent/WO2022252060A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022252060A1 (en) | 2022-12-08 |
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