CN115550286A - PCIe switch management device and method and PCIe switch - Google Patents

Abstract

The present application belongs to the technical field of PCIe communication, and in particular relates to a PCIe switch management device and method and a PCIe switch. Through the PCIe switch management device provided in this application, the coordinated control of the PCIe switch link and power management can be realized, thereby realizing the low power consumption conversion of the PCIe switch. The device includes a first control module, a second control module and a global power management module, the first control module is used to monitor the first link state of the first link; the global power management module is used to A first control signal is generated; a second control module is configured to update a second link state of the second link according to the first control signal, and the updated second link state is the same as the first link state.

Description

A PCIe switch management device, method and PCIe switch

technical field

The present application belongs to the technical field of PCIe communication, and in particular relates to a PCIe switch management device and method and a PCIe switch.

Background technique

The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) is widely used in fields such as data acquisition and storage. The power states of the PCIe switches connected to the PCIe bus include device power states (device power states, D-states for short) and link power states (link power states, L-states for short).

The PCIe protocol specifies two power management mechanisms, namely, a PCI power management (PCI-PM) mechanism and an active state power management (Active State Power Management, ASPM). The PCIe protocol stipulates that the device power state includes D0 state, D1 state, D2 state, D3hot state, D3cold state, and the like. The PCIe protocol stipulates that the link power state includes L0 state, L0s state, L1 state, L2/3ready state, L2 state, L3 state and other states. The ASPM mechanism only works in the D0 power state, and its possible link states are L0, L0s and L1. The PCI-PM mechanism works in any power state. However, the PCIe protocol does not specifically specify how to achieve low power consumption inside the device when the PCIe switch enters a certain state. Therefore, it is urgent to provide a PCIe switch management method.

Contents of the invention

In view of this, the embodiment of the present application provides a PCIe switch management device, method and PCIe switch, and the method can realize low power consumption setting of the device PCIe switch on the premise of meeting protocol requirements.

The first aspect of the embodiment of the present application provides a PCIe switch management device, including: a first control module, a second control module and a global power management module, the first control module is connected to the first PCIe device through a first interface, and the second The two control modules are connected to the second PCIe device through the second interface, the link between the first control module and the first PCIe device is the first link, and the link between the second control module and the second PCIe device is the second link. Two links; the first control module is used to monitor the first link state of the first link; the global power management module is used to generate the first control signal according to the first link state; the second control module is used to generate the first control signal according to the first link state; The first control signal controls to update the second link state of the second link, and the updated second link state is the same as the first link state.

In combination with the first aspect, in the first possible implementation of the first aspect, when the first control module is an upstream port control module and the second control module is a downstream port control module, the first link state is L0s, and the control signal is usp_in_l0s; the second control module is specifically used to update the second link state to L0s according to usp_in_l0s when the first preset condition is met; wherein, the first preset condition includes: the upstream port has no TLP or DLLP waiting to send, and usp_in_l0s signal is high level.

In combination with the first aspect, in the second possible implementation of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L0s, and the control signal is all_dsp_in_rl0s; the second control module is specifically used to update the second link state to L0s according to all_dsp_in_rl0s when the second preset condition is met; wherein, the second preset condition includes: the downstream port has no TLP or DLLP waiting to send, and all_dsp_in_rl0s signal is high.

In combination with the first aspect, in the third possible implementation of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or low power consumption In the state of L1, the control signal is all_dsp_in_l1; the second control module is specifically used to update the second link to L1 according to the control signal all_dsp_in_l1 when the third preset condition is met; wherein, the third preset condition includes: the first After the receiving direction and sending direction of the two links are both in L0s for a preset time length, the first link state is in the state of L1 ASMP or the power consumption is lower than L1 ASMP, waiting for the TLP message being sent to be sent, and Generate a blocking signal to prevent sending a new TLP packet, so that the retransmission buffer on the second link is empty.

In combination with the first aspect, in the fourth possible implementation of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or low power consumption In the state of L1, the control signal is PM_ENTER_L1 DLLP; the second control module is specifically used to update the second link to L1 according to PM_ENTER_L1 DLLP when the fourth preset condition is met; wherein, the second preset condition includes: the first After the receiving direction and sending direction of the second link are both in L0s for a preset period of time, the first link is in the state of L1 ASMP or the power consumption is lower than L1ASMP, waiting for the TLP message being sent to be sent, and generating The blocking signal prevents the sending of new TLP packets, so that the retransmission buffer on the sending link is empty.

With reference to the first aspect, in the fifth possible implementation manner of the first aspect, the first control module is also used to obtain the link control instruction sent by the first PCIe device; the global power management module is also used to control the The instruction generates a second control signal; the second control module is further configured to update the second link state according to the second control signal, and the updated second link state corresponds to the link control instruction.

With reference to the first aspect, in the sixth possible implementation of the first aspect, the first PCIe device is a root component device, and the second PCIe device is a PCIe terminal device; the link control instruction is used to instruct to update the second link status It is in L2 or L3 state; the first PCIe device is a PCIe terminal device, the second PCIe device is a root component device, and the link control instruction is used to instruct to update the second link state to L1 state.

With reference to the first aspect, in the seventh possible implementation manner of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the second control module is used to When the link state is L0s, set the second interface to the P0s state from the P0 state, and control the all_dsp_in_rl0 signal to be high level; when the first control module is the upstream port control module, and the second control module is the downstream port control module, The second control module is also used to set the second interface from the P0 state to the P0s state when the first link state is L0s, and control the usp_in_rl0 signal to be high; when the first link or the second link When updating to L1, the second control module is also used to set the first interface or the second interface from the P0 state to the P1 state, turn off the logic clock output by the first interface or the second interface, and control the aux_clk_sel signal to be pulled high.

The second aspect of the embodiment of the present application provides a PCIe switch management method, characterized in that the PCIe switch includes a first interface and a second interface, the first interface and the first PCIe device are connected through a first link, and the second interface Connecting with a second PCIe device through a second link, the method includes: monitoring a first link state of the first link; generating a first control signal according to the first link state; controlling and updating the second link according to the first control signal The second link state of the road, and the updated second link state is the same as the first link state.

A third aspect of the embodiments of the present application provides a PCIe switch, which is characterized in that it includes the PCIe switch management device according to the first aspect.

Compared with the prior art, the embodiments of the present application have the following beneficial effects:

A PCIe switch management device, method, and PCIe switch provided in this embodiment, through the PCIe switch management device provided in this embodiment, can realize the coordinated control of the PCIe switch link and power management, thereby realizing low power consumption of the PCIe switch conversion.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only for the present application For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.

Fig. 1 is a schematic diagram of an application scenario of a PCIe switch provided by an embodiment of the present application;

Fig. 2 is a kind of PCIe switch provided by the embodiment of the present application and the structural representation of its setting relation with PCIe switch management device;

Fig. 3 is a kind of low power consumption implementation block diagram of PCIe switch provided by the embodiment of the present application;

FIG. 4 is a schematic diagram of global power supply message processing implemented by a global power management module provided by an embodiment of the present application;

Fig. 5 is a schematic flow chart of the PCI-PM mechanism provided by an embodiment of the present application entering the L1 link state;

Fig. 6 is a schematic flow diagram of the ASMP mechanism provided by an embodiment of the present application entering the L1 link state;

FIG. 7 is a schematic flow diagram of the upstream port entering and exiting the L0s link state through the linkage of the clock control unit and its correspondingly connected physical layer interface provided by an embodiment of the present application;

FIG. 8 is a schematic flow diagram of the downstream port entering and exiting the L0s link state through the linkage of the clock control unit and its correspondingly connected physical layer interface provided by an embodiment of the present application;

FIG. 9 is a schematic flow diagram of entering and exiting the L1 link state through linkage between the clock control unit and the corresponding physical layer interface provided by an embodiment of the present application;

FIG. 10 is a flowchart of a method for managing a PCIe switch provided in an embodiment of the present application.

detailed description

In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

The technical solutions provided by the present application will be explained in detail below in conjunction with specific embodiments.

Some nouns or terms involved in the embodiments of the present application are explained below.

(1) Device power status

D0 state: power state for normal operation.

D1 state: light dormancy state.

D2 state: deep sleep state.

D3hot state: fully closed state, but the power supply of the device has not been cut off.

D3cold state: fully closed state, but the power supply of the device has not been cut off.

(2) Link power status

L0 state: The link state of normal operation.

L0s state: standby state.

L1 state: low power standby state.

L2/3ready state: the state of the power off stage.

L2 state: low power sleep state.

L3 state: power off state.

Among them, under different device power states, under the PCI-PM mechanism and the ASPM mechanism, the respective link states that can be entered are shown in Table 1 below:

Table 1

Device Power Status PCI-PM ASPM D0 L0 L0, L0s, L1 D1 L1 - D2 L1 - D3 L1, L2/3ready, L2, L3 -

(3) PHY interface: physical interface

(4) Signal type

PME_Turn_Off: A protocol-specified message name, which is a power management event that changes the link status of all PCIe devices to L2/L3.

RC: root complex (root complex) device.

PME_TO_Ack: A protocol-specified message name, which is a confirmation of PME_turn_off.

turn_off_rcv_ack: Internal signal indicating that the current downstream port has received a PME_TO_Ack message.

all_dsp_rcv_ack: Internal signal indicating that all downstream ports have received PME_TO_Ack messages.

(5) Link status

link_in_rl0s: The link is in the link state of L0s.

link_in_l1: The link is in L1 or deeper link state.

link_in_l23: The link is in the link state of L2/L3.

l1_exit: The link exits the link state of L1.

l23_exit: The link exits the link state of L2/L3.

The tx link is the sending link (transport), and the rx link is the receiving link (receive).

(6) Link status signal

all_dsp_in_rl0s: an internal signal indicating that the second receive links of all downstream ports are in the link state of L0s.

usp_in_l0s: internal signal, indicating that the first receiving link of the upstream port is in the link state of L0s.

PM_Enter_L1 DLLP: A protocol-specified message name, which is a power management event, which indicates that a downstream component requests to enter the link state of L1.

PM_Active_state_request_L1 DLLP: A protocol-specified message name, which indicates that the downstream component requests to enter the link state of L1 through ASPM.

all_dsp_in_l1 signal: Internal signal indicating that all downstream ports are in L1 or deeper link state.

PM_Enter_L23 DLLP: A protocol-specified message name, which is a power management event, which indicates that the downstream component requests to enter the link state of L2/3.

ready_entr_l23 signal: an internal signal indicating that all downstream ports are in the link state of L2/L3.

one_dsp_exit_l1: Internal signal indicating that one or more downstream ports exit the link state of L1.

req_exit_l1: an internal signal, used to notify the downstream port to start exiting the link state of L1.

one_dsp_exit_l23: internal signal, used to inform the upstream port that one or more downstream ports exit the link state of L23.

all_dsp_in_rl0s: internal signal, indicating that all downstream ports receive links are in the link state of L0s.

usp_in_l0s signal: an internal signal, indicating that the upstream link is in the link state of L0s.

PMCSR: A power management register that represents the PCIe protocol register.

PM_ENTER_L1 DLLP message: A protocol-specified message name used to represent a request signal to enter the L1 link state through the PM-PCI mechanism.

PM_Request_ack DLLP message: A protocol-specified message name used to indicate receipt of a PM_ENTER_L1DLLP message.

PM_active_state_request_L1 message: A protocol-specified message name used to indicate a request signal to enter the L1 link state through the ASMP mechanism.

PM_active_state_request_L1 message: A protocol-specified message name used to indicate receipt of the PM_active_state_request_L1 message.

TLP: Transport Layer Packet.

DLLP: Data Link Layer Packet.

Fig. 1 is a schematic diagram of an application scenario of a PCIe switch provided by an embodiment of the present application, as shown in Fig. ) connection. The PCIe switch is used to implement data transmission between the root component device and each PCIe terminal device, or between each PCIe terminal device.

The PCIe switch provided in this embodiment includes a PCIe switch management device, as shown in FIG. 2 , the shaded part is the module unit of the PCIe switch management device provided in this embodiment. The PCIe switch provided in this embodiment includes: a first physical layer interface (referred to as the first interface), a port controller of the upstream port, a port controller of the downstream port, and a packet switching module arranged between the upstream and downstream port controllers And a second physical layer interface (abbreviated as the second interface) and a PCIe switch management device. Wherein, according to the PCIe protocol, in the PCIe switch, the number of port controllers for the upstream port is 1, and the number of port controllers for the downstream ports is n (n is any value from 1 to 32). The root component device is connected to the PCIe switch through the first physical layer interface, and the PCIe terminal device is connected to the PCIe switch through the second physical layer interface.

In combination with the structure of the PCIe switch provided in this embodiment, the PCIe switch management device provided in this embodiment is explained. Referring to FIG. 2 , the PCIe switch management device provided in this embodiment includes: an upstream port control module, a downstream port control module, and a global power management module. The upstream port control module is set in the port controller of the upstream port of the PCIe switch, and the upstream port control module performs corresponding operations by means of the protocol logic of the port controller of the upstream port. Similarly, the downstream port control module is set in the port controller of the downstream port of the PCIe switch, and the downstream port control module performs corresponding operations by means of the protocol logic of the port controller of the downstream port. The global power management module is embedded in the PCIe switch, exists side by side with the packet switching processing module in the PCIe switch, and is connected to the upstream port control module and the downstream port control module respectively. It should be noted that, according to the setting conditions of the number of port controllers of the upstream and downstream port attributes in the PCIe switch structure, in the PCIe switch management device provided in this embodiment, the number of upstream port control modules is 1, and the number of downstream port control modules is n, wherein, n is any value from 1 to 32.

In the PCIe switch provided by this embodiment, the global power management module and the packet switching processing module exist side by side. Therefore, the global power management module works independently from the switching logic of the packet switching module when the cooperative work is completed, so it does not occupy bandwidth or Affect the normal communication of data packets.

Fig. 3 is a block diagram of realizing low power consumption of a PCIe switch provided by an embodiment of the present application. Wherein, the solid-line frame part in FIG. 3 is a structural block diagram of a PCIe switch management device provided by an embodiment of the present application. Referring to FIG. 3 , the upstream port control module in the PCIe switch management device can be connected to the root component device through the first physical layer interface based on a differential link, and the differential link includes a sending path and a receiving path. The downstream port control module may be connected to the PCIe terminal device through a second physical layer interface based on a differential link, where the differential link includes a sending path and a receiving path.

The PCIe switch management device and the PCIe switch management method provided in this embodiment are explained in detail below by taking the PCIe switch management device with one upstream port control module and one downstream port control module as an example.

The upstream port control module includes a message processing unit of the upstream port attribute, a link control unit and a clock control unit.

In the upstream port, the message processing unit is used to send and receive power management related messages stipulated in the PCIe protocol, and is also used to receive instructions from the global power management module and the link control unit, send a specified power message to the sending link, and Feedback the received power message to the link control unit and the global power management module.

The link control unit is used to control the link state and power state of the PCIe device according to the information of the message processing unit and the global power management module, and control the message processing unit to send power management messages and control the closing and opening of the clock.

The clock control unit is configured to receive instructions from the link control unit, turn off and turn on the clock according to the PIPE interface protocol, and control the power state of the physical layer interface (PHY).

The downstream port control module includes a message processing unit of downstream port attributes, a link control unit and a clock control unit.

In the downstream port, the message processing unit is used to send and receive power management related messages stipulated in the PCIe protocol, and is also used to receive instructions from the global power management module and the link control unit, send a specified power message to the sending link, and Feedback the received power message to the link control unit and the global power management module.

The link control unit is used to control the link state and power state of the PCIe device according to the information of the message processing unit and the global power management module, and control the message processing unit to send power management messages and control the closing and opening of the clock.

The clock control unit is configured to receive instructions from the link control unit, turn off and turn on the clock according to the PIPE interface protocol, and control the power state of the physical layer interface (PHY).

The global power management module is used for: (1) processing of global power messages; (2) cooperative management of link states.

The functions performed by the global power management module will be explained in detail below through the above two aspects respectively.

(1) Processing of global power supply messages

The global power management module receives the link state information sent by the message processing unit. The link state information is a link control instruction for instructing to modify the link state of all PCIe devices to a corresponding low power consumption state, and then according to the The link state information control message processing unit generates a control signal, which is used to modify the link state of all PCIe devices to the power consumption state corresponding to the link state information.

Specifically, the following steps are included: Referring to Fig. 4, the message processing unit of the upstream port, after receiving the first PME_Turn_Off message sent by the root component device through the sending path, the message is used to indicate all PCIe terminal devices connected to the downstream port The link state of the link is changed to L2 or L3 state, and the turn_off (indicating that the upstream port control module receives the first PME_Turn_Off message) request is submitted to the global power management module; the global power management module then controls the message processing module of all active downstream ports to generate And send the second PME_Turn_Off message to the PCIe device connected thereto (for example, PCIe device 1 and PCIe device 2 in FIG. 5 , etc.). After the message processing module of the downstream port sends the second PME_turn_off message, it waits for the PME_TO_Ack message (after receiving the corresponding second PME_Turn_Off message, the PCIe devices on all active downstream ports will send the PME_TO_Ack message to the respective message processing modules, indicating that they have received the PME_TO_Ack message. The second PME_Turn_Off message) confirms that if the PME_TO_Ack message is received, the downstream port message processing module sets turn_off_rcv_ack (indicating that the current downstream port receives the PME_TO_Ack message) signal to notify the global power management module. The global power management module waits for all active downstream port message processing modules to set the turn_off_rcv_ack signal (that is, to indicate that the link status of all PCIe devices connected to the downstream port is changed to L2 or L3), then set all_dsp_rcv_ack (to indicate that all downstream ports received PME_TO_Ack message) signal to the upstream port message processing module, the module generates a PME_TO_Ack message and sends it to the root component device.

(2) Collaborative management of link state

The global power management module receives the link status information of each port through the link control unit. The link status information is used to indicate the link status of each upstream and downstream port, and then generates a corresponding control signal according to the link status information, and then According to the control signal, the link states corresponding to the upstream and downstream ports are coordinated and managed.

The link control unit is configured to monitor the link status of the corresponding receiving link and the sending link. For example, the link control unit monitors the link status of the receiving link and the sending link between the PCIe terminal device and the PCIe switch. The link control unit is further configured to send the monitored link statuses of the corresponding receiving link and the sending link to the global power management module.

Among them, the link control unit uses internal signals link_in_rl0s (indicating that the link is in L0s), link_in_l1 (indicating that the link is in L1 or deeper link state), link_in_l23 (indicating that the link is in L2/L3), l1_exit (indicating that the link is in L2/L3), l1_exit (indicating The link exits L1), and l23_exit (indicating that the link exits L2/L3) feeds back the link status of the corresponding port. The following uses specific examples for explanation.

1. link_in_rL0s

Referring to FIG. 3 , if the receiving link status of the downstream port is L0s, the link control unit of the downstream port sets link_in_r10s to report to the global power management module. When the global power management module detects that the receiving link direction of all downstream ports enters the L0s link state, it sets all_dsp_in_rl0s (representing that the receiving links of all downstream ports are in the L0s state) signal to the link control unit of the upstream port, and the upstream port The link control unit controls the sending link direction and starts to execute the entry process of L0s.

After the receiving link direction of the upstream port enters L0s, the link control unit of the upstream port sets link_in_rl0s (representing that the receiving link is in the L0s state) to report to the global power management module. After the global power management module receives the link_in_rl0s signal, it sets Bit usp_in_l0s (indicating that the receive link is in L0s state) signals to the Link Control Units of all downstream ports. The link control unit of the downstream port controls all sending link directions of the downstream port and starts to execute the entry process of L0s.

2. link_in_L1

It should be noted that, according to the PCIe protocol, the request to enter the L1 link state can only be initiated by the downstream components of the PCIe switch. In this embodiment, the upstream and downstream components are divided by differential lines. For example, see FIG. 3 As shown, if the downstream component in the figure is the upstream port of the PCIe switch, the upstream component in the figure is the PCIe device connected to the upstream port of the PCIe switch, such as the root component RC. If the upstream component in the figure is a downstream port of the PCIe switch, the downstream component in the figure is a PCIe device connected to the downstream port of the PCIe switch, such as an endpoint device. That is to say, the request to enter the L1 link state can only be initiated by an upstream port or a PCIe device connected to a downstream port.

The PCIe protocol stipulates that when entering the L1 link state through the control of the upper layer software, the link state information of the signal PM_Enter_L1DLLP (indicating that the downstream component requests to enter the link L1 state through the control of the upper layer software) signal is used. For the specific process, refer to the global The power management module implements the process of global power message processing.

The hardware method automatically enters the L1 state using the PM_Active_state_request_L1 DLLP (indicating that the downstream component requests to enter the L1 link state through ASPM) signal. One of the conditions for entering ASPM L1 is that all downstream port links are in L1 (or deeper) chains. link status, or the link is down. Therefore, if the link state of the downstream port is L1 or lower, the link control unit of the downstream port sets link_in_l1 (indicating that the link state of the downstream port is L1 or deeper) to report to the global power management module. When the global power management module detects that the link status of all downstream ports is L1 link status, it sets the all_dsp_in_l1 signal (indicating that the link status of all downstream ports is in L1 or deeper link status) to the upstream port A link control unit, the link control unit of the upstream port controls the link of the upstream port to start executing the L1 entry process.

3. link_in_L23

The PCIe protocol stipulates that one of the link state conditions for the upstream port link to enter the L23 Ready link state is that all the downstream port links enter the L23 Ready link state. The upstream port sends PM_Enter_L23 DLLP (indicating that the downstream component requests to enter the link state of L23), and then the link of the upstream port enters the link state of L23 Ready. Therefore, if the link state of the downstream port is L23ready, the link control unit of the downstream port sets link_in_123 (indicating that all downstream port links are in the link state of L2/L3) to report to the global power management module. When the global power management module detects that all downstream port links are in the link state of L23Ready, it sets the ready_entr_l23 signal (indicating that all downstream port links are in the link state of L23) to the link control unit of the upstream port, and the upstream The link control unit of the port controls the link direction of the upstream port and starts to execute the L23 entry process.

4. L1_exit

If the downstream port link exits from the link state of L1, the link control unit of the downstream port sets L1_exit (indicating that the downstream port link exits from the link state of L1), and the global power management module perceives that all downstream ports have When any one or more downstream port links exit the link state of L1, set one_dsp_exit_l1 (indicating that one or more downstream port links exit the link state of L1) to notify the link control unit of the upstream port, and the upstream port The link control module unit controls the upstream port link to start entering the exit process of L1.

If the upstream port link exits from the link state of L1, the link control unit of the upstream port sets L1_exit (indicating that the port link state exits L1), and the global power management module perceives that the upstream port link exits the link state of L1 , will set req_exit_l1 (used to notify the downstream port that the link starts to exit the link state of L1) to notify the link control unit of the downstream port, and the link control unit of the downstream port controls the link of the downstream port to start to enter the L1 Exit process.

5. Withdrawal of L23

If the link state of the downstream port exits from L23, the link control unit of the downstream port sets L23_exit, and when the global power management module senses that any one or more downstream ports of all downstream ports exit the L23 link state, it sets one_dsp_exit_l23 (Used to inform the upstream port that one or more downstream ports exit the L23 link state) notify the link control unit of the upstream port, and the link control unit of the upstream port controls the link of the upstream port to start entering the L23 exit process.

The link control unit is configured to synchronize link states with link control units of other ports through the global power management module, and control respective corresponding ports to enter respective link states. The following describes specific operations performed by the link control unit when specifically controlling the corresponding upstream and downstream ports to enter different link states.

1. L0s enters

For the link control unit of the upstream port, if there is no TLP (transport layer message) or DLLP (data link layer message) waiting to be sent on this port, and all_dsp_in_rl0s (representing that the receiving links of all downstream ports are in the link of L0s State) signal is high, then satisfy the condition that the sending link of upstream port enters the L0s state; For the link control unit of downstream port, if this port does not have TLP or DLLP to wait to send, and usp_in_l0s signal (representing the sending link of upstream port Link state in L0s) is high, then TLP or DLLP is waiting to send. When the link control unit detects that the link corresponding to the upstream and downstream ports satisfies the condition of entering L0s for a first preset time length, it controls the corresponding link to enter the link state of L0s. The link control unit controls the transmitter corresponding to the physical layer interface to send an electrical idle sequence, and sets the transmitter to the Hi-Z state to reduce the power consumption of the transmitter, thereby reducing the power consumption of the PCIe switch.

2. L0s exit

When the link control unit detects that the corresponding port no longer meets the conditions for entering L0s, the transmitter controlling the physical layer interface exits the Hi-Z state, and sends N FTS ordered sets to notify the peer device to exit L0s.

3. L1 enters

There are two ways to enter the L1 link state, one is the PM-PCI mechanism, and the other is the ASPM mechanism.

The way the PCI-PM mechanism enters the L1 link state is shown in Figure 5. If the downstream component in Figure 5 is the upstream port of the PCIe switch, the upstream component in Figure 5 is the PCIe device connected to the upstream port of the switch. as the root complex. If the upstream component in FIG. 5 is a downstream port of the PCIe switch, then the downstream component in FIG. 5 is a PCIe device connected to the downstream port of the switch, such as an endpoint device.

After the link control unit of the downstream component detects that PMCSR (a power management register, representing the PCIe protocol register) is configured to enter the link state of L1, it waits for the TLP message being sent to be sent and generates a blocking signal resistance value Send a new TLP message, and then wait for the retransmission buffer (retrybuf) on the sending link to be empty. After the preset condition is met, the link control unit of the downstream component controls the message processing unit to start periodically sending PM_ENTER_L1 DLLP messages to the peer PCIe device. The message processing unit of the upstream component notifies the link control unit after receiving PM_ENTER_L1, and then starts to prepare for L1, that is, waits for the TLP message being sent to be sent, and generates a blocking signal resistance value to send a new TLP message, and then Waiting for the retransmission buffer (retrybuf) on the send path to be empty. After the preset condition is met, the link control unit of the upstream component controls the message processing unit to periodically send PM_Request_ack DLLP messages (a protocol-specified message name used to indicate receipt of PM_ENTER_L1 DLLP) to the peer PCIe device, and at the same time The link control unit of the upstream component controls the transmitter of the physical layer interface to send the electrical idle sequence, and sets the transmitter to the Hi-Z state. After the downstream component receives the PM_Request_ack DLLP, the link control unit controls the transmitter of the physical layer interface to send an electrical idle sequence, and sets the transmitter to the Hi-Z state to reduce the power consumption of the transmitter.

It should be noted that the difference between the entry of ASMP L1 and the entry of PM-PCI L1 is mainly in the following two points. First, the entry of an upstream port into ASPM L1 requires that all downstream ports be in L1 ASPM or lower state, that is, the link control of the upstream port The unit needs to detect whether the all_dsp_in_l1 signal is high; second: the incoming L1 request message sent is PM_active_state_request_L1.

The way the ASMP mechanism enters the L1 link state is shown in Figure 6. Similarly, if the downstream component in 6 is the upstream port of the PCIe switch, then the upstream component in Figure 6 is the root component device connected to the upstream port of the switch . If the upstream component in FIG. 6 is a downstream port of the PCIe switch, then the downstream component in FIG. 6 is a PCIe terminal device connected to the downstream port of the switch.

After the link control unit of the downstream component detects that both the sending link direction and the receiving link direction are in L0s for a second preset length of time, the link status of all downstream ports is in the L1 ASMP or lower state, waiting for sending The TLP message sent is completed, and a blocking signal resistance value is generated to send a new TLP message, and then waits for the retransmission buffer (retrybuf) on the sending link to be empty. After the preset condition is satisfied, the link control unit of the downstream component controls the message processing unit to start periodically sending PM_active_state_request_L1 messages to the peer PCIe device. After receiving PM_active_state_request_L1, the message processing unit of the upstream component waits for the TLP message being sent to be sent, and generates a blocking signal to send a new TLP message, and then waits for the retransmission buffer (retrybuf) on the sending link to be empty . After the conditions are satisfied, the link control unit of the upstream component controls the message processing unit to start sending PM_Request_ack DLLP messages (a protocol-specified message name to indicate receipt of PM_active_state_request_L1) periodically to the peer PCIe device, and the upstream component’s The link control unit controls the transmitter of the physical layer interface to send the electrical idle sequence, and sets the transmitter to the Hi-Z state. After the downstream component receives the PM_Request_ack DLLP, the link control unit controls the transmitter of the physical layer interface to send an electrical idle sequence, and sets the transmitter to the Hi-Z state to reduce the power consumption of the transmitter.

4. L1 exit

When the link control unit detects that the port no longer satisfies the L1 condition (PM-PCI control or ASPM automatic detection), control the physical layer interface transmitter to exit the Hi-Z state, and send N FTS training ordered sets to exit to L0.

The clock control unit is used to implement the exit and entry of each state of the upstream and downstream port ASPM through linkage with the correspondingly connected physical layer interface (phy).

1. Upstream ports enter and exit L0s

Referring to Fig. 7, when the receiving links of all downstream ports are in the link state of L0s (all_dsp_in_rl0=1), the clock control unit of the upstream port keeps the frequency of the clock signal (pclk) constant, and then sends the first physical The layer interface sends a Powerdown signal, which is used to make the first physical layer interface set from the P0 state to the P0s state, and wait for the control signal (phystatus) of the first physical layer interface (phy) after it is determined to be in the P0s state. Among them, Powerdown and phystatus are standard pipe interface signals. When the first physical layer interface confirms that it is in the P0s state, control the differential line in the transmission link direction to be in the Hi-Z state, and the transmitter of the first physical layer interface is in a low power consumption state.

Referring to shown in Figure 7, when the receive link of all downstream ports receives the signal (all_dsp_in_rl0=0) that exits the link state of L0s, the frequency of the clock control unit control clock signal (pclk) of the upstream port remains constant, then to The first physical layer interface sends a Powerdown signal, which is used to set the first physical layer interface from the P0s state to the P0 state, and waits for the control signal (phystatus) of the first physical layer interface (phy) after it is determined to be in the P0 state. When the first physical layer interface confirms that it is in the P0 state, control the differential line in the direction of the first transmission link to exit the Hi-Z state, and the transmitter of the first physical layer interface exits the low power consumption state.

2. The downstream port enters and exits L0s

Referring to Fig. 8, when the receiving link of the upstream port is in the link state of L0s (usp_in_rl0=1), the clock control unit of the downstream port controls the frequency of the clock signal (pclk) to remain unchanged, and then transmits to the second physical layer The interface sends a Powerdown signal, which is used to set the second physical layer interface from the P0 state to the P0s state, and waits for the control signal (phystatus) of the second physical layer interface (phy) after it is determined to be in the P0s state. Among them, Powerdown and phystatus are standard pipe interface signals. When the second physical layer interface confirms that it is in the P0 state, the differential line controlling the transmission link direction is in the Hi-Z state, and the transmitter of the second physical layer interface is in a low power consumption state.

Referring to shown in Figure 8, when the receive link of all downstream ports receives the signal (usp_in_rl0=0) that exits L0s link state, the frequency of clock control unit control clock signal (pclk) of downstream port remains unchanged, then to The second physical layer interface sends a Powerdown signal, which is used to make the second physical layer interface set the P0 state from the P0s state, and wait for the control signal (phystatus) of the second physical layer interface (phy) after it is determined to be in the P0 state. When the second physical layer interface confirms that it is in the P0 state, control the differential lines in the transmission link direction to exit the Hi-Z state, and the transmitter of the second physical layer interface exits the low power consumption state.

3. Enter and exit L1

In some embodiments, when the upstream and downstream ports of the PCIe switch enter and exit the L1 state, the link control unit reduces the power consumption of the PCIe switch in the following manner.

As shown in Figure 9, when the upstream and downstream ports meet the conditions for entering L1, the clock control unit sends a Powerdown signal to the corresponding physical layer interface, which is used to set the physical layer interface from the P0 state to the P1 state, and waits for the physical layer interface (phy ) the control signal (phystatus) after it is determined to be in the P1 state. Among them, Powerdown and phystatus are standard pipe interface signals. When the physical layer interface is confirmed to be in the P1 state, the logical clock (core_clk) output by the physical layer interface is turned off, and at the same time, the clock control unit pulls up the aux_clk_sel (internal signal, indicating the switching of the normal clock and the auxiliary clock) signal, and the clock control unit The driving clock (mux_aux_clk) of the internal necessary working circuit is switched from a high-frequency clock to a low-frequency auxiliary clock to achieve the purpose of reducing power consumption. In addition, in the P1 power state, the clock control unit controls the differential line in the direction of the transmission link of the physical layer interface to be in the Hi-Z state, and the transmitter of the physical layer interface is in a low power consumption state.

As shown in Figure 9, when the upstream and downstream ports receive a signal to exit the L1 link state, the clock control unit sends a Powerdown signal to the corresponding physical layer interface, which is used to set the physical layer interface from the P1 state to the P0 state, and wait for The control signal (phystatus) of the physical layer interface (phy) after it is determined to be in the P0 state. When the physical layer interface is confirmed to be in the P0 state, the logical clock (core_clk) output by the physical layer interface is turned on. At the same time, the clock control unit reduces the aux_clk_sel (internal signal, indicating the switching of the normal clock and the auxiliary clock) signal, and the internal clock control unit The driving clock (mux_aux_clk) of the necessary working circuit is switched from the low-frequency auxiliary clock to the high-frequency clock to achieve normal operation. In addition, in the P0 power state, the clock control unit controls the differential line in the direction of the transmission link of the physical layer interface to exit the Hi-Z state, and the transmitter of the physical layer interface exits the low power consumption state.

Fig. 10 is a flowchart of a PCIe switch management method provided by an embodiment of the present application, the method is applied to a PCIe switch, the PCIe switch includes a first interface and a second interface, and the first interface and the first PCIe device pass through the first link road connection, the second interface and the second PCIe device are connected through the second link, and the method includes:

S1001. Monitor the first link state of the first link.

S1002. Generate a first control signal according to the first link state.

S1003. Control and update the second link state of the second link according to the first control signal, where the updated second link state is the same as the first link state.

This embodiment also provides a PCIe switch, the PCIe switch is built with the PCIe switch management device described in this embodiment.

A PCIe switch management device and method and a PCIe switch provided in this embodiment, through the PCIe switch management device and method provided in this embodiment, can realize the coordinated control of the PCIe switch link and power management, thereby realizing low-cost PCIe switch The conversion of power consumption, and the implementation method is described in detail from the functional block diagram, timing control and other aspects.

It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and/or components, but does not exclude one or more other Presence or addition of features, wholes, steps, operations, elements, components and/or collections thereof.

Reference to "one embodiment" or "some embodiments" or the like in the specification of the present application means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrase "in one embodiment", "in some embodiments", etc. in various places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not All Examples", unless expressly stated otherwise. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions described in the examples, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application, and should be included in the Within the protection scope of this application.

Claims (10)

1. A PCIe switch management apparatus, comprising: the system comprises a first control module, a second control module and a global power management module, wherein the first control module is connected with first PCIe equipment through a first interface, the second control module is connected with second PCIe equipment through a second interface, a link between the first control module and the first PCIe equipment is a first link, and a link between the second control module and the second PCIe equipment is a second link;

the first control module is used for monitoring the first link state of the first link;

the global power management module is used for generating a first control signal according to the first link state;

the second control module is configured to control to update a second link state of the second link according to the first control signal, where the updated second link state is the same as the first link state.

2. The PCIe switch management apparatus of claim 1, wherein when the first control module is an upstream port control module and the second control module is a downstream port control module, the first link status is L0s, and the control signal is usp _ in _ L0s;

the second control module is specifically configured to update the second link state to L0s according to the usp _ in _ L0s when a first preset condition is met;

wherein the first preset condition comprises: the upstream port has no TLP or DLLP waiting to be sent, and the usp _ in _ l0s signal is high.

3. The PCIe switch management apparatus of claim 1, wherein when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L0s, and the control signal is all _ dsp _ in _ rl0s;

the second control module is specifically configured to update the second link state to L0s according to the all _ dsp _ in _ rl0s when a second preset condition is met;

wherein the second preset condition comprises: the downstream port has no TLP or DLLP waiting to be sent, and the all _ dsp _ in _ rl0s signal is high.

4. The PCIe switch management apparatus of claim 1, wherein when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is all _ dsp _ in _ L1;

the second control module is specifically configured to update the second link to L1 according to the control signal all _ dsp _ in _ L1 when a third preset condition is met;

wherein the third preset condition comprises: after the time that both the receiving direction and the sending direction of the second link are in L0s reaches the preset time length, the state of the first link is in an L1 ASMP state or a state with power consumption lower than that of the L1 ASMP, and the method waits for the sending of the TLP being sent to be completed, and generates a blocking signal to stop sending a new TLP, so that the retransmission buffer on the second link is empty.

5. The PCIe switch management apparatus of claim 1, wherein when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is PM _ ENTER _ L1DLLP;

the second control module is specifically configured to update the second link to L1 according to the PM _ ENTER _ L1DLLP when a fourth preset condition is met;

wherein the second preset condition comprises: after the time that the receiving direction and the sending direction of the second link are both in L0s reaches the preset time length, the state of the first link is in an L1 ASMP state or a state with power consumption lower than that of the L1 ASMP, and waits for the sending of the TLP being sent to be completed, and generates a blocking signal to prevent sending of a new TLP, so that the retransmission buffer on the sending link is empty.

6. The PCIe switch management apparatus of claim 1, wherein the PCIe switch management apparatus is configured to perform the following operations

The first control module is further configured to acquire a link control instruction sent by the first PCIe device;

the global power supply management module is also used for generating a second control signal according to the link control instruction;

the second control module is further configured to update the second link status according to the second control signal, where the updated second link status corresponds to the link control instruction.

7. The PCIe switch management device of claim 6,

the first PCIe device is root component equipment, and the second PCIe device is PCIe terminal equipment; the link control instruction is used for indicating to update the second link state to an L2 or L3 state;

the first PCIe device is a PCIe terminal device, the second PCIe device is a root component device, and the link control instruction is used for indicating that the second link state is updated to be the L1 state.

8. The PCIe switch management device of claim 1,

when the first control module is a downstream port control module and the second control module is an upstream port control module, the second control module is configured to set the second interface from the P0 state to the P0s state and control all _ dsp _ in _ rl0 signals to be at a high level when the first link state is L0s;

when the first control module is an upstream port control module and the second control module is a downstream port control module, the second control module is further configured to set the second interface from a P0 state to a P0s state and control a usp _ in _ rl0 signal to a high level when the first link state is L0s;

when the first link or the second link is updated to L1, the second control module is further configured to set the first interface or the second interface from a P0 state to a P1 state, turn off a logic clock output by the first interface or the second interface, and control to pull up the aux _ clk _ sel signal.

9. A PCIe switch management method, wherein the PCIe switch includes a first interface and a second interface, the first interface and a first PCIe device are connected by a first link, and the second interface and a second PCIe device are connected by a second link, the method comprising:

monitoring a first link status of the first link;

generating a first control signal according to the first link state;

and controlling to update the second link state of the second link according to the first control signal, wherein the updated second link state is the same as the first link state.

10. A PCIe switch comprising the PCIe switch management apparatus of any one of claims 1 to 8.

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