CN115360297A - MIM capacitor and manufacturing method thereof - Google Patents

Abstract

The present application provides a MIM capacitor and a manufacturing method thereof, the method comprising: providing a substrate, forming an interlayer dielectric layer on the substrate, forming a first copper conductive structure in the interlayer dielectric layer; On the electrical layer, an etching stop layer and an insulating layer are sequentially formed; a first patterned photoresist layer is formed, and a pattern window of the upper electrode of the MIM capacitor is formed in the insulating layer; the first patterned photoresist layer is removed to expose the etched Stop layer; form the second patterned photoresist layer, form the pattern window of the through hole of the second copper conductive structure in the insulating layer and the etching stop layer; remove the second patterned photoresist layer, in the MIM capacitance The pattern window of the upper electrode and the pattern window of the through hole of the second copper conductive structure are filled with copper metal. According to the present application, when defining the upper electrode and the through-hole pattern, the same mask is used to shorten the process cycle and reduce the manufacturing cost; the bottom corner of the formed MIM capacitor upper electrode is rounded to avoid edge effects.

Description

A kind of MIM capacitor and manufacturing method thereof

technical field

The present application relates to the field of semiconductor technology, in particular to a MIM capacitor and a manufacturing method thereof.

Background technique

With the development of VLSI, in order to create high-precision capacitors while ensuring high-level performance of devices, MIM capacitors with copper interconnect technology are the key means. MIM capacitors are usually a sandwich structure, including metal electrodes on the upper layer and metal electrodes on the lower layer, and a thin insulating layer is separated between the upper metal electrodes and the lower metal electrodes.

When manufacturing MIM capacitors, the process of making the upper and lower electrodes of MIM capacitors requires the use of one or two masks; after forming the metal electrodes of MIM capacitors, the process of making copper conductive structures to form the leads of the upper and lower electrodes of MIM capacitors requires the use of another mask. The stencils are used to define the patterns of the through holes and the trenches, and the patterns of the masks used each time are different, requiring corresponding photolithography and etching processes, which is not conducive to shortening the process cycle and reducing manufacturing costs.

At the same time, the process of making the upper electrode of the MIM capacitor is to etch the metal material layer after depositing the metal material layer. After the etching is completed, the bottom corner of the metal material layer is sharp, as shown in Figure 1, causing the charge to be concentrated and distributed on the capacitor electrode. The edge of the board leads to edge effects, which bring great difficulties to reliability, parasitic parameter extraction, and circuit design.

Contents of the invention

In view of the above-mentioned shortcoming of prior art, the present application provides a kind of manufacturing method of MIM electric capacity, comprising:

providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a first copper conductive structure in the interlayer dielectric layer;

sequentially forming an etch stop layer and an insulating layer on the interlayer dielectric layer;

Forming a first patterned photoresist layer on the insulating layer, and forming a pattern window of the upper electrode of the MIM capacitor in the insulating layer;

removing the first patterned photoresist layer to expose the etch stop layer;

forming a second patterned photoresist layer on the insulating layer, and forming a pattern window of a through hole of a second copper conductive structure in the insulating layer and the etching stop layer;

The second patterned photoresist layer is removed, and copper metal is filled in the pattern window of the upper electrode of the MIM capacitor and the pattern window of the through hole of the second copper conductive structure.

Preferably, forming the first patterned photoresist layer and the second patterned photoresist layer on the insulating layer is accomplished by exposing and developing different pattern parts of the same mask plate.

Preferably, the first copper conductive structure comprises a portion serving as the bottom electrode of the MIM capacitor.

Preferably, the thickness of the etching stop layer is determined according to the unit capacitance value of the MIM capacitor to be formed.

Preferably, forming the pattern window of the upper electrode of the MIM capacitor in the insulating layer includes: using the first patterned photoresist layer as a mask, forming the pattern window of the upper electrode of the MIM capacitor in the insulating layer by first etching .

Preferably, the first etching is dry etching.

Preferably, after the first etching is completed, most of the exposed insulating layer is removed.

Preferably, the first patterned photoresist layer is removed by second etching.

Preferably, the second etching is dry etching.

Preferably, after the removal of the first patterned photoresist layer is completed, the insulating layer below the pattern window of the upper electrode of the MIM capacitor is removed by the third etching, so that the bottom corner of the pattern window of the upper electrode of the MIM capacitor is arc-shaped shape.

Preferably, the third etching is wet etching.

Preferably, after the copper metal is filled, a grinding process is performed until the insulating layer is exposed.

Preferably, the grinding process adopts chemical mechanical grinding.

On the other hand, the present application also provides a MIM capacitor manufactured according to the above-mentioned manufacturing method of the MIM capacitor.

As mentioned above, the MIM capacitor provided by the present application and its manufacturing method have the following beneficial effects: when manufacturing the MIM capacitor, define the upper electrode of the MIM capacitor and the through hole of the copper conductive structure used to form the lead wire of the lower electrode of the MIM capacitor When patterning, the same mask is used, thereby shortening the process cycle and reducing manufacturing costs; the bottom corners of the upper electrode of the formed MIM capacitor are rounded to avoid edge effects.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, the accompanying drawings in the following description The drawings are some implementations of the present application, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 shows the sharp schematic diagram of the bottom corner shape of the upper electrode of the MIM capacitor manufactured by the prior art;

2-4 shows a schematic diagram of a cross-sectional structure of a device formed after each step of a manufacturing method of a MIM capacitor provided by the prior art is completed;

5-7 show a schematic diagram of a cross-sectional structure of a device formed after each step of another MIM capacitor manufacturing method provided by the prior art is completed;

Fig. 8 shows the flowchart of the manufacturing method of a kind of MIM electric capacity provided for the embodiment of the present application;

FIG. 9 shows a schematic diagram of a cross-sectional structure of a device formed after step 801 is completed in a method for manufacturing a MIM capacitor provided by an embodiment of the present application;

FIG. 10 shows a schematic diagram of a cross-sectional structure of a device formed after step 802 is completed in a method for manufacturing a MIM capacitor provided by an embodiment of the present application;

FIG. 11 shows a schematic diagram of a cross-sectional structure of a device formed after step 803 is completed in a method for manufacturing a MIM capacitor provided by an embodiment of the present application;

FIG. 12 shows a schematic diagram of a cross-sectional structure of a device formed after step 804 is completed in a method for manufacturing a MIM capacitor provided by an embodiment of the present application;

FIG. 13 shows a schematic diagram of a cross-sectional structure of a device formed after step 805 is completed in a method for manufacturing a MIM capacitor provided in an embodiment of the present application;

FIG. 14 shows a schematic diagram of a cross-sectional structure of a device formed after step 806 in a manufacturing method of a MIM capacitor provided by an embodiment of the present application.

Detailed ways

The implementation of the present application is described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The orientation or positional relationship indicated is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the application. limit. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, or it may be the internal communication of two components, which may be wireless connection or wired connection connect. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below may be combined as long as they do not constitute a conflict with each other.

Please refer to FIG. 2-FIG. 4, which show a schematic diagram of a cross-sectional structure of a device formed after each step of a manufacturing method of a MIM capacitor provided by the prior art.

As shown in FIG. 2 , a first low dielectric constant layer 100 is provided, and at least one first copper conductive structure 101 is fabricated in the first low dielectric constant layer 100 .

Next, a dielectric barrier layer 102, an interlayer insulating layer 103, a first metal material layer 104, a first dielectric layer 105, a second metal material layer 106, and a second dielectric layer 107 are sequentially deposited to cover the first low dielectric constant layer. layer 100 and a first copper conductive structure 101.

Optionally, the deposition is chemical vapor deposition, the material of the dielectric barrier layer 102 is silicon carbide (NDC), the material of the interlayer insulating layer 103 is silicon oxide, and the material of the first metal material layer 104 and the second metal material layer 106 The material is TaN, and the material of the first dielectric layer 105 and the second dielectric layer 107 is silicon nitride.

As shown in Figure 3, the MIM capacitor structure 10 is formed on the interlayer insulating layer 103 by photolithography and etching process, wherein, the first metal material layer 104 constitutes the lower electrode of the MIM capacitor structure 10, and the second metal material layer 106 constitutes The upper electrode of the MIM capacitor structure 10 , the first dielectric layer 105 constitutes an insulating layer between the upper and lower electrodes of the MIM capacitor structure 10 , and the second dielectric layer 107 constitutes a dielectric barrier layer of the MIM capacitor structure 10 .

The process of forming the MIM capacitor structure 10 needs to use two reticles with different patterns, and perform two photolithography and etching processes.

As shown in FIG. 4 , a second low dielectric constant layer 110 is formed, and at least one second copper conductive structure 111 is fabricated in the second low dielectric constant layer 110 .

The second copper conductive structure 111 forms a copper interconnection structure with the upper and lower electrodes of the first copper conductive structure 101 and the MIM capacitor structure 10 respectively.

Forming the second copper conductive structure 111 needs to use another mask, and perform two photolithography and etching processes.

Please refer to FIG. 5-FIG. 7 , which show a schematic diagram of a cross-sectional structure of a device formed after each step of another MIM capacitor manufacturing method provided by the prior art.

As shown in FIG. 5 , a first low dielectric constant layer 200 is provided, and at least one first copper conductive structure 201 is fabricated in the first low dielectric constant layer 200 .

Next, a dielectric barrier layer 202 , an interlayer insulating layer 203 , a metal material layer 204 and a dielectric layer 205 are sequentially deposited to cover the first low dielectric constant layer 200 and the first copper conductive structure 201 .

Optionally, the deposition is chemical vapor deposition, the material of the dielectric barrier layer 202 is silicon carbide, the material of the interlayer insulating layer 203 is silicon oxide, the material of the metal material layer 204 is TaN, and the material of the dielectric layer 205 is nitrogen Silicon.

As shown in Figure 6, the MIM capacitor structure 20 is formed on the interlayer insulating layer 203 by photolithography and etching process, wherein, the metal material layer 204 constitutes the upper electrode of the MIM capacitor structure 20, and the first copper conductive structure located in the middle part 201 forms the lower electrode of the MIM capacitor structure 20 , the interlayer insulating layer 203 forms the insulating layer between the upper and lower electrodes of the MIM capacitor structure 20 , and the dielectric layer 205 forms the dielectric barrier layer of the MIM capacitor structure 20 .

The process of forming the upper electrode of the MIM capacitor structure 20 needs to use a mask to implement a photolithography and etching process.

As shown in FIG. 7 , a second low dielectric constant layer 210 is formed, and at least one second copper conductive structure 211 is formed in the second low dielectric constant layer 210 .

The second copper conductive structure 211 forms a copper interconnection structure with the upper and lower electrodes of the first copper conductive structure 201 and the MIM capacitor structure 20 respectively.

Forming the second copper conductive structure 211 needs to use another mask, and perform two photolithography and etching processes.

In summary, when using the prior art to manufacture the MIM capacitor structure, the upper electrode of the MIM capacitor and the copper conductive structure used to form the lead wires of the upper and lower electrodes of the MIM capacitor are independently made, and three pieces with different patterns need to be used. For the mask plate, three photolithography and etching processes are implemented, which is not conducive to shortening the process cycle and reducing manufacturing costs.

Simultaneously, the actual shape of the bottom corner of the upper electrode of the MIM capacitance structure shown in Fig. 4 and Fig. 7 is sharp, as shown in Fig. 1, causes electric charge to concentrate and distribute on the capacitive plate edge, and then causes edge effect, and this edge effect gives Reliability, parasitic parameter extraction, and circuit design bring great difficulties.

In view of the above-mentioned shortcomings of the prior art, the present application provides a method for manufacturing an MIM capacitor.

Please refer to FIG. 8 , which shows a flow chart of a method for manufacturing a MIM capacitor provided in an embodiment of the present application. The method includes the following steps:

In step 801, a substrate is provided, an interlayer dielectric layer is formed on the substrate, and a first copper conductive structure is formed in the interlayer dielectric layer.

As shown in FIG. 9, a substrate is provided on which isolating features and device structures such as transistors are formed. For simplicity, it is not shown in the legend.

Optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.

A plurality of isolation features are formed in the substrate, and the isolation features can be composed of any insulating material such as silicon dioxide (SiO ₂ ), or a "high-k" dielectric with a high dielectric constant such as In other words, it can be higher than 3.9. In some cases, the isolation features may be composed of oxide species. Examples of materials suitable for use in the isolation component include silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), praseodymia (Pr ₂ O ₃ ), zirconia (ZrO ₂ ), erbium oxide (ErOx), and other currently known or later developed materials with similar properties.

In this embodiment, the present application forms isolation components through a shallow trench isolation process (STI, Shallow Trench Isolation). The shallow trench isolation process includes but not limited to shallow trench etching, oxide filling and oxide planarization.

The shallow trench etching includes but not limited to isolating an oxide layer, nitride precipitation, performing shallow trench isolation using a mask, and performing STI shallow trench etching. The STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (Chemical Vapor Deposition) oxide filling or PVD (Physical Vapor Deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by various methods. The planarization of the silicon wafer can be achieved by filling the gap with SOG (spin-on-glass). SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked, the solvent is evaporated, and the silicon dioxide Left in the gap, the entire surface can also be etched back to reduce the thickness of the entire silicon wafer. Planarization can also be effectively performed by a CMP process (also known as a chemical mechanical polishing process), including but not limited to trench oxide polishing (chemical mechanical polishing may be used) and nitride removal.

Next, an interlayer dielectric layer 300 is formed on the substrate, and a first copper conductive structure 301 is formed in the interlayer dielectric layer 300 .

Optionally, the interlayer dielectric layer 300 is formed by a chemical vapor deposition process. The interlayer dielectric layer 300 may be, but not limited to, various dielectric layers such as silicon dioxide, fluorinated silicate glass (Fluorinated SilicateGlass FSG) or carbon silicon oxyhydride.

In order to simplify the manufacturing process, the first copper conductive structure 301 includes a portion used as the bottom electrode of the MIM capacitor.

In step 802, an etch stop layer and an insulating layer are sequentially formed on the interlayer dielectric layer.

As shown in FIG. 10 , an etch stop layer 302 and an insulating layer 303 are sequentially formed on the interlayer dielectric layer 300 .

Optionally, the etching stop layer 302 and the insulating layer 303 are formed by using a chemical vapor deposition process. Optionally, the material of the etching stop layer 302 is silicon nitride, and the material of the insulating layer 303 is oxide, such as silicon dioxide.

The thickness of the etching stop layer 302 is determined according to the unit capacitance value of the MIM capacitor to be formed. The etch stop layer 302 can also prevent the copper metal in the first copper conductive structure 301 from diffusing into the insulating layer 303 .

In step 803, a first patterned photoresist layer is formed, and a pattern window of the upper electrode of the MIM capacitor is formed in the insulating layer.

As shown in FIG. 11 , a first patterned photoresist layer 304 is formed on the insulating layer 303 , and the first patterned photoresist layer 304 defines the position of the insulating layer 303 to be etched.

Next, using the first patterned photoresist layer 304 as a mask, the first etching is performed to form the pattern window 31 of the upper electrode of the MIM capacitor in the insulating layer 303 .

In this embodiment, the first etching is dry etching. After the first etching is completed, most of the exposed insulating layer 303 is removed.

In step 804, the first patterned photoresist layer is removed, exposing the etch stop layer.

As shown in FIG. 12 , a second etching is performed to remove the first patterned photoresist layer 304 . In this embodiment, the second etching is dry etching.

Next, a third etching is performed to remove the insulating layer 303 under the pattern window 31 to expose the etching stop layer 302 . In this embodiment, the third etching is wet etching.

After the third etching is completed, the corners at the bottom of the graphics window 31 are arc-shaped. After the pattern window 31 is subsequently filled with copper metal to form the upper electrode of the MIM capacitor, the corners at the bottom of the plate are rounded to avoid edge effects.

In step 805, a second patterned photoresist layer is formed, and patterned windows of through holes of the second copper conductive structure are formed in the insulating layer and the etch stop layer.

As shown in FIG. 13 , a second patterned photoresist layer 305 is formed on the insulating layer 303 , and the second patterned photoresist layer 305 defines the positions of the insulating layer 303 and the etch stop layer 302 that need to be etched.

Next, using the second patterned photoresist layer 305 as a mask, the insulating layer 303 and the etching stop layer 302 are sequentially etched to form the via holes of the second copper conductive structure in the insulating layer 303 and the etching stop layer 302. graphics window32. Optionally, the etching is dry etching.

In this embodiment, forming the first patterned photoresist layer 304 and the second patterned photoresist layer 305 on the insulating layer 303 is accomplished by exposing and developing different pattern parts of the same reticle.

In step 806, the second patterned photoresist layer is removed, and copper metal is filled in the pattern window of the upper electrode of the MIM capacitor and the pattern window of the through hole of the second copper conductive structure.

As shown in FIG. 14 , the second patterned photoresist layer 305 is removed, and copper metal 306 is filled in the pattern window 31 of the upper electrode of the MIM capacitor and the pattern window 32 of the through hole of the second copper conductive structure.

Optionally, the second patterned photoresist layer 305 is removed by an ashing process.

Optionally, a copper electroplating process is used to fill the pattern window 31 of the upper electrode of the MIM capacitor and the pattern window 32 of the through hole of the second copper conductive structure with copper metal 306 .

Optionally, after the copper metal 306 is filled, a grinding process is performed until the insulating layer 303 is exposed.

Optionally, the grinding process adopts a chemical mechanical grinding process.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present application, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

In summary, the application provides a MIM capacitor and its manufacturing method. When manufacturing the MIM capacitor, when defining the upper electrode of the MIM capacitor and the through-hole pattern of the copper conductive structure used to form the lead wire of the lower electrode of the MIM capacitor , use the same mask, thereby shortening the process cycle and reducing manufacturing costs; at the same time, the bottom corner of the upper electrode of the formed MIM capacitor is rounded to avoid edge effects. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial application value.

Next, a dielectric layer is formed on the insulating layer 303 . Through photolithography and etching processes, pattern windows of trenches of the second copper conductive structure are formed in the dielectric layer. Through the copper electroplating process, the pattern window of the groove of the second copper conductive structure is filled with metallic copper. Chemical mechanical polishing is performed to complete the fabrication of the second copper conductive structure, the second copper conductive structure includes the part used as the lead wire of the bottom electrode of the MIM capacitor.

Next, another interlayer dielectric layer is formed on the dielectric layer. A pattern window of the third copper conductive structure is formed in the interlayer dielectric layer through photolithography and etching processes. Metal copper is filled in the pattern window of the third copper conductive structure through a copper electroplating process. Perform chemical mechanical polishing to complete the fabrication of the third copper conductive structure, the third copper conductive structure includes a part used as the lead of the upper electrode of the MIM capacitor.

The above-mentioned embodiments are only illustrative to illustrate the principles and effects of the present application, but are not intended to limit the present application. Any person familiar with the technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present application.

Claims (14)

1. a kind of manufacturing method of MIM electric capacity, it is characterized in that, described manufacturing method comprises: providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a first copper conductive structure in the interlayer dielectric layer; sequentially forming an etching stop layer and an insulating layer on the interlayer dielectric layer; Forming a first patterned photoresist layer on the insulating layer, and forming a pattern window of the upper electrode of the MIM capacitor in the insulating layer; removing the first patterned photoresist layer to expose the etch stop layer; forming a second patterned photoresist layer on the insulating layer, and forming a pattern window of a through hole of a second copper conductive structure in the insulating layer and the etching stop layer; The second patterned photoresist layer is removed, and copper metal is filled in the pattern window of the upper electrode of the MIM capacitor and the pattern window of the through hole of the second copper conductive structure. 2. the manufacturing method of MIM capacitance according to claim 1 is characterized in that, forming the photoresist layer of described first patterning and the photoresist layer of described second patterning on described insulation layer is It is done by exposing and developing different pattern parts of the same mask. 3 . The manufacturing method of the MIM capacitor according to claim 1 , wherein the first copper conductive structure comprises a portion used as a bottom electrode of the MIM capacitor. 4 . 4. The manufacturing method of the MIM capacitor according to claim 1, wherein the thickness of the etching stop layer is determined according to the unit capacitance value of the MIM capacitor to be formed. 5. The manufacturing method of the MIM capacitor according to claim 1, characterized in that, forming the pattern window of the upper electrode of the MIM capacitor in the insulating layer comprises: using the first patterned photolithography The glue layer is a mask, and the pattern window of the upper electrode of the MIM capacitor is formed in the insulating layer through the first etching. 6 . The method for manufacturing an MIM capacitor according to claim 5 , wherein the first etching is dry etching. 7. The manufacturing method of the MIM capacitor according to claim 5 or 6, characterized in that, after the first etching is completed, most of the exposed insulating layer is removed. 8 . The method for manufacturing a MIM capacitor according to claim 1 , wherein the first patterned photoresist layer is removed by second etching. 9. The manufacturing method of the MIM capacitor according to claim 8, wherein the second etching is dry etching. 10. The manufacturing method of the MIM capacitor according to claim 1, after the removal of the first patterned photoresist layer is completed, the pattern window below the upper electrode of the MIM capacitor is removed by the third etching The insulating layer makes the bottom corner of the graphic window of the upper electrode of the MIM capacitor be arc-shaped. 11. The method for manufacturing a MIM capacitor according to claim 10, wherein the third etching is wet etching. 12 . The manufacturing method of the MIM capacitor according to claim 1 , wherein after the copper metal is filled, a grinding process is performed until the insulating layer is exposed. 13 . 13. The manufacturing method of the MIM capacitor according to claim 12, wherein the grinding process adopts chemical mechanical grinding. 14. A MIM capacitor manufactured according to the method for manufacturing an MIM capacitor according to any one of claims 1-13.

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