CN115359833A - A storage chip test key protection method, device and equipment - Google Patents

Abstract

The application provides a method, a device and equipment for protecting a test key of a memory chip, which specifically comprise the following steps: when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enabling field, wherein the target key enabling field comprises a port level signal for controlling the test control module to enable; the target key processing module loads a target key to a target key register of the power-down emptying data; the target key processing module controls the starting of the test control module according to the port level signal of the target key enabling field so that the test control module can receive and compare whether the user input key is consistent with the target key or not and judge whether the user input key is correct or not. According to the method, the device and the equipment for protecting the test key of the memory chip, the time sequence complexity is improved, the circuit complexity is improved, and other organizations or individuals are difficult to judge the target key and the target key enabling field through circuit analysis.

Description

A storage chip test key protection method, device and equipment

technical field

The present application relates to the technical field of chip key protection, in particular to a storage chip test key protection method, device and equipment.

Background technique

In the field of storage chips, different wafer production processes often bring about changes in the characteristics of the memory cell, so the control method or control accuracy of the peripheral circuit of the entire memory module also changes accordingly, including: the control of the analog module Selection of accuracy, selection of control method of digital modules, selection of data path, selection of circuit operating speed, and selection or configuration of other multiple parts. For example, the target clock of the generation circuit of the on-chip clock oscillator (Oscillator) is 50MHz. Considering process changes or deviations in the production process, designers usually choose multiple RC parameters for the oscillator. During the chip test, the tester will let the chip enter the test mode, find the configuration parameter closest to 50MHz, and then store this selection information in the boot memory module (Boot memory).

When a well-designed chip is sold well in the market, other organizations or individuals may open the chip, take pictures of the circuit and analyze it, and conduct actual circuit measurement and analysis in test mode. In this case, if the key to enter the chip test is relatively simple or the protection strength is low, other organizations or individuals can usually guess the key through the shmoo test, or deduce the key through logical analysis of the camera circuit. After obtaining the key, enter the chip test mode through the testing machine, obtain the configuration parameters of the chip, and conduct a large number of complex circuit measurement and analysis, and finally understand the design ideas and design points of the circuit.

Therefore, it is very important to protect the test key of the memory chip through circuit design, which can further protect the configuration parameters of the chip circuit after leaving the factory from being rewritten or researched and plagiarized.

Contents of the invention

In view of this, the embodiments of the present application provide a storage chip test key protection method, device and equipment, aiming at protecting the storage chip test key through circuit design.

On the one hand, the present application proposes a storage chip test key protection method, the method comprising:

When the chip is powered on again, the target key processing module obtains the prestored target key and the target key enable field, the target key is a key other than the initial key input for the initial test of the chip, and the target key The enable field includes a port level signal for controlling the enabling of the test control module;

The target key processing module loads the target key into the target key register of power-off clear data;

The target key processing module controls the activation of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares whether the user input key is consistent with the target key, and judges whether the user input key is correct.

Optionally, when the chip is powered on again, the target key processing module obtains the pre-stored target key and target key enable field, specifically including:

Write the target key and the target key enable field into the boot storage module;

The chip is powered on again, and the target key processing module obtains the target key and the target key enable field loaded by the boot logic module from the boot storage module.

Optionally, write the target key and the target key enable field into the boot storage module, including:

The target key and the target key enable field are written into the start storage module by programming instructions, and the write times of the target key and the target key enable field are written into the start storage module according to the programmable times of the start storage module Sure.

Optionally, the target key processing module loads the target key into the target key register of power-off clear data, further including:

The target key processing module performs data processing on the target key to form a processed target key;

Load the processed target key into the target key register for power-off clear data.

Optionally, perform data processing on the target key, including:

Negating the target key, and/or adding a fixed value to the target key.

Optionally, the chip is powered on again as the second stage, and there is also a first stage before the second stage, and the first stage includes:

When the chip is powered on for the first time, the test control module compares whether the initial key input by the user is consistent with the pre-saved initial key. If they are consistent, the test control module passes the test to enable the initial chip test;

After the initial test of the chip is completed, the target key and the target key enable field are written into the boot storage module using programming instructions to wait for the chip to be powered on again.

In the second aspect, the present application also proposes a storage chip test key protection device, including a target key processing module, a target key register and a test control module,

The target key processing module is used to obtain the pre-saved target key and the target key enable field when the chip is powered on again, and load the target key into the target key register of power-off clear data, the target key is a key other than the initial key input for the initial test of the chip, and the target key enabling field includes a port level signal for controlling the enabling of the test control module;

The target key processing module is also used to control the enablement of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares whether the user input key is consistent with the target key, and judges the user input key is it right or not;

The test control module is also provided with an input port for a user to input a key.

Optionally, the device also includes: a startup storage module and a startup logic module,

The startup storage module is used to store the target key and the target key enable field;

The startup logic module is electrically connected with the startup storage module and the target key processing module respectively, and is used for loading the target key and the target key enable field in the startup storage module to the target key processing module.

Optionally, the chip is powered on again as the second stage, and there is a first stage before the second stage. In the first stage, the device also includes: an initial key module,

The initial key module is used to save the initial key, so that the test control module compares whether the stored initial key is consistent with the user input initial key when the chip is powered on, and if consistent, the test control module enables the chip to be opened by testing The initial test, so that after the initial test of the chip is completed, the target key and the target key enable field are written into the boot storage module to wait for the chip to be powered on again.

In the third aspect, the present application also proposes a storage chip test key protection device, including a memory and a processor, the memory is used to store a computer program, and when the processor invokes the computer program, the above-mentioned storage Chip test key protection method.

Embodiments of the present application provide a storage chip test key protection method, device and equipment. In the technical solution of this application, compared with the prior art, the test control module no longer uses the fixed circuit form of directly obtaining the stored key and the key input by the user, and adds a target key processing module and a target key register. The data in the target key register disappears every time the chip is powered off, and the target key processing module needs to be powered on to obtain the pre-stored target key and enable the target key. The key is stored in the target key register where the power-down data is cleared, the target key processing module controls the test control module to enable according to the port level signal of the target key enable field, obtains the target key in the target key register, and the test control module In the enabled working state, it is possible to compare whether the key entered by the user is consistent with the target key stored in the target target key register, and then judge whether it is enough to open the chip test circuit. The complexity of the circuit increases, making it difficult for other organizations or individuals to pass through the circuit. The field of target key and target key enablement is obtained through analysis, so that the circuit can well protect the two key information of target key and target key enablement.

Description of drawings

In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is a flow chart of a storage chip test key protection method provided by an embodiment of the present application;

Fig. 2 is a flow chart of the method for starting the chip test circuit by the test control module when the chip provided by the embodiment of the present application is powered on for the first time;

FIG. 3 is a flowchart of a method for obtaining a pre-saved target key and target key enablement provided by an embodiment of the present application;

FIG. 4 is a scenario flow chart of a storage chip test key protection method provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a memory chip test key protection device provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of a storage chip test key protection device provided by an embodiment of the present application.

Detailed ways

In the existing memory chip test protection technology, the pre-stored initial key is obtained from the test initial key through the test control module, and the pre-stored initial key is compared with the key input by the user. The circuit is simple and the memory chip is damaged. The test protection is not safe. It is easy to get the test key through the shmoo test or through the logic analysis of the camera circuit, and the instructions in the test mode can also be obtained through the logic analysis of the camera circuit. Once the test key is deciphered, other institutions or individuals can do the test experiments required for circuit analysis at will, and the risk of excellent circuits being plagiarized is relatively high.

Compared with the prior art, the inventor considers no longer using the fixed circuit form in which the test control module directly obtains the stored key and compares it with the key input by the user, and adds a target key processing module and a target key register. The data in the target key register disappears every time the chip is powered off, and the target key processing module needs to be powered on to obtain the pre-stored target key and enable the target key. The key is stored in the target key register where the power-down data is cleared, the target key processing module controls the test control module to enable according to the port level signal of the target key enable field, obtains the target key in the target key register, and the test control module In the enabled working state, it is possible to compare whether the key entered by the user is consistent with the target key stored in the target target key register, and then judge whether it is enough to open the chip test circuit. The complexity of the circuit increases, making it difficult for other organizations or individuals to pass through the circuit. Analyze and obtain the target key and the target key enable field. Further, the target key processing module can also perform data processing on the target key and then save it in the target key register, so as to improve other institutions or individuals to infer The difficulty of the target key. Further, the target key and the target key enable are written into the boot memory module of the chip test circuit through programming instructions. Different chip batches can be set with different target keys to improve the accuracy of the target key. protection strength. If other organizations or individuals forcibly modify the contents of the target key register through methods such as focused ion beam (FIB, Focused Ion beam), but the bit width of the target key register is large, the modification is difficult, and even if the modification is successful, it is limited to one chip. It is far from reaching the number of chips required for the test circuit experiment.

In the embodiment of this application, the hardware device may include:

Initial key store for storing initial keys.

The target key register is used to temporarily store the target key when the chip is powered on.

A boot storage module used to store the target key and the target key enablement.

The chip testing circuit is used for testing the chip, and the boot storage module is set in the chip testing circuit.

The test control module is used to compare whether the key stored in the chip is consistent with the key input by the user. If they are consistent, the test control module controls the chip test circuit to start the chip test.

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Fig. 1 is a flow chart of a method for protecting a memory chip test key provided in an embodiment of the present application. Referring to Fig. 1, a method for protecting a memory chip test key includes:

S101. When the chip is powered on again, the target key processing module obtains the pre-stored target key and the target key enable field.

The target key is a key other than the initial key input for the initial test of the chip. The chip is powered on again as the second stage. Before the second stage, there is a first stage. The first stage is the initial power-on of the chip. At this time, the target key and the target key enable field have not been saved in the chip test circuit, and the opening of the chip test circuit needs to be controlled by the initial key. After the first stage is over, the target key is used when the chip is powered on again.

The target key enable field includes a port level signal for controlling the enable of the test control module.

S102. The target key processing module loads the target key into a target key register whose data is cleared after power-off.

The target key register adopts a target key register that clears data when power is off. When the chip is not powered on, the outside world cannot obtain the key from the target key register that is cleared from data. After the chip is powered on, the target key processing module can Perform data processing on the target key, load the target key after data processing into the target key, and increase the difficulty for other organizations or individuals to obtain the key through analytical circuit reasoning. Of course, the target key processing module may not key for data processing.

S103, the target key processing module controls the enablement of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares whether the user input key is consistent with the target key, and judges whether the user input key is correct.

When the chip is powered on, the target key processing module obtains the target key enable field, for example, the field is: FINAL_KEY_EN=1, then the target key processing module uses the target key to enable the field according to the port level indication of the target key enable field. The FINAL_KEY_EN high level can be turned on and the test control module is in the working state. Then, the control test control module can compare the key input by the user with the target key. However, if the chip is not powered on or the target key is not enabled correctly, it cannot be enabled. Test control module.

This application sets the target key processing module and the target key register. After the chip is powered off each time, the target key register data disappears, and the target key and target key enable fields are pre-stored in the memory of the chip test circuit through programming instructions. Every time the chip is powered on again, the target key processing module reacquires the target key and the target key enablement. Compared with the known technology, this application no longer only uses the fixed circuit in the first stage, but requires power, the target key and the target key enable field can be called, and then the test control module is turned on to enter the working state. Key comparison, timing and circuit complexity are all improved, making it more difficult for other organizations or individuals to deduce the final key and the final key enable field through circuit analysis and judgment.

In an embodiment of the present application, in step S101 described in FIG. 1 above, when the chip is powered on again, it is the second stage, and there is a first stage before the second stage, and the first stage is the initial power-on of the chip When the target key is not pre-stored and the target key is enabled, the implementation of starting the chip test circuit through the test control module will be described in detail below. It should be noted that the implementation manners given in the introduction below are only exemplary descriptions, and do not represent all implementation manners of the embodiments of the present application.

Fig. 2 is a flow chart of the method for starting the chip test circuit by the test control module when the chip provided by the embodiment of the present application is powered on for the first time, referring to Fig. 2, the first stage includes:

S201. The chip is powered on for the first time, and the test control module compares whether the initial key input by the user is consistent with the pre-stored initial key. If they are consistent, the test control module passes the test enable and starts the initial test of the chip.

The initial key is the initial key set by chip production, which is used when the chip is started for the first time before leaving the factory for chip testing. When the chip is tested for the first time, the initial key test uses a fixed circuit, and the test control module directly communicates to the user. Comparing the input initial key with the pre-stored initial key can quickly obtain the access to the chip test circuit and speed up the process of chip delivery.

S202 , the initial test of the chip is completed, and the target key and the target key enable field are written into the boot storage module by using a programming instruction, so as to wait for the chip to be powered on again.

After the initial test of the chip is completed and the test is passed, the chip can be arranged to leave the factory. In order to prevent other organizations or individuals from analyzing and cracking the circuit, the target key and the target key enable field are written into the startup storage module inside the chip test circuit instead of using the initial The fixed circuit of the key is used to judge the correctness of the key. The target key control module controls the test control module through the target key and the target key enable field, which increases the complexity of the circuit and improves the ability of other organizations or individuals to crack the password through circuit analysis and reasoning. key difficulty.

The initial key setting is to facilitate the chip to quickly start the chip before leaving the factory. At this time, the chip has not yet been shipped, and the chip is safe. You can directly compare the initial key entered by the user with the pre-saved initial key through the test control module. The use authority of the chip test circuit improves the efficiency of chip delivery; the target key and target key enable fields are used for use with the target key processing module after the chip leaves the factory, and the target key and target key can only be called when the chip is powered on. The key enablement increases the complexity of the circuit timing and the complexity of the circuit, and improves the security of the chip test circuit after the chip leaves the factory.

In another embodiment of the present application, the implementation manner of step S101 described above in FIG. 1 will be described in detail below. It should be noted that the implementation manners given in the introduction below are only exemplary descriptions, and do not represent all implementation manners of the embodiments of the present application.

FIG. 3 is a flow chart of a method for obtaining a pre-saved target key and target key enablement provided by an embodiment of the present application, further illustrating the target key processing module to obtain the target key and target key enablement again. See Figure 3. When the chip is powered on again, the pre-saved target key and target key enablement are obtained, including:

S301. Write the target key and the target key enable field into the boot storage module.

The starting storage module is a self-starting storage module in the chip test circuit, and the chip can be started to call stored data and parameters therefrom, and the target key and the target key enabling field are written into the starting storage module by programming instructions, The writing times of the target key and the target key enabling field into the boot storage module are determined according to the programmable times of the boot storage module.

S302. The chip is powered on again, and the target key processing module obtains the target key and the target key enable field loaded by the boot logic module from the boot storage module.

The startup logic can be arranged in the chip test circuit and connected with the startup storage module, and the startup logic can also be arranged in the target key processing module and connected with the startup storage module in the chip test circuit.

The chip is powered on again, and the boot storage module loads the target key and the target key enable field from the boot storage module to the target key processing module, changing the existing technology where the key is stored in a fixed location, and the test control module can be directly called Compared with the scheme, the final key and the final key enable field are stored in the boot storage area, which needs to be loaded through the boot logic, and the timing is complicated, which increases the time for competitors to judge the final key and the final key enable field through circuit analysis. difficulty.

Write the target key and the target key enable field into the start-up storage module of the chip test circuit through programming instructions. Different chip batches can set different target keys to improve the protection of the target key. When the start-up storage module When the number of programmable times is multiple, the target key in the chip can be changed later, and the target key is not unique, which improves the security of the chip test circuit.

A storage chip test key protection method provided by the embodiment of the present application has been introduced above, and the method for the storage chip test key will be exemplarily described below in combination with specific application scenarios.

Fig. 4 is a scenario flowchart of a storage chip test key protection method provided in an embodiment of the present application. Referring to Fig. 4, a storage chip test key protection method includes:

S401, the tester of the original chip design factory inputs the initial key through the test machine, and the test control module compares the input initial key with the pre-stored initial key, and if they are consistent, the test control module passes the test enable (TEST_EN=1 ) start the initial test of the chip, and the initial test of the chip includes the test function of the circuit under test, or the opening of the test path, or the recognition of the test instruction.

The circuit for testing the initial key is fixed and cannot be changed once produced.

S402. After the initial test of the chip is completed, the target key and the target key enable field can be written together into the boot storage module by using a programming instruction on the premise that the initial key is matched correctly.

The stored information will not be lost when the storage module is powered off.

The configuration parameters of the chip can be written into the boot storage module at the same time, and the subsequent chip is powered on again. Under the protection of the target key and the target key enablement, the configuration parameters of the chip can also reduce the tampering of the chip configuration parameters by other institutions or individuals and plagiarism.

S403. When the chip is powered on again, the boot logic (Boot logic) module is responsible for loading the target key of the boot storage module and the target key enable field into the target key processing module of the chip control circuit.

S404. The target key processing module (Final key process) is responsible for inverting the loaded target key and/or adding fixed values and other data processing to form a processed target key, and converting the processed target key Load to the target key register (Final key reg), or directly load the target key to the target key register (Final key reg) without data processing.

The target key register is responsible for saving the target key. Every time the power is turned off, the content of the target key register disappears, and it waits to be re-powered to load the value.

The target key processing module outputs target key enable FINAL_KEY_EN=1 to the test control module for controlling the enablement of the test control module (Test control).

S405 , when the target key is enabled, the tester inputs the target key through the test machine, and the test control module is responsible for comparing whether the input target key is consistent with the target key, and if they are consistent, the chip test is started.

When the chip is powered on for the first time, the test control module is used to compare the pre-saved initial key with the initial key input by the user, and judge whether to open the chip test circuit for testing.

When the chip is not powered on for the first time, the startup storage module is used to store the target key and the target key enablement, and the startup logic is used to start the target key and the target password stored in the storage module when the chip is powered on. The key can be loaded into the target key processing module, and the target key processing module is used to load the target key into the target key register, and the target key processing module is also enabled by the target key enabling control test control module , when the control test module is turned on, it is used to compare whether the final password input by the user is consistent with the password in the test key, and if they are consistent, the chip test circuit can be turned on and used.

This embodiment combined with implementation scenarios can be implemented.

The above provides some specific implementations of a memory chip test key protection method according to the embodiments of the present application. Based on this, the present application also provides corresponding devices and equipment.

The following will introduce the device provided by the embodiment of the present application from the perspective of functional modularization.

FIG. 5 is a schematic diagram of a memory chip test key protection device provided in an embodiment of the present application. A memory chip test key protection device 200 includes a target key processing module 210, a target key register 220 and a test control module. 230.

The target key processing module 210 is used to obtain the pre-saved target key and the target key enable field when the chip is powered on again, and load the target key to the target key register 220 that clears data after power-off. The key is a key other than the initial key input for the initial test of the chip, and the target key enabling field includes a port level signal for controlling the enabling of the test control module 230;

The target key processing module 210 is also used to control the enablement of the test control module 230 according to the port level signal of the target key enable field, so that the test control module 230 receives and compares whether the user input key is consistent with the target key, and judges whether the user input key is consistent with the target key. Whether the input key is correct;

The test control module 230 is also provided with an input port for the user to input a key.

FIG. 6 is a schematic diagram of a memory chip test key protection device provided in an embodiment of the present application. Referring to FIG. 6 , a memory chip test key protection device further includes: a startup storage module 240 and a startup logic module 250,

The startup storage module 240 is used to store the target key and the target key enable field (FINAL_KEY_EN=1).

The startup logic module 250 is electrically connected to the startup storage module and the target key processing module respectively, and is used to load the target key and the target key enable field in the startup storage module 240 to the target key processing module 210;

The target key processing module obtains the target key enabling field, and then the target key processing module indicates according to the port level of the target key enabling field, for example, the field is: FINAL_KEY_EN=1, and the FINAL_KEY_EN high level is enabled with the target key The test control module is turned on to be in working state, so that the test control module 230 receives and compares whether the key input by the user is consistent with the target key, and judges whether the key input by the user is correct.

Re-powering on the chip is the second stage, and there is a first stage before the second stage. In the first stage, the device also includes: an initial key module 260,

The initial key module 260 is used to save the initial key, so that the test control module compares whether the stored initial key is consistent with the user input initial key when the chip is powered on for the first time, and if consistent, the test control module 230 uses the Can (TEST_EN=1) enable the initial test of the chip, so that after the initial test of the chip is completed, the target key and the target key enable field are written into the boot storage module 240 for waiting for the chip to be powered on again.

The type of the boot storage module 240 includes any one of a one-time programmable device, a multiple-time programmable device and a flash memory.

The target key processing module 210, target key register 220 and test control module 230 are all set in the chip control circuit.

The boot storage module 240 is set in the chip test circuit, and the boot logic module 250 can be set in the chip test circuit, and can also be set in the target key processing module 210 .

The following will introduce the devices provided by the embodiments of the present application.

The present application also proposes a memory chip test key protection device, including a memory and a processor, the memory is used to store a computer program, and when the processor invokes the computer program, the above-mentioned memory chip test key protection method is implemented .

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without creative effort.

The above descriptions are only exemplary implementations of the present application, and are not intended to limit the protection scope of the present application.

Claims (10)

1. A method for protecting a test key of a memory chip is characterized by comprising the following steps:

when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enabling field, wherein the target key is a key except an initial key input by the chip in the initial test, and the target key enabling field comprises a port level signal used for controlling the test control module to enable;

the target key processing module loads a target key to a target key register of the power-down emptying data;

the target key processing module controls the starting of the test control module according to the port level signal of the target key enabling field so that the test control module can receive and compare whether the user input key is consistent with the target key or not and judge whether the user input key is correct or not.

2. The method of claim 1, wherein when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enable field, and specifically includes:

writing the target key and the target key enabling field into the starting storage module;

and the chip is powered on again, and the target key processing module obtains the target key and the target key enabling field loaded by the starting logic module from the starting storage module.

3. The method of claim 2, wherein writing the target key and the target key enable field to the boot storage module comprises:

and the target key enabling field are written into the starting storage module through a programming instruction, and the writing times of the target key and the target key enabling field written into the starting storage module are determined according to the programmable times of starting the storage module.

4. The method of claim 1, wherein the target key processing module loads the target key into a target key register of the power down flush data, further comprising:

the target key processing module performs data processing on the target key to form a processed target key;

and loading the processed target key to a target key register of the power-down emptying data.

5. The method of claim 4, wherein performing data processing on the target key comprises:

negating the target key, and/or fixing a fixed value to the target key.

6. The method of claim 1, wherein the chip is powered up again as a second phase, and a first phase is provided before the second phase, the first phase comprising:

the chip is electrified for the first time, the test control module compares whether an initial key input by a user is consistent with a pre-stored initial key or not, and if so, the test control module enables the chip to start the first test through the test;

and after the initial test of the chip is finished, writing the target key and the target key enabling field into the starting storage module by using a programming instruction, and waiting for the chip to be electrified again.

7. A memory chip test key protection device is characterized by comprising a target key processing module, a target key register and a test control module,

the target key processing module is used for obtaining a target key and a target key enabling field which are stored in advance when the chip is electrified again, and loading the target key to a target key register of power-down emptying data, wherein the target key is a key except an initial key input by the chip in the initial test, and the target key enabling field comprises a port level signal used for controlling the test control module to enable;

the target key processing module is also used for controlling the starting of the test control module according to the port level signal of the target key enabling field so as to facilitate the test control module to receive and compare whether the user input key is consistent with the target key or not and judge whether the user input key is correct or not;

the test control module is also provided with an input port for a user to input a key.

8. The apparatus of claim 7, further comprising: a start-up storage module and a start-up logic module,

the starting storage module is used for storing a target key and a target key enabling field;

the starting logic module is respectively electrically connected with the starting storage module and the target key processing module and is used for loading the target key and the target key enabling field in the starting storage module to the target key processing module.

9. The apparatus of claim 7, wherein the power-up of the chip is a second phase, and a first phase is provided before the second phase, and the apparatus further comprises: the initial key module is used to generate a key,

the initial key module is used for storing an initial key so that the test control module compares whether the stored initial key is consistent with the initial key input by a user when the chip is electrified for the first time, if so, the test control module enables the chip to test for the first time through the test enable, so that after the chip is tested for the first time, a target key and a target key enable field are written into the starting storage module to wait for the chip to be electrified again.

10. A memory chip test key protection device, comprising a memory for storing a computer program and a processor for implementing a memory chip test key protection method according to claims 1 to 6 when the processor calls the computer program.

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