CN115347757A - Power Control System - Google Patents

Abstract

A power control system is suitable for a direct current power supply, a power supply supporting ATX standard and a load unit. The power control system receives the output power of one of the power supply and the direct current power supply as an input voltage, and comprises a first switch to a seventh switch, a first direct current transformer and a second direct current transformer, and outputs various output voltages to the load unit under different states supporting Advanced Configuration and Power Interface (ACPI) by controlling a plurality of enabling ends and a plurality of disabling ends of the first switch to the seventh switch, the first direct current transformer and the second direct current transformer.

Description

power control system

technical field

The present invention relates to a power control system, in particular to a power control system compatible with ATX standard power supply or direct current as input power.

Background technique

Most of the current motherboards that support the X86 standard use a power supply that supports the ATX standard as the input power. However, in an embedded system (Embedded system), its embedded motherboard (Embedded motherboard) usually also uses a DC power supply such as 12V or 24V as the input power supply for the convenience of power supply selection, also known as DC-IN power supply. Way. Therefore, in the product development stage, product planners often have to develop different types of products for the same hardware architecture for customers to choose. As a result, human resources and product development costs increase. In view of the aforementioned phenomena, whether there are other more flexible power control systems has become a problem to be solved.

Contents of the invention

Therefore, the object of the present invention is to provide a hardware device and a power control system compatible with ATX standard power supply or direct current as input power.

Therefore, the present invention provides a power control system, which is suitable for a DC power supply, a power supply supporting the ATX standard, and a load unit, and includes a first switch to a seventh switch, a first DC transformer, and a second DC transformer.

The first switch includes a first terminal receiving a first input voltage of 5 volts from the power supply, an enable terminal, a disabling terminal, and a first intermediate voltage output of 5 volts. a second end. The second switch includes a first end electrically connected to the second end of the first switch to receive the first intermediate voltage, an enabling end, and a second end outputting a first output voltage of 5 volts .

The first DC transformer includes an input terminal receiving a second input voltage of 12 volts from the power supply or the DC power supply, an enabling terminal, a disabling terminal, and an output terminal of 5 volts. An output terminal of the second intermediate voltage. The third switch includes a first terminal electrically connected to the output terminal of the first DC transformer to receive the second intermediate voltage, an enabling terminal, and a second terminal outputting the first intermediate voltage.

The fourth switch includes a first terminal electrically connected to the second terminal of the third switch to receive the first intermediate voltage, an enabling terminal, a disabling terminal, and a second output voltage whose magnitude is 5 volts an output terminal of . The fifth switch includes a first terminal receiving the second input voltage from the power supply or the DC power supply, an enabling terminal, and a second terminal outputting a third intermediate voltage.

The second DC transformer includes an input terminal electrically connected to the second terminal of the fifth switch to receive the third intermediate voltage, an enabling terminal, a disabling terminal, and a third output voltage whose magnitude is 3.3 volts an output terminal of . The sixth switch includes a first end electrically connected to the output end of the second DC transformer to receive the third output voltage, an enable end, and a second end for outputting a fourth output voltage of 3.3 volts . The seventh switch includes a first terminal electrically connected to the output terminal of the second DC transformer to receive the third output voltage, an enabling terminal, a disabling terminal, and a fifth output voltage whose output magnitude is 3.3 volts a second end of .

Wherein, the parallel output of the first output voltage and the second output voltage is a first parallel output voltage, the parallel output of the fourth output voltage and the fifth output voltage is a second parallel output voltage, and the DC power supply and the power supply Only one of the suppliers is electrically connected to the power control system, and can output the second input voltage, the first intermediate voltage, the third output voltage, the first parallel output voltage, and the second parallel output voltage. output voltage to the load cell.

Preferably, the power control system is also applicable to a chipset supporting Advanced Configuration and Power Interface (ACPI). Wherein, the enabling terminal and the disabling terminal of the first switch respectively receive the first input voltage and the second intermediate voltage. The enabling end of the second switch receives a signal indicating a depth Sx state from the chipset. The enabling terminal and the disabling terminal of the first DC transformer respectively receive the second input voltage and the first input voltage. The enabling end of the third switch receives the second intermediate voltage. The enabling terminal and the disabling terminal of the fourth switch respectively receive a signal indicating the state of S3 and the first input voltage from the chipset. The enabling end of the fifth switch receives the first input voltage. The enabling end of the second DC transformer receives the second input voltage and the first intermediate voltage. The disabled end of the second DC transformer receives the first input voltage. The enabling terminal of the sixth switch receives the signal indicating the state of depth Sx from the chipset. The enabling end and the disabling end of the seventh switch respectively receive the signal indicating the state of S3 from the chipset and the first input voltage.

Preferably, the power control system further includes a first diode, and the first diode includes an anode terminal receiving the first input voltage, and a cathode terminal electrically connected to the input terminal of the second DC transformer.

Preferably, when the chipset instructs the load unit to operate in a deep Sx state, the power control system outputs the first intermediate voltage and the third output voltage to the load unit. When the chipset instructs the load unit to operate in a deep S5 state, the power control system outputs the second input voltage, the first intermediate voltage, and the third output voltage to the load unit. When the chipset instructs the load unit to operate in the S5 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, and the fourth output voltage to the load unit.

When the chipset indicates that the load unit operates in the S0 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, the The second output voltage and the fifth output voltage are sent to the load unit. When the chipset instructs the load unit to operate in the S3 state, the power control system outputs the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, and the second output voltage to the load unit.

Preferably, when the signal indicating the deep Sx state output by the chipset is equal to logic 0, the second switch and the sixth switch are controlled not to conduct, so that the load unit operates in the deep Sx state. And when the signal indicating the deep Sx state output by the chipset is equal to logic 1, the second switch and the sixth switch are controlled to be turned on, so that the load unit does not operate in the deep Sx state.

Preferably, the power control system further includes a first connector, a second connector, and a third connector. Wherein, the first connector and the second connector both support the ATX standard and include 24 pins and 4 pins respectively, and are electrically connected to the first switch, the fourth switch, the fifth switch, the The seventh switch, the first DC transformer, the second DC transformer, and the first diode are used to receive the first input voltage and output it to the first switch when electrically connected to the power supply The first end and the enable end of the fourth switch, the disable end of the fourth switch, the enable end of the fifth switch, the disable end of the seventh switch, the disable end of the first DC transformer The energy end, the disabled end of the second DC transformer, and the anode end of the first diode, and also receive the second input voltage to output to the first end of the fifth switch, the first The first terminal and the enabling terminal of a DC transformer, and the enabling terminal of the second DC transformer. The third connector is used to receive the second input voltage when electrically connected to the DC power supply, so as to output to a 4th pin and a 24th pin of the first connector, and then output to the fifth switch. The first terminal, the first terminal and the enabling terminal of the first DC transformer, and the enabling terminal of the second DC transformer.

Compared with the prior art, the present invention utilizes the first switch to the seventh switch, the first DC transformer, and the multiple enable terminals and multiple disable terminals of the second DC transformer in the power control system. Terminal control, so that whether the hardware device is powered by the power supply or the DC power supply, it can output various output voltages to the load in different states that support the Advanced Configuration and Power Interface (ACPI) unit.

【Description of drawings】

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein:

Fig. 1 is a block diagram illustrating an embodiment of the power supply control system of the present invention;

Fig. 2 is a schematic diagram illustrating three kinds of joints of this embodiment;

Fig. 3 is a circuit diagram illustrating a kind of aspect of a first switch of this embodiment;

Fig. 4 is a circuit diagram illustrating a kind of aspect of a second switch of this embodiment; And

Fig. 5 is a circuit diagram illustrating an aspect of a first DC transformer of the embodiment.

【Detailed ways】

Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same numerals.

Referring to FIG. 1 , an embodiment of the power control system of the present invention is applicable to a DC power supply, a power supply supporting the ATX standard, and a hardware device. The power control system 1 includes a first switch to a seventh switch 11 - 17 , a first DC transformer 18 , a second DC transformer 19 , and a first diode 20 .

In this embodiment, the hardware device is, for example, an embedded system, and includes a chipset (PCH), a load unit, a casing, and a mainboard. The chipset, the load unit, and the power control system 1 are arranged on the mainboard, and are arranged in the casing together with the mainboard. The chipset supports the Advanced configuration and power interface (ACPI) standard. The load unit is, for example, a processor, at least one memory, and other application circuits and chips. This power supply supports ATX standard. The DC power supply is, for example, an AC-DC transformer to convert the AC commercial power into a second input voltage of DC. In this embodiment, the magnitude of the second input voltage is 12 volts, while in other embodiments , can also be, for example, 24 volts, or other values between 12-24 volts.

Referring to FIG. 1 and FIG. 2 , the power source of the hardware device is from one of the power supply and the DC power supply. In more detail, the motherboard is provided with a first connector 31, a second connector 32, and a third connector 33, when the power supply is arranged in the case and through the first connector 31 and the second When the connector 32 outputs the first input voltage V_5P0_ATX or the DC power supply outputs the second input voltage +12VIN through the third connector 33 , various voltages required by the chip set and the load unit can be provided.

In more detail, both the first connector 31 and the second connector 32 support the ATX standard and include 24 pins and 4 pins respectively, and are electrically connected to the first switch 11 and the fourth switch 14 , the fifth switch 15, the seventh switch 17, the first DC transformer 18, the second DC transformer 19, and the first diode 20, and are used to output the The first input voltage V_5P0_ATX is received, and a 4th pin and a 24th pin among the pins output the received second input voltage +12VIN. And when the power supply is not set, and the DC power supply inputs the second input voltage +12VIN through the third connector 33, the third connector outputs the second input voltage +12VIN to the first connector 31 and The 4th pin and the 24th pin of the second connector 32 are connected via the first switch 11 to the seventh switch 17, the first DC transformer 18, the second DC transformer 19, and the first DC transformer 19. A diode 20 can also provide various voltages required for the operation of the chipset and the load unit. That is to say, when a power supply supporting the ATX standard is installed, the power supply outputs the first input voltage V_5P0_ATX through the first connector 31 and the second connector 32, and when powered by the DC power supply, it is connected with The third connector 33 is connected to output the second input voltage +12VIN to the first connector 31 and the second connector 32 through the third connector 33, thereby providing various functions required for the operation of the chipset and the load unit. Voltage. In addition, it should be noted that the third connector 33 in FIG. 2 includes 8 pins, and in other embodiments, the third connector 33 may also include other numbers of pins.

The first switch 11 includes a first end receiving a first input voltage V_5P0_ATX of 5 volts from the power supply, an enable end receiving the first input voltage V_5P0_ATX, and an end receiving a second intermediate voltage V_5P0A_DC a disable end, and a second end outputting a first intermediate voltage V_5P0_A of 5 volts.

The second switch 12 includes a first end electrically connected to the second end of the first switch 11 to receive the first intermediate voltage V_5P0_A, and a signal SLP_SUS# indicating a depth Sx state from the chipset. terminal, and a second terminal outputting a first output voltage 5VSB of 5 volts.

The first DC transformer 18 includes an input terminal receiving the second input voltage +12VIN of 12 volts from the power supply or the DC power supply, an enabling terminal receiving the second input voltage +12VIN, receiving A disable terminal of the first input voltage V_5P0_ATX, and an output terminal of the second intermediate voltage V_5P0A_DC outputting magnitude of 5 volts.

The third switch 13 includes a first end electrically connected to the output end of the first DC transformer 18 to receive the second intermediate voltage V_5P0A_DC, an enabling end for receiving the second intermediate voltage V_5P0A_DC, and outputting the first A second terminal of the intermediate voltage V_5P0_A.

The fourth switch 14 includes a first end electrically connected to the second end of the third switch 13 to receive the first intermediate voltage V_5P0_A, and an enabling end for receiving a signal SLP_S3# from the chipset indicating the state of S3 , a disabling terminal receiving the first input voltage V_5P0_ATX, and an output terminal outputting a second output voltage VCC of 5 volts.

The fifth switch 15 includes a first terminal receiving the second input voltage +12VIN from the power supply or the DC power supply, an enabling terminal receiving the first input voltage V_5P0_ATX, and outputting a third intermediate voltage + A second terminal of 12V_A.

The second DC transformer 19 includes an input end electrically connected to the second end of the fifth switch 15 to receive the third intermediate voltage +12V_A, an enabling end, a disabling end, and an output voltage of 3.3 volts. An output terminal of the third output voltage V_3P3_A. The enable terminal receives the second input voltage +12VIN and the first intermediate voltage V_5P0_A. The disable terminal receives the first input voltage V_5P0_ATX.

The sixth switch 16 includes a first end that is electrically connected to the output end of the second DC transformer 19 to receive the third output voltage V_3P3_A, and receives the signal SLP_SUS# indicating the depth Sx state from the chipset. The energy terminal, and a second terminal outputting a fourth output voltage 3VSB with a magnitude of 3.3 volts.

The seventh switch 17 includes a first terminal electrically connected to the output terminal of the second DC transformer 19 to receive the third output voltage V_3P3_A, and a capability to receive the signal SLP_S3# indicating the state of S3 from the chipset. terminal, a disabled terminal receiving the first input voltage V_5P0_ATX, and a second terminal outputting a fifth output voltage VCC3 with a magnitude of 3.3 volts.

The first diode 20 includes an anode end receiving the first input voltage V_5P0_ATX, and a cathode end electrically connected to the input end of the second DC transformer 19 .

More specifically, the first intermediate voltage V_5P0_A will pass through at least one other DC voltage converter, for example, first convert 3.3 volts and then 1.8 volts (or 1.5 volts) of DC voltage as a standby power supply (Standbypower), The backup power is then provided to the chipset as a source of power required to operate in various power-saving states of the Advanced Configuration and Power Interface (ACPI).

In addition, the first output voltage 5VSB and the second output voltage VCC are also connected in parallel to form a first parallel output voltage 5V_DUAL. The fourth output voltage 3VSB and the fifth output voltage VCC3 are further output in parallel to form a second parallel output voltage 3V_DUAL.

When the chipset indicates that the load unit operates in a deep Sx (Deep Sx) state, the chipset controls the output signal SLP_SUS# indicating the depth Sx state to be equal to logic 0, so that the second switch 12 and the sixth The switch 16 is not conducting, and the output signal SLP_S3# indicating the state of S3 is controlled to be equal to logic 0, so that the fourth switch 14 and the seventh switch 17 are not conducting. At this time, when the power source of the hardware device is from the power supply, the first switch 11 is turned on, the first DC transformer 18 transfers the second intermediate voltage V_5P0A_DC, and the third switch 13 is turned on The first intermediate voltage V_5P0_A is output, the fifth switch 15 is turned on, and the second DC transformer 19 outputs the third output voltage V_3P3_A. That is to say, the power control system 1 outputs the first intermediate voltage V_5P0_A and the third output voltage V_3P3_A to the load unit.

Conversely, when the power source of the hardware device is from the DC power supply, the first switch 11 is not turned on, the first DC transformer 18 transfers the second intermediate voltage V_5P0A_DC, and the third switch 13 is turned on to output For the first intermediate voltage V_5P0_A, the fifth switch 15 is not turned on, and the second DC transformer 19 outputs the third output voltage V_3P3_A. That is to say, the power control system 1 also outputs the first intermediate voltage V_5P0_A and the third output voltage V_3P3_A to the load unit.

When the chipset indicates that the load unit operates in the deep S5 (Deep S5) state, at this moment, the signal SLP_SUS# indicating the depth Sx state output by the chipset is equal to logic 1, and the second switch 12 and the second switch 12 are controlled. The six switches 16 are turned on, and the power control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V_5P0_A, and the third output voltage V_3P3_A to the load unit.

When the chipset indicates that the load unit operates in the S5 state, at this time, the signal SLP_SUS# indicating the depth Sx state output by the chipset is equal to logic 1, and the second switch 12 and the sixth switch 16 are controlled to be turned on. , the power supply control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V_5P0_A, the third output voltage V_3P3_A, the first parallel output voltage 5V_DUAL through the first output voltage 5VSB, and the first parallel output voltage 5V_DUAL through the first The quad output voltage 3VSB is output as the second parallel output voltage 3V_DUAL to the load unit.

When the chipset indicates that the load unit operates in the S0 state, at this time, the signal SLP_SUS# indicating the depth Sx state output by the chipset is equal to logic 1, and the second switch 12 and the sixth switch 16 are controlled to be turned on. , the power supply control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V_5P0_A, the third output voltage V_3P3_A, and outputs the first parallel output through the first output voltage 5VSB and the second output voltage VCC The voltage 5V_DUAL is output to the load unit as the second parallel output voltage 3V_DUAL via the fourth output voltage 3VSB and the fifth output voltage VCC3.

When the chipset indicates that the load unit operates in the S3 state, the chipset controls the output signal SLP_SUS# indicating the depth Sx state to be equal to logic 1, so that the second switch 12 and the sixth switch 16 are turned on, And when the output signal SLP_S3# indicating the state of S3 is equal to logic 1, the fourth switch 14 and the seventh switch 17 are turned on. At this time, when the power source of the hardware device is from the power supply, the first switch 11 is turned on, the first DC transformer 18 transfers the second intermediate voltage V_5P0A_DC, and the third switch 13 is turned on The first intermediate voltage V_5P0_A is output, the fifth switch 15 is turned on, and the second DC transformer 19 outputs the third output voltage V_3P3_A. That is to say, the power supply control system 1 outputs the first intermediate voltage V_5P0_A, the third output voltage V_3P3_A, outputs the first parallel output voltage 5V_DUAL via the first output voltage 5VSB and the second output voltage VCC, and outputs via the first output voltage 5VSB and the second output voltage VCC. The fourth output voltage 3VSB is output as the second parallel output voltage 3V_DUAL to the load unit.

Conversely, when the power source of the hardware device is from the DC power supply, the first switch 11 is not turned on, the first DC transformer 18 transfers the second intermediate voltage V_5P0A_DC, and the third switch 13 is turned on to output For the first intermediate voltage V_5P0_A, the fifth switch 15 is not turned on, and the second DC transformer 19 outputs the third output voltage V_3P3_A. That is to say, the power control system 1 also outputs the first intermediate voltage V_5P0_A, the third output voltage V_3P3_A, outputs the first parallel output voltage 5V_DUAL through the first output voltage 5VSB and the second output voltage VCC, and The second parallel output voltage 3V_DUAL is output to the load unit via the fourth output voltage 3VSB.

Referring to FIG. 1 and FIG. 3 , FIG. 3 illustrates an example of the first switch 11 . The first switch 11 includes two resistors R1, R2, an N-type transistor N1, and a P-type transistor P1. When the power supply outputs the first input voltage V_5P0_ATX through the first connector, and when the first input voltage V_5P0_ATX received by the enabling terminal reaches half of the rated value, the N-type transistor N1 is turned on. , and the P-type transistor P1 is turned on, so that the second end of the first switch 11 is turned on with the first end, that is, the first intermediate voltage V_5P0_A is equal to the first input voltage V_5P0 _ATX. And when the DC power supply outputs the second input voltage +12VIN through the second connector, and when the second intermediate voltage V_5P0A_DC reaches half of the rated value, the P-type transistor P1 is not turned on. At this time, the N The type transistor N1 is also turned on, so as to prevent the first intermediate voltage V_5P0_A from feeding back the first input voltage V_5P0_ATX.

Referring to FIG. 1 and FIG. 4 , FIG. 4 illustrates an example of the second switch 12 . The second switch 12 includes a P-type transistor P2. When the signal SLP_SUS# indicating the depth Sx state from the chipset is equal to logic 1, the P-type transistor P2 is turned on, so that the second end of the second switch 12 is turned on with the first end, that is, the first end of the second switch 12 is turned on. An output voltage 5VSB is equal to the first intermediate voltage V_5P0_A.

Referring to FIG. 1 and FIG. 5 , FIG. 5 illustrates an example of the first DC transformer 18 . The first DC transformer 18 includes a resistor R4 , an N-type transistor N2 , and a first DC converter (DC-DC converter) 181 . The first DC converter 181 has an enabling terminal for controlling the first DC converter 181 to switch out or not switch out an output voltage according to the logic signal received by the enabling terminal. By virtue of the connection relationship between the resistor and the N-type transistor N2 and the enabling end of the first DC converter 181, the first DC converter 181 originally only capable of enabling can become capable of enabling. The first DC transformer 18 can be used with or without functions. It should be noted that in other embodiments, a DC transformer which itself has two functions of enabling and disabling can also be used.

In addition, it should be specially added that: from the perspective of the prior art in the field of the present invention, the implementation manners of the first switch to the seventh switch 11-17, the first DC transformer 18, or the second DC transformer 19 There are many known circuit architectures and forms, and the above-mentioned FIGS. 3 to 5 merely illustrate the implementation of two types of switches and one type of DC transformer simply and exemplarily, and are not limited thereto.

In summary, through the control of the first switch to the seventh switch, the first DC transformer, and the multiple enabling terminals and multiple disabling terminals of the second DC transformer of the power supply control system, so that Whether the hardware device is powered by the power supply or the DC power supply, it can output various output voltages to the load unit under different states that support the Advanced Configuration and Power Interface (ACPI), thereby realizing A power control system compatible with ATX standard power supply or direct current as input power, so it can really achieve the purpose of the present invention.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (6)

1. A power control system adapted for a dc power supply, a power supply supporting ATX standard, and a load unit, comprising:

a first switch including a first terminal receiving a first input voltage of 5 volts from the power supply, an enable terminal, a disable terminal, and a second terminal outputting a first intermediate voltage of 5 volts;

a second switch including a first terminal electrically connected to the second terminal of the first switch for receiving the first intermediate voltage, an enable terminal, and a second terminal for outputting a first output voltage of 5 volts;

a first DC transformer including an input terminal receiving a second input voltage of 12 volts from the power supply or the DC power supply, an enable terminal, a disable terminal, and an output terminal outputting a second intermediate voltage of 5 volts;

a third switch, including a first end electrically connected to the output end of the first DC transformer for receiving the second intermediate voltage, an enable end, and a second end for outputting the first intermediate voltage;

a fourth switch including a first end electrically connected to the second end of the third switch for receiving the first intermediate voltage, an enable end, a disable end, and an output end for outputting a second output voltage of 5 volts;

a fifth switch including a first terminal receiving the second input voltage from the power supply or the dc power supply, an enable terminal, and a second terminal outputting a third intermediate voltage;

a second dc transformer including an input terminal electrically connected to the second terminal of the fifth switch for receiving the third intermediate voltage, an enable terminal, a disable terminal, and an output terminal for outputting a third output voltage of 3.3 volts;

a sixth switch including a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, and a second terminal for outputting a fourth output voltage of 3.3 volts; and

a seventh switch including a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, a disable terminal, and a second terminal for outputting a fifth output voltage of 3.3 volts;

the first output voltage and the second output voltage are output in parallel to form a first parallel output voltage, the fourth output voltage and the fifth output voltage are output in parallel to form a second parallel output voltage, only one of the direct current power supply and the power supply can be electrically connected with the power supply control system, and the direct current power supply and the power supply can output the second input voltage, the first intermediate voltage, the third output voltage, the first parallel output voltage and the second parallel output voltage to the load unit.

2. The power control system of claim 1, further adapted to a chipset supporting advanced configuration and power interface, wherein the enable terminal and the disable terminal of the first switch receive the first input voltage and the second intermediate voltage, respectively, the enable terminal and the disable terminal of the second switch receive a signal indicating a depth Sx state from the chipset, the enable terminal and the disable terminal of the first dc transformer receive the second input voltage and the first input voltage, respectively, the enable terminal and the disable terminal of the third switch receive the second intermediate voltage, the enable terminal and the disable terminal of the fourth switch receive a signal indicating an S3 state and the first input voltage, respectively, the enable terminal of the fifth switch receive the first input voltage, the enable terminal of the second dc transformer receive the second input voltage and the first intermediate voltage, the disable terminal of the second dc transformer receive the first input voltage, the sixth switch receive the signal indicating the depth Sx state and the enable terminal of the seventh switch receive the signal indicating the depth Sx state, respectively.

3. The power control system of claim 2, further comprising a first diode including an anode terminal receiving the first input voltage and a cathode terminal electrically connected to the input terminal of the second dc transformer.

4. The power control system of claim 3,

when the chipset indicates that the load unit is operating in the Sx state, the power control system outputs the first intermediate voltage and the third output voltage to the load unit,

when the chipset indicates the load unit to operate in the deep S5 state, the power control system outputs the second input voltage, the first intermediate voltage, and the third output voltage to the load unit,

when the chipset indicates that the load unit operates in the S5 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, and the fourth output voltage to the load unit,

when the chipset indicates the load unit to operate in the S0 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, the second output voltage, and the fifth output voltage to the load unit,

when the chipset indicates that the load unit operates in the S3 state, the power control system outputs the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, and the second output voltage to the load unit.

5. The power control system of claim 4, wherein when the signal indicating the Sx state outputted from the chipset is equal to logic 0, the second switch and the sixth switch are controlled to be turned off, so that the load unit operates in the Sx state,

and when the signal indicating the depth Sx state output by the chip set is equal to logic 1, controlling the second switch and the sixth switch to be conducted so that the load unit does not operate in the depth Sx state.

6. The power control system of claim 4 further comprising a first connector, a second connector, and a third connector,

the first connector and the second connector both support the ATX standard and respectively include 24 pins and 4 pins, and are electrically connected to the first switch, the fourth switch, the fifth switch, the seventh switch, the first dc transformer, the second dc transformer, and the first diode, and are configured to receive the first input voltage to output to the first terminal and the enable terminal of the first switch, the disable terminal of the fourth switch, the enable terminal of the fifth switch, the disable terminal of the seventh switch, the disable terminal of the first dc transformer, the disable terminal of the second dc transformer, and the anode terminal of the first diode, and further receive the second input voltage to output to the first terminal of the fifth switch, the first terminal and the enable terminal of the first dc transformer, and the enable terminal of the second dc transformer, when electrically connected to the power supply,

the third connector is used for receiving the second input voltage when being electrically connected with the direct current power supply so as to output the second input voltage to a 4 th pin and a 24 th pin of the first connector, and further output the second input voltage to the first end of the fifth switch, the first end and the enabling end of the first direct current transformer and the enabling end of the second direct current transformer.

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