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CN115273936A - MAC array based on resistive random access memory and MAC array operation method - Google Patents

MAC array based on resistive random access memory and MAC array operation method Download PDF

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CN115273936A
CN115273936A CN202210702582.2A CN202210702582A CN115273936A CN 115273936 A CN115273936 A CN 115273936A CN 202210702582 A CN202210702582 A CN 202210702582A CN 115273936 A CN115273936 A CN 115273936A
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resistive memory
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mac array
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CN115273936B (en
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刘业帆
周煜梁
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Xinyuan Semiconductor Shanghai Co ltd
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Xinyuan Semiconductor Shanghai Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell

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Abstract

本发明提供一种基于阻变存储器的MAC阵列，存储有不同权重的相同位的1T1R阻变式存储单元分布在相邻连续的多条位线上；存储有相同权重的不同位的1T1R阻变式存储单元分布在同一条位线上，且以2n条字线为间隔；每个1T1R阻变式存储单元包括晶体管‑阻变存储器；阻变存储器包括电阻，所述电阻与所述晶体管相连接，字线用于传输输入信号；源线为电阻施加电压，以在位线上形成偏置电流，ADC模块对位线中的偏置电流进行转换以形成数字乘积运算结果，移位加法器用于对数字乘积运算结果进行求和以获取MAC运算结果，如此，每次只打开一行字线，多根位线连接到同一ADC，实现模数转换和求和运算，因此在计算他们的电流和时，寄生参数带来的影响大大减小。

Figure 202210702582

The present invention provides a MAC array based on resistive memory. 1T1R resistive memory cells that store the same bit with different weights are distributed on adjacent consecutive bit lines; 1T1R resistive memory cells that store different bits with the same weight Each 1T1R resistive memory cell includes a transistor-resistive memory; the resistive memory includes a resistor, which is in phase with the transistor. Connection, the word line is used to transmit the input signal; the source line applies a voltage to the resistor to form a bias current on the bit line, and the ADC module converts the bias current in the bit line to form a digital product operation result, which is used by the shift adder For summing the digital product operation results to obtain the MAC operation results, in this way, only one row of word lines is turned on at a time, and multiple bit lines are connected to the same ADC to achieve analog-to-digital conversion and summation operations, so the sum of their currents is calculated. , the influence of parasitic parameters is greatly reduced.

Figure 202210702582

Description

MAC array based on resistive random access memory and MAC array operation method
Technical Field
The invention relates to the technical field of memories, in particular to an MAC array based on a resistive random access memory and an MAC array operation method.
Background
The multiplication and addition operation (MAC) isThe most important calculation method of Neural network (Neural network) represents two groups of numbers (A)0,A1,A2…)(B0,B1,B28230;) sum of the products of (A)0·B0+A1·B1+A2B2+ \8230). A resistance change memory, which is a type of nonvolatile memory, stores information using a resistance state of a device. When voltage is applied to two ends of the device, the input voltage and the resistance of the device respectively represent 1bit signals, and multiplication operation is realized in the form of output current. The sum of the output currents represents the product sum of the 1-bit input signals and the 1-bit stored information, i.e., the MAC operation. The MAC array based on the Resistive Random Access Memory (RRAM) has the characteristics of high density, low cost and high energy efficiency. The invention provides an MAC operation array architecture based on a resistive random access memory, which obviously improves the calculation speed by utilizing the division of an input signal time domain on the basis of ensuring higher operation precision.
However, since the actual size of the resistive random access memory array usually exceeds 1Mb, the long WL/BL wiring causes a large amount of parasitic resistance/capacitance, which causes a large current drift when the products of memory cells at different positions in the array and the WL input signal are the same during calculation, and further reduces the distinction degree between different products and corresponding total current, and in a severe case, even causes the different products and corresponding current ranges to overlap, thereby generating a read error. In a 1Mb RRAM MAC array of 28nm technology, the current reading difference of the traditional method at the position of WL/BL parasitic optimum/worst is in the optimum/worst case, the range of MAC summation current is overlapped seriously, and the reading error is caused. In order to solve the problem, each ADC needs to be modulated separately, but this greatly increases the difficulty of circuit design and test cost and severely reduces the accuracy of MAC operation under the requirement of a large computational power and large array.
Therefore, there is a need for a MAC array and an operation method based on a resistive random access memory, which significantly reduce errors in calculation results due to resistance differences of resistive random access memory devices and parasitic parameters of large arrays, and minimize accuracy loss.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a MAC array based on a resistive random access memory, so as to solve the problem that the actual size of the resistive random access memory array usually exceeds 1Mb, wherein a long WL/BL wiring causes a large amount of parasitic resistance/capacitance, which causes a large current drift when the products of memory cells at different positions in the array and WL input signals are the same during calculation, and further reduces the discrimination between different products and corresponding total currents, which even causes the overlapping of different products and corresponding current ranges in severe cases, resulting in read errors; the range of the MAC summation current is seriously overlapped, so that reading errors are caused, the difficulty and the test cost of circuit design are increased, and the accuracy of MAC operation is seriously reduced.
The invention provides a MAC array based on a resistive random access memory, which comprises a 1T1R resistive random access memory unit, word lines, source lines, bit lines, an ADC module and a shift adder, and is characterized in that,
1T1R resistance variable memory cells storing same bits with different weights are distributed on a plurality of adjacent continuous bit lines; wherein the spacing of the bit lines is less than or equal to 8;
the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and have a value of 2nThe strip word lines are at intervals; n is less than or equal to 5;
each 1T1R resistive random access memory unit comprises a transistor-resistive random access memory;
the resistive random access memory comprises a resistor, wherein the resistor is connected with the transistor and can be high or low;
the word line is connected with the gate end of the transistor, is controlled by a decoder and is used for transmitting an input signal;
the source line and the 1T1R resistive memory cell, and the source line is used for applying voltage to the resistor to form bias current on the bit line;
the ADC module is connected with the bit lines, all the bit lines share one ADC module, and the ADC module is used for converting the bias current in the bit lines to form a digital product operation result;
the shift adder is used for summing the digital product operation results to obtain a MAC operation result.
Preferably, the bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance.
Preferably, the device also comprises a control unit,
the control unit is used for simultaneously opening a row of word lines and a plurality of bit lines to carry out MAC operation.
Preferably, the control unit is further configured to perform a set operation and a reset operation on a row of word lines before a simultaneous row of word lines.
Preferably, the set operation is: applying high voltage to the bit line and the word line, and grounding the source line;
the reset operation is: the word line and the source line apply high voltage, and the bit line is grounded.
Preferably, a voltage value of the word line in the set operation is less than half of a voltage value in the reset operation.
The invention also provides an MAC array operation method based on the resistive random access memory, which is realized based on the MAC array based on the resistive random access memory and comprises the following steps:
simultaneously opening a row of word lines, bit lines and source lines at preset intervals in the MAC array based on the resistive random access memory;
applying a voltage to a resistor in the resistive random access memory based on the source line based on the word line transmission input signal to form a bias current on the bit line;
the ADC module in the MAC array based on the resistive random access memory is used for converting the bias current in the bit line to form a digital product operation result;
and summing the digital product operation result through a shift adder in the MAC array based on the resistive random access memory to obtain an MAC operation result.
Preferably, before a row of word lines is simultaneously turned on, the row of word lines is subjected to a set operation and a reset operation;
the setting operation is as follows: the bit line and the word line apply high voltage, and the source line is grounded;
the reset operation is: the word line and the source line apply high voltage, and the bit line is grounded.
According to the technical scheme, the MAC array based on the resistive random access memory comprises 1T1R resistive random access memory units, word lines, source lines, bit lines, an ADC module and a shift adder, wherein the 1T1R resistive random access memory units storing the same bits with different weights are distributed on a plurality of adjacent continuous bit lines; wherein the spacing of the bit lines is less than or equal to 8; the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and have a value of 2nThe strip word lines are at intervals; each 1T1R resistive random access memory unit comprises a transistor-resistive random access memory; the resistive random access memory comprises a resistor, wherein the resistor is connected with the transistor and can be high or low; the word line is connected with the gate end of the transistor and is controlled by a decoder, and the word line is used for transmitting an input signal; the source line and the 1T1R resistance change type memory unit are used for applying voltage to a resistor to form bias current on a bit line, the ADC module is connected with the bit line, all the bit lines share one ADC module, the ADC module is used for converting the bias current in the bit line to form a digital product operation result, and the shift adder is used for summing the digital product operation result to obtain an MAC operation result; at the same time, for all 1T1R cells of the same WL, their BL parasitic parameters are substantially identical, so when calculating their current sums, the parasitic parameters bring aboutThe influence of (a) is greatly reduced.
Drawings
Other objects and results of the present invention will become more apparent and readily appreciated by reference to the following specification taken in conjunction with the accompanying drawings, and as the invention becomes more fully understood. In the drawings:
fig. 1 is a schematic diagram of a resistive random access memory based MAC array according to an embodiment of the present invention;
fig. 2 is a flowchart of an operation method of a MAC array based on a resistive random access memory according to an embodiment of the present invention;
Detailed Description
Because the actual size of the resistive random access memory array usually exceeds 1Mb, a large amount of parasitic resistance/capacitance is caused by long WL/BL wiring, so that when the product of memory cells at different positions in the array and WL input signals is the same, the current can also greatly drift, the discrimination between different products and corresponding total current is further reduced, and in severe cases, even different products and corresponding current ranges can be overlapped, and reading errors can be generated; in a 1Mb RRAM MAC array in a 28nm process, under the condition that the current reading difference of the traditional method at the optimal/worst position of WL/BL parasitics is optimal/worst, the range of MAC summation current is seriously overlapped, so that reading errors are caused; in order to solve the problem, each ADC needs to be modulated separately, but this greatly increases the difficulty of circuit design and test cost and seriously reduces the accuracy of MAC operation under the requirement of a large computational power array. In view of the above problems, the present invention provides a MAC array based on a resistive random access memory, and the following describes in detail a specific embodiment of the present invention with reference to the accompanying drawings.
In order to illustrate the MAC array based on the resistive random access memory and the operation method thereof provided by the present invention, fig. 1 schematically indicates the MAC array based on the resistive random access memory according to the embodiment of the present invention; fig. 2 shows an example of an operation method of a MAC array based on a resistive random access memory according to an embodiment of the present invention.
The following description of the exemplary embodiment(s) is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Techniques and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be considered a part of the specification where appropriate.
As shown in fig. 1, the MAC array based on the resistive random access memory according to the embodiment of the present invention includes 1T1R resistive random access memory cells, word lines, source lines, bit lines, an ADC module, and a shift adder, where the 1T1R resistive random access memory cells storing identical bits with different weights are distributed on a plurality of adjacent continuous bit lines; wherein the spacing of the bit lines is less than or equal to 8; the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and have a value of 2nThe word lines are intervals; in this embodiment, the 1T1R cells storing the same bits with different weights are distributed on the adjacent BL (bit line), that is, the 1T1R resistive memory cells storing the same bits with different weights are distributed on the adjacent consecutive bit lines, so that the parasitic parameters between the 1T1R cells are very close when the MAC operation is performed on the same bit, and the summation error of the product of the same bit can be avoided. Different bits with the same weight are distributed on the same BL and are not distributed continuously, but are spaced by 4/8/16/32 WLs, and the spacing of bit lines is less than or equal to 8 in the embodiment; taking 4 WLs as an interval for example, WL0 is connected with weight B00Corresponding cell, WL4 connection weight B01Correspondingly, WL8 is connected to the weight B02The corresponding unit 8230effectively improves the precision of high-order operation by the scattered distribution of different bits with the same weight. In the AI operation, the operation error of the lower bits can be generally ignored, therefore, the method can effectively improve the overall operation precision.
In the embodiment shown in fig. 1, each 1T1R resistance change memory cell includes a transistor-resistance change memory; the resistive random access memory comprises a resistor, wherein the resistor is connected with the transistor and can be high or low; the word line is connected with the grid end of the transistor and controlled by the decoder, and the word line is used for transmitting an input signal; the source line and the 1T1R resistance change type memory unit are used for applying voltage to the resistor so as to form bias current on the bit line; the ADC module is connected with the bit line and is used for converting the bias current in the bit line to form a digital product operation result; the shift adder is used for summing the digital product operation result to obtain an MAC operation result; in this embodiment, all bit lines are connected to the same ADC, and a plurality of BLs are connected to the same ADC, so that analog-to-digital conversion sum of multi-bit product sums of a plurality of weights and a plurality of input signals is realized, and larger-scale summation is performed through an addition tree in the periphery, thereby reducing the occupied space, improving the space utilization rate, and improving the operation speed.
In actual operation, only one row of WLs is opened at a time, a plurality of BL are connected to the same ADC, analog-to-digital conversion and summation operation are realized, and larger-scale summation is carried out through an addition tree at the periphery. The method has the advantage of high parallelism of analog summation, and can effectively limit the error within an allowable range.
Specifically, each transistor-resistive random access memory (1T 1R) cell is used to hold one bit of weight, representing 0 when the R resistance is high and 1 when the R resistance is low; WL (word line) is controlled by decoder for transmitting input signal; the SL (source line) is used for applying a fixed reading voltage and forming a bias current on the BL (bit line), and then the bias current is processed by the ADC to generate an MAC operation result; when the WL of the 1T1R cell is taken high, it indicates that the input signal is 1; since the 1T1R cell stores a 1, this current is large, indicating that the product of the input signal and the 1T1R cell is 1; when the 1T1R unit stores 0 or the WL is not gated, the BL current of the unit is very low, which indicates that the product of the input signal and the 1T1R unit is 0; in this embodiment, a bias current is generated based on the input signal and the voltage, reflecting the product of the input signal and the resistance, and by simultaneously opening a row WL, these currents representing the product can be formed into a total current, thereby achieving a summation of the products.
In this embodiment, the apparatus further includes a control unit, configured to open a row of word lines and a plurality of bit lines at preset intervals at the same time, so as to perform a subsequent MAC operation, and complete a summation operation of a product of the input signal and the resistance; the control unit is also used for carrying out setting operation and resetting operation on a row of word lines before simultaneously opening the row of word lines; wherein the set operation is: applying high voltage to the bit line and the word line, and grounding the source line; the reset operation is: applying high voltage to the word line and the source line, and grounding the bit line; wherein a voltage value of the word line in the set operation is less than half of a voltage value in the reset operation.
In one embodiment, during the operation, a row of WL is opened simultaneously each time, the WL interval is 4, the bl interval is 8, and the actual condition can be adjusted to be equal to 4,8, 16, 32, and is calculated as int8 (which can be adjusted according to the actual application). The 0 th bits of B0-B7 are distributed on WL0, the 0 th-7 th bits of B0 are distributed on BL0, the WL0, WL4, WL8, WL12, WL16, WL20, WL24, WL28, the rest weights are repeated, and the like, when in each calculation, a certain WL (such as WL 0) is opened, meanwhile BL0-BL7 input the 0 th-7 th bits of A0-A7 in sequence, and then output currents of a plurality of BL are converted into product sum through ADC. As shown in fig. 1, since the ADC performs current sum conversion on the results of multiple BLs, an ADC in a current mode needs to be used, but the ADC density is significantly reduced compared to fig. 1, which is beneficial to the design of layout wiring, and meanwhile, for all 1T1R cells of the same WL, the BL parasitic parameters are substantially consistent, so that the influence of the parasitic parameters when calculating their current sum is greatly reduced.
Moreover, since the ADC module is shared by a plurality of BLs, the space of the ADC module in the transverse length is greatly expanded, and compared with the design in which one BL corresponds to one ADC as shown in fig. 1, the present invention has a greater advantage in space utilization. Therefore, the ADC module with higher precision and larger area can be configured to realize the summation of more BL, and the parallelism, namely the overall operation speed, is effectively improved.
As described above, the MAC array based on the resistive random access memory provided by the present invention includes 1T1R resistive random access memory cells, word lines, source lines, bit lines, ADC modules, and shift adders, where the 1T1R resistive random access memory cells storing identical bits with different weights are distributed on a plurality of adjacent and consecutive bit lines; wherein the spacing of the bit lines is less than or equal to 8; the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and have a value of 2nThe strip word lines are at intervals; each 1T1R resistive random access memory unit comprises a transistor-resistive random access memory; resistance changeThe memory comprises a resistor which is connected with the transistor and can be high or low; the word line is connected with the gate end of the transistor and is controlled by a decoder, and the word line is used for transmitting an input signal; the source line and the 1T1R resistance change type memory unit are used for applying voltage to a resistor to form bias current on the bit line, the ADC module is connected with the bit line, all the bit lines share one ADC module, the ADC module is used for converting the bias current in the bit line to form a digital product operation result, and the shift adder is used for summing the digital product operation result to obtain an MAC operation result; meanwhile, for all 1T1R units of the same WL, BL parasitic parameters are basically consistent, so when calculating the current sum of the BL parasitic parameters, the influence brought by the parasitic parameters is greatly reduced.
As shown in fig. 2, the present invention further provides an operation method of an MAC array based on a resistive random access memory, which is implemented based on the MAC array based on the resistive random access memory, and includes:
s1: simultaneously opening a row of word lines, bit lines at preset intervals and source lines in the MAC array based on the resistive random access memory;
s2: applying a voltage to a resistor in the resistive random access memory based on the source line based on the word line transmission input signal to form a bias current on the bit line;
s3: the ADC module in the MAC array based on the resistive random access memory is used for converting the bias current in the bit line to form a digital product operation result;
s4: and summing the digital product operation result through a shift adder in the MAC array based on the resistive random access memory to obtain an MAC operation result.
Before a row of word lines are opened simultaneously, carrying out setting operation and resetting operation on the row of word lines;
the setting operation is as follows: the bit line and the word line apply high voltage, and the source line is grounded;
the reset operation is: the word line and the source line apply high voltage, and the bit line is grounded.
Specifically, during operation, all bit lines are connected to the same ADC, a plurality of BL are connected to the same ADC, analog-to-digital conversion sum of multi-bit product sums of a plurality of weights and a plurality of input signals is achieved, large-scale summation is carried out through an addition tree in the periphery, so that the occupied space can be reduced, the space utilization rate is improved, and the operation speed is increased.
In actual operation, only one row of WLs is opened at a time, a plurality of BL are connected to the same ADC, analog-to-digital conversion and summation operation are realized, and larger-scale summation is carried out through an addition tree at the periphery. The method has the advantage of high parallelism of analog summation, and can effectively limit the error within an allowable range.
In one embodiment, during the operation, a row of WL is opened simultaneously each time, the WL interval is 4, the bl interval is 8, and the actual condition can be adjusted to be equal to 4,8, 16, 32, and is calculated as int8 (which can be adjusted according to the actual application). The 0 th bits of B0-B7 are distributed on WL0, the 0 th-7 th bits of B0 are distributed on BL0, the WL0, WL4, WL8, WL12, WL16, WL20, WL24, WL28, the rest weights are repeated, and the like, when in each calculation, a certain WL (such as WL 0) is opened, meanwhile BL0-BL7 input the 0 th-7 th bits of A0-A7 in sequence, and then output currents of a plurality of BL are converted into product sum through ADC. As shown in fig. 1, since the ADC performs current sum conversion on the results of multiple BLs, an ADC in a current mode needs to be used, but the ADC density is significantly reduced compared to fig. 1, which is beneficial to the design of layout wiring, and meanwhile, for all 1T1R cells of the same WL, the BL parasitic parameters are substantially consistent, so that the influence of the parasitic parameters when calculating their current sum is greatly reduced.
Moreover, since the ADC module is shared by multiple BLs, the space of the ADC module in the transverse length is greatly expanded, and compared with the design shown in fig. 1 in which one BL corresponds to one ADC, the present invention has a greater advantage in space utilization. Therefore, the ADC module with higher precision and larger area can be configured to realize the summation of more BL, and the parallelism, namely the overall operation speed, is effectively improved.
According to the embodiment, the operation method of the MAC array based on the resistive random access memory is realized based on the MAC array based on the resistive random access memory, and a row of word lines, bit lines at preset intervals and source lines in the MAC array based on the resistive random access memory are opened at the same time; then transmitting an input signal based on the word line, and applying voltage to the resistor in the MAC array based on the resistance change memory based on the source line so as to form bias current on the bit line; then converting the bias current in the bit line through an ADC module in the MAC array based on the resistive random access memory to form a digital product operation result; finally, the digital product operation result is summed through a shift adder in the resistance random access memory-based MAC array to obtain an MAC operation result, so that only one row of WL (word line) is opened each time during actual operation, a plurality of BL (bit lines) are connected to the same ADC, analog-to-digital conversion and summation operation are realized, large-scale summation is carried out on the periphery through an addition tree, the advantage of high parallelism of analog summation is achieved, and errors can be effectively limited within an allowable range; meanwhile, for all 1T1R units of the same WL, the BL parasitic parameters are basically consistent, so when calculating the current sum of the 1T1R units, the influence brought by the parasitic parameters is greatly reduced.
The MAC array based on the resistance change memory and the operating method according to the present invention are described above by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various modifications can be made to the MAC array and the operation method based on the resistive random access memory proposed in the present invention without departing from the scope of the present invention. Accordingly, the scope of the invention should be determined from the content of the appended claims.

Claims (8)

1.一种基于阻变存储器的MAC阵列，包括1T1R阻变式存储单元、字线、源线、位线、ADC模块和移位加法器，其特征在于，1. A MAC array based on resistive memory, comprising 1T1R resistive memory unit, word line, source line, bit line, ADC module and shift adder, is characterized in that, 存储有不同权重的相同位的1T1R阻变式存储单元分布在相邻连续的多条位线上；其中，所述位线的间隔小于或等于8；1T1R resistive memory cells storing the same bit with different weights are distributed on a plurality of adjacent continuous bit lines; wherein, the interval between the bit lines is less than or equal to 8; 存储有相同权重的不同位的1T1R阻变式存储单元分布在同一条位线上，且以2n条字线为间隔；n小于或等于5；1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line, and are separated by 2 n word lines; n is less than or equal to 5; 每个1T1R阻变式存储单元包括晶体管-阻变存储器；Each 1T1R resistive memory unit includes a transistor-resistive memory; 所述阻变存储器包括电阻，所述电阻与所述晶体管相连接，且所述电阻可高可低；The RRAM includes a resistor, the resistor is connected to the transistor, and the resistor can be high or low; 所述字线与所述晶体管的栅端相连接，所述字线被译码器控制，所述字线用于传输输入信号；The word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; 所述源线与所述1T1R阻变式存储单元，且所述源线用于为所述电阻施加电压，以在所述位线上形成偏置电流；the source line and the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; 所述ADC模块与所述位线相连接，且所有位线共用一个ADC模块，所述ADC模块用于对所述位线中的偏置电流进行转换以形成数字乘积运算结果；The ADC module is connected to the bit line, and all the bit lines share one ADC module, and the ADC module is used to convert the bias current in the bit line to form a digital product operation result; 所述移位加法器用于对所述数字乘积运算结果进行求和以获取MAC运算结果。The shift adder is used for summing the digital product operation results to obtain the MAC operation result. 2.如权利要求1所述的基于阻变存储器的MAC阵列，其特征在于，2. the MAC array based on RRAM as claimed in claim 1, is characterized in that, 所述偏置电流基于所述输入信号与所述电压生成，反映所述输入信号与所述电阻的乘积。The bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance. 3.如权利要求2所述的基于阻变存储器的MAC阵列，其特征在于，还包括控制单元，3. The MAC array based on RRAM as claimed in claim 2, further comprising a control unit, 所述控制单元用于同时打开一行字线和多条位线，以进行MAC运算。The control unit is used for turning on a row of word lines and multiple bit lines at the same time to perform MAC operation. 4.如权利要求3所述的基于阻变存储器的MAC阵列，其特征在于，4. the MAC array based on RRAM as claimed in claim 3, is characterized in that, 所述控制单元还用于在同时打开一行字线之前，对所述一行字线进行置位操作和复位操作。The control unit is further configured to perform a set operation and a reset operation on a row of word lines before simultaneously turning on the row of word lines. 5.如权利要求4所述的基于阻变存储器的MAC阵列，其特征在于，5. the MAC array based on RRAM as claimed in claim 4, is characterized in that, 所述置位操作为：所述位线、所述字线施加高电压，所述源线接地；The setting operation is: applying a high voltage to the bit line and the word line, and grounding the source line; 所述复位操作为：所述字线、所述源线施加高电压，所述位线接地。The reset operation is: applying a high voltage to the word line and the source line, and grounding the bit line. 6.如权利要求5所述的基于阻变存储器的MAC阵列，其特征在于，6. the MAC array based on RRAM as claimed in claim 5, is characterized in that, 所述字线在所述置位操作中的电压值为在所述复位操作中的电压值的一半以下。A voltage value of the word line in the set operation is half or less of a voltage value in the reset operation. 7.一种基于阻变存储器的MAC阵列操作方法，基于如权利要求1-6任一所述的基于阻变存储器的MAC阵列实现，包括：7. A method for operating a MAC array based on a resistive memory, based on the realization of the MAC array based on a resistive memory as described in any one of claims 1-6, comprising: 同时打开基于阻变存储器的MAC阵列中的一行字线、预设间隔的位线和源线；Simultaneously open a row of word lines, bit lines and source lines at preset intervals in the MAC array based on the resistive memory; 基于所述字线传输输入信号，基于所述源线为所述基于阻变存储器的MAC阵列中的电阻施加电压，以在所述位线上形成偏置电流；transmitting an input signal based on the word line, and applying a voltage to a resistor in the MAC array based on the RRAM based on the source line to form a bias current on the bit line; 通过所述基于阻变存储器的MAC阵列中的ADC模块对所述位线中的偏置电流进行转换以形成数字乘积运算结果；Converting the bias current in the bit line through the ADC module in the MAC array based on the resistive variable memory to form a digital product operation result; 通过所述基于阻变存储器的MAC阵列中的移位加法器对所述数字乘积运算结果进行求和以获取MAC运算结果。The result of the digital product operation is summed by a shift adder in the MAC array based on the RRAM to obtain a MAC operation result. 8.如权利要求7所述的基于阻变存储器的MAC阵列操作方法，其特征在于，8. the MAC array operation method based on RRAM as claimed in claim 7, is characterized in that, 在同时打开一行字线之前，对所述一行字线进行置位操作和复位操作；Before simultaneously opening a row of word lines, performing a set operation and a reset operation on the row of word lines; 所述置位操作为：所述位线、所述字线施加高电压，所述源线接地；The setting operation is: applying a high voltage to the bit line and the word line, and grounding the source line; 所述复位操作为：所述字线、所述源线施加高电压，所述位线接地。The reset operation is: applying a high voltage to the word line and the source line, and grounding the bit line.
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