CN115276680A - Multistage tunable ultra-wideband transmitter - Google Patents
Multistage tunable ultra-wideband transmitter Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
本发明公开一种多级可调谐的超宽带发射机，涉及无线通讯领域，针对现有技术中工艺偏差等因素带来精度及可靠性问题而提出本方案。包括依次信号连接的窄脉冲产生电路、三角包络电路、压控环形振荡电路、输出缓冲电路以及天线；窄脉冲产生电路将基带数据信号和时钟信号处理产生纳秒级宽度可调的OOK极窄脉冲信号；三角包络电路将窄脉冲信号通过积分转换为三角脉冲信号；压控环形振荡电路由三角脉冲信号以互补开关形式开启振荡产生频率可调的超宽带信号；输出缓冲电路通过电压控制调整超宽带信号频谱幅度输出符合FCC频谱标准的超宽带射频信号。优点在于实现了脉冲宽度、中心频率以及幅度可调的可调谐性功能，能应对工艺偏差等因素对频率产生的不良影响。
The invention discloses a multi-level tunable ultra-wideband transmitter, which relates to the field of wireless communication, and proposes the solution in view of the problems of accuracy and reliability caused by factors such as process deviation in the prior art. It includes a narrow pulse generation circuit, a triangular envelope circuit, a voltage-controlled ring oscillator circuit, an output buffer circuit and an antenna connected in sequence; Pulse signal; the triangular envelope circuit converts the narrow pulse signal into a triangular pulse signal through integration; the voltage-controlled ring oscillator circuit turns on the oscillation of the triangular pulse signal in the form of a complementary switch to generate an ultra-wideband signal with adjustable frequency; the output buffer circuit is adjusted by voltage control Ultra-Wideband Signal Spectrum Amplitude Outputs an ultra-wideband RF signal that complies with FCC spectrum standards. The advantage is that it realizes the tunability function with adjustable pulse width, center frequency and amplitude, and can cope with the adverse effects of process deviation and other factors on the frequency.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a multistage tunable ultra-wideband transmitter.
Background
In 2002, the Federal Communications Commission (FCC) defined a signal with a-10 dB bandwidth greater than 500MHz or a central frequency of more than 20% as an ultra-wideband signal, specified two frequency bands of 0 to 960MHz and 3.1GHz to 10.6GHz as civil ultra-wideband communications, and required that the radiated power spectral density of the ultra-wideband signal be lower than-41.3 dBm/MHz. The ultra-wideband signal can run on a baseband, depends on nanosecond-level time domain pulse waveforms, and does not need sine wave carrier wave or intermediate frequency processing. According to the characteristics, the ultra-wideband radio communication can be applied to through-wall imaging, precise positioning, medical monitoring and the like, and has the advantages of wide bandwidth, high precision, low power consumption and large data volume.
The ultra-wideband transmitter needs to have a well-balanced trade-off relationship in the aspects of circuit complexity, system power consumption, spectrum efficiency, output amplitude and the like so as to meet the requirements of an FCC spectrum mask, and is particularly represented as a preferred choice of an ultra-wideband signal waveform, a modulation mode and a generation method. Commonly used ultra-wideband signal waveforms mainly include rectangular, triangular, half-cosine and gaussian ultra-wideband waveforms. The gaussian waveform has the highest spectral efficiency of 38%, but the circuit implementation is more complex; the triangular waveform frequency spectrum efficiency is 29.5%, and the circuit is relatively simple to realize. Common ultra-wideband modulation methods include on-off keying (OOK), phase keying (PSK), pulse Amplitude Modulation (PAM), and Pulse Position Modulation (PPM). The OOK modulation circuit has a simple structure and high transmission rate; PSK modulation has strong anti-noise capability and a complex transceiving circuit structure. The ultra-wideband signal generation method mainly comprises a pulse filtering and shaping technology, a multipath pulse edge synthesis technology and a voltage-controlled oscillation technology. A large number of inductance and capacitance are needed for filtering and shaping, and a large chip area is occupied; the synthesis of multi-path pulse edges requires precise control of time delay; the voltage-controlled oscillation technology requires higher reliability and faster oscillation starting speed. In order to cope with the influence caused by the process deviation, the power supply voltage, the working temperature and the compromise relationship, the increase of the tunability of the ultra-wideband transmitter is particularly important in the design process.
Disclosure of Invention
The invention aims to provide a multistage tunable ultra-wideband transmitter to realize the tunability of the transmitter.
The invention relates to a multistage tunable ultra-wideband transmitter, which comprises a narrow pulse generating circuit, a triangular envelope circuit, a voltage-controlled ring oscillation circuit, an output buffer circuit and an antenna which are sequentially connected by signals;
the narrow pulse generating circuit: the circuit comprises a clock signal processing unit, a data processing unit and a data processing unit, wherein the clock signal processing unit is used for processing a baseband data signal according to a clock signal to generate a differential extremely narrow pulse signal; adjusting the pulse width of the extremely narrow pulse signal according to the first control voltage;
the triangular envelope circuit: the narrow pulse signal is converted into a triangular pulse signal through integration;
the voltage-controlled ring oscillation circuit: the ultra-wideband signal generating circuit is used for starting oscillation in a complementary switch mode according to the triangular pulse signal to generate an ultra-wideband signal with adjustable frequency; adjusting the center frequency of the ultra-wideband signal according to the second control voltage;
an output buffer circuit: the ultra-wideband signal processing circuit is used for adjusting the spectrum amplitude of the ultra-wideband signal and outputting an ultra-wideband radio frequency signal which accords with the FCC spectrum standard; adjusting the amplitude of the ultra-wideband radio frequency signal according to a third control voltage;
the antenna is as follows: for transmitting the ultra-wideband radio frequency signal.
The narrow pulse generating circuit comprises a return-to-zero code conversion unit, a delay control unit, a first delay module, a second delay module, three exclusive-OR gates and an AND gate;
the first input end of the return-to-zero code conversion unit is connected with a baseband data signal, the second input end of the return-to-zero code conversion unit is connected with a clock signal, and the output end of the return-to-zero code conversion unit is divided into three branches; the first branch is connected to the first input end of the AND gate, the second branch is connected to the first input end of the first exclusive-OR gate after passing through the first delay module, and the third branch is connected to the second input end of the first exclusive-OR gate after passing through the second delay module; the output end of the first exclusive-OR gate is connected to the second input end of the AND gate;
the first input end of the second exclusive-OR gate is connected with power supply voltage, the second input end of the second exclusive-OR gate is connected with the output end of the AND gate, and the output end of the second exclusive-OR gate outputs an inverted signal of the extremely narrow pulse signal; the first input end of the third exclusive-OR gate is grounded with the output end and the second input end of the AND gate, and the output end outputs the in-phase signal of the extremely narrow pulse signal;
and the delay control unit adjusts the delay time of the second delay module according to the first control voltage.
The delay control unit comprises a first capacitor, two PMOS tubes and two NMOS tubes;
the source electrode of the first PMOS tube is connected with the power supply voltage, the common point of the grid electrode and the drain electrode and then connected with the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is grounded; the grid electrode of the second PMOS tube is connected with a first control voltage; the drain electrode of the first NMOS tube is connected with the control end of the second delay module, the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the source and the drain of the second NMOS tube are grounded;
one end of the first capacitor is connected with the grid electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
The adjustment amplitude of the pulse width of the extremely narrow pulse signal is nanosecond.
The voltage-controlled ring oscillation circuit comprises a bias circuit, two PMOS (P-channel metal oxide semiconductor) tubes, two NMOS (N-channel metal oxide semiconductor) tubes and N-1 inverters connected in series; wherein N is an odd number greater than 1;
the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded; the grid electrodes of the third PMOS tube and the third NMOS tube are connected with the N-1 inverters connected in series after being in a common point;
the inverted signal of the triangular pulse signal is connected with the grid electrode of the fourth PMOS tube;
the in-phase signal of the triangular pulse signal is connected with the grid electrode of the fourth NMOS tube;
and the biasing circuit regulates the dynamic charge and discharge current of the N-1 inverters connected in series according to a second control voltage.
The multistage tunable ultra-wideband transmitter has the advantages that the tunability function of adjusting the pulse width, the center frequency and the amplitude is realized, and the adverse effect of factors such as process deviation on the frequency can be dealt with.
Drawings
Fig. 1 is a schematic diagram of the structure of the ultra-wideband transmitter of the present invention.
Fig. 2 is a schematic structural diagram of a narrow pulse generating circuit according to the present invention.
Fig. 3 is a schematic diagram of the structure of the voltage-controlled ring oscillator circuit according to the present invention.
Fig. 4 is a time domain waveform diagram of an ultra-wideband radio frequency signal of the ultra-wideband transmitter according to the present invention under the TSMC 65nm process.
Fig. 5 is a waveform diagram of an ultra-wideband radio frequency signal spectrum of the ultra-wideband transmitter according to the invention under the TSMC 65nm process.
Reference numerals are as follows:
vctrl _ 1-first control voltage, vctrl _ 2-second control voltage, vctrl _ 3-third control voltage;
data-baseband Data signal, clk-clock signal, in-phase signal of P _ P-narrow pulse signal, anti-phase signal of P _ n-narrow pulse signal, in-phase signal of T _ P-triangular pulse signal, anti-phase signal of T _ n-triangular pulse signal, X-ultra wide band signal, Y-ultra wide band radio frequency signal;
XOR 1-a first XOR gate, XOR 2-a second XOR gate, XOR 3-a third XOR gate;
PM 1-a first PMOS tube, PM 2-a second PMOS tube, PM 3-a third PMOS tube and PM 4-a fourth PMOS tube;
NM 1-first NMOS transistor, NM 2-second NMOS transistor, NM 3-third NMOS transistor, NM 4-fourth NMOS transistor;
point A is the common point of the grid electrode and the drain electrode of the first PMOS tube, the source electrode of the second PMOS tube and the grid electrode of the first NMOS tube.
Detailed Description
As shown in fig. 1 to fig. 3, the multistage tunable ultra-wideband transmitter of the present invention has the characteristics of simple structure, strong stability, adjustable frequency spectrum, and low power consumption. The device comprises a narrow pulse generating circuit, a triangular envelope circuit, a voltage-controlled ring oscillation circuit, an output buffer circuit and an antenna which are sequentially connected through signals.
The narrow pulse generating circuit: the circuit is used for processing the baseband data signal according to the clock signal to generate a differential extremely narrow pulse signal. The pulse width of the extremely narrow pulse signal is adjusted according to the first control voltage.
The triangular envelope circuit: the narrow pulse signal is converted into a triangular pulse signal with excellent spectrum efficiency through integration.
The voltage-controlled ring oscillation circuit: and the ultra-wideband signal generating circuit is used for starting oscillation in a complementary switch mode according to the triangular pulse signal to generate an ultra-wideband signal with adjustable frequency. And adjusting the center frequency of the ultra-wideband signal according to the second control voltage, and up-converting the triangular pulse signal into an ultra-wideband radio frequency signal with the center frequency of 4 GHz.
An output buffer circuit: and the ultra-wideband signal processing module is used for adjusting the spectrum amplitude of the ultra-wideband signal and outputting the ultra-wideband radio-frequency signal which accords with the FCC spectrum standard. And adjusting the amplitude of the ultra-wideband radio frequency signal according to the third control voltage.
The antenna is as follows: for transmitting the ultra-wideband radio frequency signal.
The narrow pulse generating circuit comprises a return-to-zero code conversion unit, a delay control unit, a first delay module, a second delay module, three exclusive-OR gates and an AND gate.
The first input end of the return-to-zero code conversion unit is connected with a baseband data signal, the second input end of the return-to-zero code conversion unit is connected with a clock signal, and the output end of the return-to-zero code conversion unit is divided into three branches. The first branch circuit is connected to the first input end of the AND gate, the second branch circuit is connected to the first input end of the first exclusive-OR gate after passing through the first delay module, and the third branch circuit is connected to the second input end of the first exclusive-OR gate after passing through the second delay module. And the output end of the first exclusive-OR gate is connected to the second input end of the AND gate.
The first input end of the second exclusive-OR gate is connected with a power supply voltage, the second input end of the second exclusive-OR gate is connected with the output end of the AND gate, and the output end of the second exclusive-OR gate outputs an inverted signal of the extremely narrow pulse signal. And the first input end of the third exclusive-OR gate is grounded with the output end and the second input end of the AND gate, and the output end outputs the in-phase signal of the extremely narrow pulse signal.
And the delay control unit adjusts the delay time of the second delay module according to the first control voltage.
The delay control unit comprises a first capacitor, two PMOS tubes and two NMOS tubes.
The source electrode of the first PMOS tube is connected with the power supply voltage, the common point of the grid electrode and the drain electrode and then connected with the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is grounded. The grid electrode of the second PMOS tube is connected with a first control voltage. The drain electrode of the first NMOS tube is connected with the control end of the second delay module, the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube. And the source and the drain of the second NMOS tube are grounded.
One end of the first capacitor is connected with the grid electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
The adjustment amplitude of the pulse width of the extremely narrow pulse signal is nanosecond.
The voltage-controlled ring oscillation circuit comprises a bias circuit, two PMOS (P-channel metal oxide semiconductor) tubes, two NMOS (N-channel metal oxide semiconductor) tubes and N-1 inverters connected in series. Wherein N is an odd number greater than 1.
The power supply voltage is connected with a source electrode of a third PMOS tube, a drain electrode of the third PMOS tube is connected with a source electrode of a fourth PMOS tube, a drain electrode of the fourth PMOS tube is connected with a drain electrode of a fourth NMOS tube, a source electrode of the fourth NMOS tube is connected with a drain electrode of the third NMOS tube, and a source electrode of the third NMOS tube is grounded. And the grids of the third PMOS tube and the third NMOS tube are connected with the N-1 inverters connected in series after being in a common point.
And the inverted signal of the triangular pulse signal is connected with the grid electrode of the fourth PMOS tube.
And the in-phase signal of the triangular pulse signal is connected with the grid electrode of the fourth NMOS tube.
And the biasing circuit regulates the dynamic charge and discharge current of the N-1 inverters connected in series according to a second control voltage.
The output buffer circuit is of conventional construction.
The operating principle of the multistage tunable ultra-wideband transmitter is as follows:
the differential very narrow pulse signal is an OOK signal.
The baseband data signal and the clock signal are input to a return-to-zero code conversion unit, and the unit consists of a D trigger and an AND gate, so that the baseband data signal and the clock signal are synchronized, and return-to-zero of the baseband data signal is realized. The baseband data signals after return to zero are input into two paths of delay modules. The delay modules are all formed by cascading an even number of inverters, wherein the delay time of the second delay module is controlled by the delay control unit. The first delay module AND the second delay module generate a narrow pulse signal with the pulse width being the delay difference of the first exclusive-or gate AND the AND gate. And finally, respectively carrying out exclusive OR on the extremely narrow pulse signals and power supply voltage 1 and ground 0 to generate two paths of synchronous out-of-phase extremely narrow pulse signals.
The working principle of the delay control unit is as follows: the voltage of the point A is adjusted by changing the first control voltage, so that the conduction current of the first NMOS tube is controlled, the current charges and discharges the internal capacitor of the second NMOS tube, and the delay time of the second delay module is accurately controlled. The first PMOS tube connected with the diode is used as a resistance load to limit the grid voltage of the first NMOS tube and prevent the conduction current of the first NMOS tube from being overlarge, and the first capacitor is used as a blocking capacitor.
The triangular envelope circuit converts the extremely narrow pulse into a triangular pulse through integration, and the voltage-controlled ring oscillation circuit up-converts the triangular pulse into an ultra-wideband radio frequency signal.
And a third NMOS tube and a third PMOS tube of the voltage-controlled ring oscillation circuit form a first-stage inverter, the first-stage inverter is cascaded with N-1 inverters connected in series, wherein N is an odd number larger than 1. In the present embodiment, the number of stages N is set to 3. The fourth NMOS tube and the fourth PMOS tube are used as switching tubes, and the triangular pulse signals T _ p and T _ n are used as switching signals and are respectively and correspondingly connected to the grids of the two tubes, so that the voltage-controlled ring oscillation circuit only works in a short time, and the overall power consumption is effectively reduced. The second control voltage changes the dynamic charge-discharge current of the ring oscillator by controlling the bias circuit, so as to control the oscillation frequency.
The output buffer circuit can adjust the spectrum output swing of the ultra-wideband radio frequency signal through the third control voltage so as to meet the requirement of FCC spectrum mask.
The pulse width, center frequency, and output power amplitude of the ultra-wideband radio frequency signal may be adjusted by varying the control voltages Vctrl _1, vctrl _2, and Vctrl _3, respectively. The ultra-wideband radio frequency signal generated by the multistage tunable ultra-wideband transmitter has strong flexibility and stability, and can cope with the influences of process deviation, power supply voltage and working temperature on waveform and frequency.
In order to further verify the working performance of the ultra-wideband transmitter, the physical verification is carried out by the TSMC 65nm process, as shown in FIGS. 4 and 5. As can be seen from fig. 4, the pulse width of the ultra-wideband radio frequency signal is 1ns, the period is 4ns, and the corresponding data rate is 250Mbps. As can be seen from FIG. 5, the center frequency of the UWB RF signal is 4GHz, the-10 dB bandwidth is 3-5GHz, and the side lobe suppression ratio is 30dB. The triangular envelope circuit can effectively improve the frequency spectrum efficiency of the ultra-wideband radio frequency signal and enhance the suppression capability of the side lobe.
Various other modifications and changes may occur to those skilled in the art based on the foregoing teachings and concepts, and all such modifications and changes are intended to be included within the scope of the appended claims.
Claims (5)
1. A multistage tunable ultra-wideband transmitter is characterized by comprising a narrow pulse generating circuit, a triangular envelope circuit, a voltage-controlled ring oscillation circuit, an output buffer circuit and an antenna which are sequentially connected by signals;
the narrow pulse generating circuit: the circuit comprises a clock signal processing unit, a data processing unit and a data processing unit, wherein the clock signal processing unit is used for processing a baseband data signal according to a clock signal to generate a differential extremely narrow pulse signal; adjusting the pulse width of the extremely narrow pulse signal according to the first control voltage;
the triangular envelope circuit: the narrow pulse signal is converted into a triangular pulse signal through integration;
the voltage-controlled ring oscillation circuit: the ultra-wideband signal generating circuit is used for starting oscillation in a complementary switch mode according to the triangular pulse signal to generate an ultra-wideband signal with adjustable frequency; adjusting the center frequency of the ultra-wideband signal according to the second control voltage;
an output buffer circuit: the ultra-wideband signal processing circuit is used for adjusting the spectrum amplitude of the ultra-wideband signal and outputting an ultra-wideband radio frequency signal which accords with the FCC spectrum standard; adjusting the amplitude of the ultra-wideband radio frequency signal according to a third control voltage;
the antenna is as follows: for transmitting the ultra-wideband radio frequency signal.
2. The multi-stage tunable ultra-wideband transmitter of claim 1, wherein the narrow pulse generating circuit comprises a return-to-zero code conversion unit, a delay control unit, a first delay module, a second delay module, three exclusive or gates, and an and gate;
the first input end of the return-to-zero code conversion unit is connected with a baseband data signal, the second input end of the return-to-zero code conversion unit is connected with a clock signal, and the output end of the return-to-zero code conversion unit is divided into three branches; the first branch is connected to the first input end of the AND gate, the second branch is connected to the first input end of the first XOR gate after passing through the first delay module, and the third branch is connected to the second input end of the first XOR gate after passing through the second delay module; the output end of the first exclusive-OR gate is connected to the second input end of the AND gate;
the first input end of the second exclusive-OR gate is connected with power supply voltage, the second input end of the second exclusive-OR gate is connected with the output end of the AND gate, and the output end of the second exclusive-OR gate outputs an inverted signal of the extremely narrow pulse signal; the first input end of the third exclusive-OR gate is grounded with the output end and the second input end of the AND gate, and the output end outputs the in-phase signal of the extremely narrow pulse signal;
and the delay control unit adjusts the delay time of the second delay module according to the first control voltage.
3. The multi-stage tunable ultra-wideband transmitter of claim 2, wherein the delay control unit comprises a first capacitor, two PMOS transistors and two NMOS transistors;
the source electrode of the first PMOS tube is connected with the power supply voltage, the common point of the grid electrode and the drain electrode and then connected with the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is grounded; the grid electrode of the second PMOS tube is connected with a first control voltage; the drain electrode of the first NMOS tube is connected with the control end of the second delay module, the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the source and drain of the second NMOS tube are grounded;
one end of the first capacitor is connected with the grid electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
4. The multi-stage tunable ultra-wideband transmitter of claim 2, wherein the amplitude of the modulation of the pulse width of the ultra-narrow pulse signal is in the order of nanoseconds.
5. The multi-stage tunable ultra-wideband transmitter of claim 2, wherein the voltage-controlled ring oscillator circuit comprises a bias circuit, two PMOS transistors, two NMOS transistors and N-1 series-connected inverters; wherein N is an odd number greater than 1;
the source electrode of the third PMOS tube is connected with the source electrode of the fourth NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded; the grid electrodes of the third PMOS tube and the third NMOS tube are connected with the N-1 inverters connected in series after being in a common point;
the inverse signal of the triangular pulse signal is connected with the grid electrode of the fourth PMOS tube;
the in-phase signal of the triangular pulse signal is connected with the grid electrode of the fourth NMOS tube;
and the biasing circuit regulates the dynamic charge and discharge current of the N-1 inverters connected in series according to a second control voltage.
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