CN115276626A - PMOS drive circuit with gate voltage clamping protection function and enable translation circuit - Google Patents

Abstract

The invention provides a PMOS driving circuit and an enabling translation circuit with a gate voltage clamping protection function. In the PMOS driving circuit, a first end of a first clamping branch is connected to a power supply end, and a second end is connected to a two-stage open loop the output node of the first stage of the comparator circuit; the first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the output node of the second stage of the two-stage open-loop comparator circuit; the first end of the first discharge branch The terminal is connected to the output node of the second stage, and the second terminal of the first discharge branch is grounded; the enhanced pull-down driving clamp circuit is connected to the output node of the first stage and the output node of the second stage; An inverter is set between the two inverters, the input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter is connected to the second input terminal. Large-sized PMOS transistors that require gate clamping. The present invention also provides an enabling translation circuit for realizing the gate voltage clamping protection function.

Description

PMOS drive circuit with gate voltage clamp protection function and enable translation circuit

technical field

The invention relates to the technical field of integrated circuits, in particular to a PMOS drive circuit and an enabling translation circuit with a gate voltage clamping protection function.

Background technique

PMOS switching devices are widely used in integrated circuit drive chips. In some existing integrated circuit processes, the common characteristics of this PMOS switching device are as follows: relatively large tube size, relatively small internal resistance, gate and source The withstand voltage between them is limited, and the withstand voltage between the source and drain is relatively high, so it is suitable for various switch controls. Therefore, the driving circuit using this kind of PMOS switching device is required to have strong driving capability and output characteristics with clamping function. If this requirement is not met, the reliability of the PMOS switching device will be reduced, and then the chip will be affected. quality.

Contents of the invention

The first object of the present invention is to provide a PMOS drive circuit with a strong drive capability and a gate voltage clamping protection function.

The second object of the present invention is to provide another PMOS drive circuit with a strong drive capability and a gate voltage clamping protection function.

The third object of the present invention is to provide an enable translation circuit with gate voltage clamping protection function for enabling control of internal modules of the chip.

In order to achieve the first purpose above, the present invention provides a PMOS drive circuit with a gate voltage clamping protection function, which includes a two-stage open-loop comparator circuit, which also includes: a first clamping branch, a second A clamping branch, a first discharge branch, and an enhanced pull-down drive clamping circuit; the first end of the first clamping branch is connected to the power supply terminal, and the second end is connected to the first-stage output node of the two-stage open-loop comparator circuit; The first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit; the first end of the first discharge branch is connected to the second-stage output node, and the first The second end of the discharge branch is grounded; the enhanced pull-down drive clamp circuit is connected to the output node of the first stage and the output node of the second stage; an inversion is provided between the first input end and the second input end of the two-stage open-loop comparator The input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter is connected to the second input terminal; when the first input terminal receives a low-level signal, the first clamping branch clamps the output node of the first stage Voltage, the second-stage output node outputs the first driving voltage to the gate of the external PMOS transistor; when the first input terminal receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamp circuit control the gate of the external PMOS transistor The capacitor is discharged to a second preset value, and the second clamping branch clamps the voltage of the output node of the second stage to be the second driving voltage.

It can be seen from the above scheme that the gate-source voltages of all PMOS transistors in the present invention are controlled within an acceptable safe range, and the gates of the PMOS transistors are protected by the first clamping circuit and the second clamping circuit provided to enhance the pull-down drive While the clamping circuit improves the load capacitance driving capability of the second-stage output node, it drives the second clamping circuit to clamp the gate voltage of the external PMOS transistor, so that the gate-source voltage of the external PMOS transistor is relatively fixed, and can drive large-sized PMOS switches device.

A further solution is that the enhanced pull-down drive clamping circuit includes a second discharge branch and a bias branch for enhanced driving; the first end of the second discharge branch is connected to the second-stage output node, and the second end is grounded; the enhanced driving The bias branch is connected to the first-stage output node, the second-stage output node, and the second discharge branch; when the first input end receives a high-level signal, the enhanced bias branch is driven to control the first discharge branch and the second discharge branch. The discharge branch discharges the gate capacitance of the external PMOS transistor to a second preset value.

A further solution is that the first discharge branch includes a first NMOS transistor and a fifth NMOS transistor, the second clamping branch includes a first PMOS transistor and a second NMOS transistor; the driving enhanced bias branch includes a third PMOS transistor , the first clamping component, the third NMOS transistor, and the fourth NMOS transistor; the drain of the first NMOS transistor is connected to the output node of the second stage, and the gate of the first NMOS transistor is connected to the input terminal of the inverter and the first input terminal , the source of the first NMOS transistor is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to a two-stage open-loop comparator circuit, and the gate of the fifth NMOS transistor is grounded; the source of the first PMOS transistor is connected to The second output node of the second stage and the second end of the second clamping branch, the gate of the first PMOS transistor is connected to the enhanced bias branch, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor; The gate of the second NMOS transistor is connected to the input terminal of the inverter and the first input terminal, the source of the second NMOS transistor is grounded; the source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first stage Output node, the drain of the third PMOS transistor is connected to the gate of the second PMOS transistor; the first end of the first clamping component is connected to the power supply terminal, and the second end is connected to the third PMOS transistor; the gate of the third NMOS transistor Connect the input end of the inverter and the first input end, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the fourth NMOS transistor The gate is connected to the two-stage open-loop comparator circuit, and the source of the fourth NMOS transistor is grounded; the fourth NMOS transistor is in a conduction state.

A further solution is that the first clamping component includes a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor connected in series; the source of the fourth PMOS transistor is connected to the power supply terminal, and the gate of the fourth PMOS transistor is connected to the fourth PMOS transistor. The drain of the PMOS tube; the source of the fifth PMOS tube is connected to the drain of the fourth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube; the source of the sixth PMOS tube is connected to the fifth PMOS tube The drain of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is connected to the gate of the first PMOS transistor and the drain of the third NMOS transistor.

A further solution is that the second clamping branch includes a second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the second PMOS transistor is The pole is connected to the output node of the second stage and the source of the first PMOS transistor.

A further solution is that the two-stage open-loop comparator circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a current source The source of the seventh PMOS transistor is connected to the power supply terminal, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the eighth NMOS transistor The gate of the eighth NMOS transistor is connected to the first input terminal and the input terminal of the inverter, the source of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor; the source of the eighth PMOS transistor is connected to the power supply terminal, and the source of the eighth NMOS transistor is connected to the power supply terminal. The gates of the eight PMOS transistors are connected to the gates of the seventh PMOS transistors, the drains of the eighth PMOS transistors are connected to the drains of the ninth NMOS transistors and the gates of the ninth PMOS transistors; the gates of the ninth NMOS transistors are connected to the inverter The output terminal of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor; the first stage output node is set at the drain of the eighth PMOS transistor; the second stage output node is set at the drain of the ninth PMOS transistor; The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the seventh NMOS transistor is grounded; the drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded; The gate of the sixth NMOS transistor is connected to the first discharge branch and the enhanced pull-down drive clamping circuit; one end of the current source is connected to the drain and gate of the sixth NMOS transistor, the other end of the current source is grounded, and the current direction of the current source is It flows into the drain of the sixth NMOS transistor; the first end of the first clamping branch is connected to the power supply terminal, and the second end of the first clamping branch is connected to the gate of the ninth PMOS transistor.

A further solution is that the first clamping branch includes a second clamping component.

A further solution is that the second clamping component includes a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; the source of the tenth PMOS transistor is connected to the power supply terminal, and the gate of the tenth PMOS transistor is connected to the tenth PMOS transistor. The drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor; the source of the eleventh PMOS transistor is connected to the drain of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor is connected to the tenth PMOS transistor. The drain of the first PMOS transistor, the drain of the eleventh PMOS transistor is connected to the source of the twelve PMOS transistors; the source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the gate of the twelfth PMOS transistor The drain of the twelfth PMOS transistor is connected, and the drain of the twelfth PMOS transistor is connected to the gate of the ninth PMOS transistor.

In order to achieve the above-mentioned second purpose, the present invention provides a PMOS drive circuit with a gate voltage clamping protection function, which includes a two-stage open-loop comparator circuit, which also includes: a second clamping branch, a first Discharge branch, enhanced pull-down drive clamping circuit; the first end of the first discharge branch is connected to the power supply terminal, and the second end is grounded; the first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the two-stage switch The second-stage output node of the ring comparator circuit; the first end of the first discharge branch is connected to the second-stage output node, and the second end of the first discharge branch is grounded; the driving pull-down driver clamping circuit is connected to the first-stage output node and the second-stage output node; an inverter is connected between the first input end and the second input end of the two-stage open-loop comparator, and the input end of the inverter is connected to the first input end, and the output end of the inverter is connected to the second Two input terminals; when the first input terminal receives a low-level signal, the second-level output node outputs the first driving voltage to the gate of the external PMOS transistor; when the first input terminal receives a high-level signal, the second-level output node and The enhanced pull-down driving clamping circuit controls the discharge of the gate capacitance of the external PMOS transistor to a second preset value, and the second clamping branch clamps the voltage of the output node of the second stage to the second driving voltage.

It can be seen from the above solution that a large-sized PMOS switching device requiring gate clamping can be driven.

In order to achieve the above third objective, the present invention provides an enabling translation circuit with a gate voltage clamping protection function, which includes a two-stage open-loop comparator circuit, which also includes: a first clamping branch; The first end of a clamping branch is connected to the power supply end, and the second end is connected to the first-stage output node of the two-stage open-loop comparator circuit; between the first input end and the second input end of the two-stage open-loop comparator An inverter is connected, the input end of the inverter is connected to the first input end, and the output end of the inverter is connected to the second input end; when the first input end receives a low-level signal, the first clamping branch clamps the first The voltage at the output node of the stage.

It can be seen from the above scheme that a low-voltage to high-voltage enabling translation circuit structure with clamp control can be realized, as the enabling control of the functional modules inside the chip, and the enabling control of the protection function module. The gate voltage of the PMOS transistor makes the enabling control The gate-source voltage of the PMOS transistor remains stable, increasing reliability.

Description of drawings

FIG. 1 is a circuit schematic diagram of a two-stage open-loop comparator circuit in the prior art.

FIG. 2 is a schematic circuit diagram of the PMOS drive circuit with gate voltage clamp protection function connected to an external PMOS transistor in the embodiment of the PMOS drive circuit with gate voltage clamp protection function in the present invention.

FIG. 3 is a schematic diagram of internal node waveforms in FIG. 2 .

FIG. 4 is a schematic circuit diagram of the enabling translation circuit with the gate voltage clamping protection function connected to the internal functional modules of the chip in the embodiment of the enabling translation circuit with the gate voltage clamping protection function of the present invention.

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Detailed ways

The PMOS driving circuit with the gate voltage clamping protection function of the present invention can control the gate-source voltage of the PMOS transistor within a safe range that it can withstand through a reasonable design of the clamping circuit, and realizes driving a larger voltage through double pull-down driving. size of the PMOS switching device.

The gate voltage clamping protection function is determined by the manufacturing process used by the chip and the designer's use of this type of PMOS device. The characteristics of this type of PMOS device are as follows: the gate-source voltage when the PMOS is turned on is relatively low, and the typical value is 5V. , and the withstand voltage between the drain and source is relatively high, such as 25V, 40V, 100V, or even higher withstand voltage. However, this type of PMOS device has an obvious advantage. Compared with ordinary PMOS devices, under the same on-current driving condition, the internal resistance of the tube is relatively low, so this type of device is especially suitable for active control switches. Power management, battery management, motor drive, automotive drive chips and other electronic products are widely used. If this type of PMOS device needs to be used inside the chip, it is necessary to perform voltage clamping protection on its gate-source voltage. The gate protection clamping voltage realization principle of the present invention comes from the current voltage I of the MOS when working in the saturation region. /V characteristic, its expression is as follows:

Among them, the up, Cox and Vth parameters are determined by the manufacturing process itself, and can be obtained as follows:

It can be seen from the above formula that if the width-to-length ratio W/L of the MOS is fixed and the bias current Id is determined, the Vgs voltage of the MOS transistor is a certain value; changing the width-to-length ratio W/L of the PMOS or the bias current or both If both are changed together, the Vgs voltage of the PMOS will be changed. In the present invention, the clamping control of the PMOS gate voltage is based on the Vgs voltage drop of one PMOS or the voltage drop generated by multiple PMOSs connected in series.

Embodiment of PMOS drive circuit with gate voltage clamp protection function:

Referring to Fig. 1, the two-stage open-loop comparator circuit in the prior art includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7, eighth NMOS transistor N8, ninth NMOS transistor N9, current source; the source of the seventh PMOS transistor P7 is connected to the power supply terminal VDD, the gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8 and the seventh The drain of the PMOS transistor P7, the drain of the seventh PMOS transistor P7 is connected to the drain of the eighth NMOS transistor N8; the gate of the eighth NMOS transistor N8 is connected to the INN terminal, and the source of the eighth NMOS transistor N8 is connected to the seventh NMOS transistor The drain of N7; the source of the eighth PMOS transistor P8 is connected to the power supply terminal VDD, the gate of the eighth PMOS transistor P8 is connected to the gate of the seventh PMOS transistor P7, and the drain of the eighth PMOS transistor P8 is connected to the ninth NMOS transistor N9 The drain of the ninth PMOS transistor P9 and the gate of the ninth NMOS transistor P9; the gate of the ninth NMOS transistor N9 is connected to the IPN terminal, the source of the ninth NMOS transistor N9 is connected to the drain of the seventh NMOS transistor N7; the gate of the seventh NMOS transistor N7 The pole is connected to the gate of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7 is grounded; the drain of the sixth NMOS transistor N6 is connected to the gate of the sixth NMOS transistor N6, and the source of the sixth NMOS transistor N6 is grounded; The drain of the fifth NMOS transistor N5 is connected to the discharge branch, the gate of the fifth NMOS transistor N5 is connected to the gate of the sixth NMOS transistor N6, and the source of the fifth NMOS transistor N5 is grounded; the output node of the first stage is set on the eighth PMOS The drain of the tube P8; the second-stage output node (OUT) is set on the drain of the ninth PMOS transistor P9; one end of the current source is connected to the drain and the gate of the sixth NMOS transistor N6, and the other end of the current source is grounded, and the current The current direction of the source is to flow into the drain of the sixth NMOS transistor N6.

The output characteristics of the above-mentioned two-stage open-loop comparator circuit in the prior art are: when the voltage at the input IPN terminal is greater than the voltage at the IN terminal, the output node of the second stage, that is, the OUT node, outputs a high level; when the voltage at the input INP terminal is less than the voltage at the INN terminal , the output node of the second stage, that is, the OUT node outputs a low level. Due to the limitations of the performance parameters of the architecture itself, for example, when the pull-down current of the second-stage output node is fixed, the driving capacitive load capacity is limited, and the output low level of the second-stage output node is the power ground, which obviously cannot be used to drive the type described in the present invention. large size switching PMOS devices.

The PMOS drive circuit 1 with the gate voltage clamping protection function of the present embodiment is realized based on the above-mentioned two-stage open-loop comparator circuit of the prior art. Referring to FIG. 2 , it includes a two-stage open-loop comparator circuit 11, a first clamp A branch 12 , a second clamping branch 13 , a first discharging branch 14 , and an enhanced pull-down drive clamping circuit 15 . The two-stage open-loop comparator circuit is respectively connected to the first clamping branch 12, the second clamping branch 13, the first discharge branch 14, and the enhanced pull-down drive clamping circuit 15, and the second clamping branch 13 is connected to the first The discharging branch 14 and the enhanced pull-down drive clamping circuit 15 are connected to the second clamping branch 13 and the first discharging branch 14 . Different from the two-stage open-loop comparator circuit in the prior art, in this embodiment, the fifth NMOS transistor N5 and the first NMOS transistor N1 form the first discharge branch 14 .

An inverter INV is arranged between the first input terminal IN and the second input terminal INB of the two-stage open-loop comparator, the input terminal of the inverter INV is connected to the first input terminal IN, and the output terminal of the inverter INV is connected to the second input terminal IN. Input INB. Therefore, the input of the two-stage open-loop comparator is directly set as an input signal with complementary levels, the first input terminal IN receives the high-level or low-level signal output by the digital circuit inside the chip, and the differential pair of the eighth NMOS transistor Only one of N8 and the ninth NMOS transistor N9 is in a conduction state when each level is input.

The first end of the first clamping branch 12 is connected to the power supply terminal VDD, and the second end is connected to the first output node of the two-stage open-loop comparator circuit. The first clamping branch 12 includes a first clamping component. In this embodiment, the first clamping component includes a tenth PMOS transistor P10, an eleventh PMOS transistor P11, and a twelfth PMOS transistor P12. The source of the tenth PMOS transistor P10 is connected to the power terminal, the gate of the tenth PMOS transistor P10 is connected to the drain of the tenth PMOS transistor P10 , and the drain of the tenth PMOS transistor P10 is connected to the source of the eleventh PMOS transistor P11 . The source of the eleventh PMOS transistor P11 is connected to the drain of the tenth PMOS transistor P10, the gate of the eleventh PMOS transistor P11 is connected to the drain of the eleventh PMOS transistor P11, and the drain of the eleventh PMOS transistor P11 is connected to the tenth PMOS transistor P11. The source of the second PMOS transistor. The source of the twelfth PMOS transistor P12 is connected to the drain of the eleventh PMOS transistor P11, the gate of the twelfth PMOS transistor P12 is connected to the drain of the twelfth PMOS transistor P12, and the drain of the twelfth PMOS transistor P12 is connected to The gate of the ninth PMOS transistor P9.

One end of the first discharge branch 14 is connected to the power supply terminal VDD, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit 11 . The first discharge branch 14 includes a first NMOS transistor N1 and a fifth NMOS transistor. The drain of the first NMOS transistor N1 is connected to the output node of the second stage, the gate of the first NMOS transistor N1 is connected to the input terminal of the inverter INV and the first input terminal IN, and the source of the first NMOS transistor N1 is connected to the fifth NMOS drain of tube N5.

The first end of the second clamping branch 13 is connected to the power supply terminal VDD, and the second end is connected to the second-stage output node. The second clamping branch 13 includes a second clamping component. The second clamping component in this embodiment includes a second PMOS transistor P2, the source of the second PMOS transistor P2 is connected to the power supply terminal, and the gate of the second PMOS transistor P2 The drain of the second PMOS transistor P2 is connected, and the drain of the second PMOS transistor P2 is connected to the output node of the second stage and the source of the first PMOS transistor P1.

The enhanced pull-down drive clamping circuit 15 is connected to the output node of the first stage and the output node of the second stage, including a second discharge branch 151 and a bias branch 152 with enhanced drive, and the bias branch 152 with enhanced drive is connected to the second discharge branch Road 151.

The first end of the second discharge branch 151 is connected to the second-stage output node, and the second end is grounded. The second discharge branch 151 includes a first PMOS transistor P1 and a second NMOS transistor N2, the source of the first PMOS transistor P1 is connected to the output node of the second stage and the second end of the second clamping branch 13, the first PMOS transistor The gate of P1 is connected to the enhanced pull-down drive clamping circuit 15, and the drain of the first PMOS transistor P1 is connected to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to the input terminal of the inverter INV and the first input terminal IN, and the source of the second NMOS transistor N2 is grounded.

The driving enhanced bias branch 152 is connected to the first-stage output node, the second-stage output node, and the second discharge branch 151 . The bias circuit 152 for driving the enhancement branch includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, and a fourth NMOS transistor N4. The source of the third PMOS transistor P3 is connected to the power supply terminal, the gate of the third PMOS transistor P3 is connected to the output node of the first stage, and the drain of the third PMOS transistor P3 is connected to the gate of the second PMOS transistor P2. The source of the fourth PMOS transistor P4 is connected to the power supply terminal, and the gate of the fourth PMOS transistor P4 is connected to the drain of the fourth PMOS transistor P4. The source of the fifth PMOS transistor P5 is connected to the drain of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5 is connected to the drain of the fifth PMOS transistor P5. The source of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6 is connected to the drain of the sixth PMOS transistor P6, and the drain of the sixth PMOS transistor P6 is connected to the first PMOS transistor P1 and the drain of the third NMOS transistor N3. The gate of the third NMOS transistor N3 is connected to the input terminal of the inverter INV and the first input terminal IN, and the source of the third NMOS transistor N3 is connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3, the gate of the fourth NMOS transistor N4 is connected to the gate of the sixth NMOS transistor N6 in the two-stage open-loop comparator circuit, and the gate of the fourth NMOS transistor N4 Source ground. The fourth NMOS transistor N4 is turned on.

Referring to Fig. 3, when the first input terminal IN is at low level, the second input terminal INB is at high level, at this time the ninth NMOS transistor N9 is turned on, the first stage output node is at low level, and the second stage output node The first driving voltage is the voltage of the power supply terminal VDD. For ease of description, the external PMOS transistor P0 that needs to be driven by the PMOS drive circuit of this embodiment is set in FIG. 2. The external PMOS transistor P0 is an active switch large-size PMOS device. The gate of the PMOS transistor P0 is connected to the second-stage output node, and the drain of the external PMOS transistor P0 is connected to the external PAD. The first clamping branch 12 clamps the voltage of the output node of the first stage so that the voltage difference between the voltage of this node and the power supply terminal VDD is a relatively fixed voltage drop, and clamps the gate voltage of the ninth PMOS transistor P9 to prevent There is a situation that the power supply terminal VDD increases, so that the gate-source voltage of the ninth PMOS transistor P9 exceeds the withstand voltage value and is damaged. It can be understood that replacing the tenth PMOS transistor P10, the eleventh PMOS transistor P11, and the twelfth PMOS transistor P12 with clamping diodes can play the same role, but the clamping diodes add a layer of photomask in the manufacturing process of the chip , making the cost increase. By connecting multiple PMOS transistors in series, that is, the tenth PMOS transistor P10 , the eleventh PMOS transistor P11 and the twelfth PMOS transistor P12 can also reduce the current of the first clamping branch 12 .

When the first input terminal IN is at a high level, the second input terminal INB is at a low level, at this time the ninth NMOS transistor N9 is turned off, and the output node of the first stage is at a high level. At the same time, the first NMOS transistor N1 of the first discharge branch 14 is turned on, and the first discharge branch 14 can start to work. In the enhanced pull-down drive clamping circuit 15, the second NMOS transistor N2 is turned on, and the third NMOS transistor N3 is turned on. The first-stage output node in the enhanced bias branch 152 turns off the third PMOS transistor P3, at this time, the fixed voltage drop of the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 is subtracted from the power supply terminal VDD The obtained low level turns on the first PMOS transistor P1, so that the second discharge branch 152 can start to work. Since the first input terminal IN is at a low level, the second-stage output node charges the gate capacitance of the external PMOS transistor P0 to the voltage value of the power supply terminal VDD, and at this time the gate capacitance starts to pass through the voltage value of the power supply terminal VDD. The first discharge branch 14 and the second discharge branch 151 are discharged to a second preset value. The second preset value is the gate clamp voltage value required by the external PMOS transistor P0. In this embodiment, through the double pull-down drive control of the first discharge branch and the enhanced pull-down drive circuit, the second stage The voltage value of the output node is clamped at the voltage value of the power supply terminal VDD minus the gate-source voltage of the second PMOS transistor P2, so that the gate voltage of the external PMOS transistor P0 is clamped at the second driving voltage, which is the power supply The gate-source voltage of the second PMOS transistor P2 is subtracted from the voltage value of the terminal VDD, so that the external PMOS transistor P0 works in the safe range of the gate-source voltage, and will not be damaged due to the increase of the voltage value of the power supply terminal VDD, and the first The discharge branch 14 and the second discharge branch 151 enable the output node of the second stage to be driven by double pull-down, so that a larger-sized PMOS switching device can be driven. It should be noted that in the circuit design, it is necessary to ensure that the voltage of the power supply terminal VDD-the gate-source voltage of the second PMOS transistor P2=the gate voltage of the first PMOS transistor P1+the threshold voltage (Vth) of the first PMOS transistor P1, At this time, the gate-source clamping voltage of the external PMOS transistor P0 is mainly determined by the voltage drop of the second PMOS transistor P2, so that the gate voltage of the external PMOS transistor P0 is clamped at the voltage of the power supply terminal VDD-the gate-source voltage of the second PMOS transistor P2 Voltage. The gate voltage of the first PMOS transistor P1 is determined by the sum of gate-source voltages of the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6. It can be understood that the second PMOS transistor P2 of the second clamping branch, and the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 in the enhanced pull-down drive clamping circuit 15 can be replaced by equal-voltage down the clamping diode.

In practical applications, the PMOS drive circuit 1 with the gate voltage clamping protection function does not need to set the first clamping branch 12, and can still realize the pull-down drive of the second-stage output point to drive the large-sized PMOS switching device, but it cannot protect The gate of the ninth PMOS transistor P9.

Embodiment of enabling translation circuit with gate voltage clamping protection function:

Different from the above-mentioned embodiments, this embodiment is not used for active switching large-size PMOS devices, but used for other functional modules (such as LDO module and current bias module) inside the chip. These module applications usually have an EN_CTRL enable control signal. In order to meet the design requirements of low power consumption, it is inevitable to apply small-sized PMOS devices that need gate clamp protection as switching devices, and the EN_CTRL enable control signal is usually Digital modules derived from low-voltage power domains are used to drive functional modules in high-voltage power domains (for example, the low-voltage current domain is 5V and below, and the high-voltage current domain is between 5V and 100V), which requires a clamp output Low voltage to high voltage enable translation circuit to realize logic conversion.

Referring to Fig. 4, the low-voltage to high-voltage enabling control translation point circuit 2 with gate voltage clamping protection function of this embodiment includes a two-stage open-loop comparator circuit 21 and a first clamping branch 22. The connection relationship between the loop comparator circuit 21 and the first clamping branch 22 and the first clamping branch 22 are the same as those of the above-mentioned first embodiment, and the two-stage open-loop comparator circuit 21 of this embodiment is the same as that of the above-mentioned first embodiment The difference between the two-stage open-loop comparator circuit 11 is that the second-stage output node is not provided, that is, the ninth PMOS transistor and the fifth NMOS transistor in the above-mentioned first embodiment are not provided. The first input end is EN_IN, which receives the enable control signal inside the chip, and the first-stage output node is the EN_CTRL node.

For ease of description, an internal functional module 23 is also provided in FIG. 4 . The internal functional module 23 may be a module such as an LDO module or a current bias module with an enabling control PMOS transistor P13. In this embodiment, it is an LDO module. When the enable control signal received by the first input terminal EN_IN is a low level in the low-voltage power supply domain, the EN_CTRL node outputs a low level with voltage clamping, enabling the control of the PMOS transistor P13 to be turned on, and setting the high impedance node of the LDO module to high . When the LDO module needs to work, the enable control signal received by the first input terminal EN_IN becomes a high level in the low-voltage power supply domain, and the output of the EN_CTRL node is a high level in the high-voltage power supply domain, enabling the control of the PMOS transistor P13 to be turned on and off, thereby Does not affect internal module work. In addition, when the enable control signal received by the first input terminal EN_IN changes, the output waveform of the EN_CTRL node can be roughly consistent with the waveform of the OUT node in Figure 2 of the present invention, and the voltage drop between the relative power supply terminal VDD is also the first The sum of gate-source voltages of the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor.

To sum up, in the enabling translation circuit with gate voltage clamping protection of the present invention, the gate-source voltages of all the PMOS transistors inside can be controlled within a tolerable voltage range, and the setting of the first clamping circuit can be Clamp the first-stage output node of the two-stage open-loop comparator circuit, so that it can be used for the enable control of the internal module of the chip with the enable control PMOS transistor, ensuring the reliability of the internal module of the chip. Combining the second clamping circuit, the first discharge branch, and the enhanced pull-down drive clamping circuit on the basis of the first clamping circuit can have strong driving capability and output characteristics with clamping, so that it can drive large-sized PMOS switch device.

Claims (10)

1. A kind of PMOS drive circuit with gate voltage clamp protection function, comprises two-stage open-loop comparator circuit, is characterized in that, also comprises: The first clamping branch, the second clamping branch, the first discharging branch, and the enhanced pull-down drive clamping circuit; The first end of the first clamping branch is connected to the power supply terminal, and the second end is connected to the first-stage output node of the two-stage open-loop comparator circuit; The first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit; The first end of the first discharge branch is connected to the second-stage output node, and the second end of the first discharge branch is grounded; The enhanced pull-down drive clamping circuit is connected to the first-stage output node and the second-stage output node; An inverter is arranged between the first input terminal of the two-stage open-loop comparator and the second input terminal, the input terminal of the inverter is connected to the first input terminal, and the inverter The output terminal is connected to the second input terminal; When the first input terminal receives a low-level signal, the first clamping branch clamps the voltage of the first-stage output node, and the second-stage output node outputs the first driving voltage to the gate of the external PMOS transistor. pole; When the first input terminal receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamp circuit control the discharge of the gate capacitance of the external PMOS transistor to a second preset value, and the second clamp The bit branch clamps the voltage of the second-stage output node to be the second driving voltage. 2. the PMOS drive circuit with gate voltage clamp protection function as claimed in claim 1, is characterized in that: The enhanced pull-down drive clamping circuit includes a second discharge branch and a bias branch for enhanced driving; The first end of the second discharge branch is connected to the second-stage output node, and the second end is grounded; The drive-enhanced bias branch is connected to the first-stage output node, the second-stage output node, and the second discharge branch; When the first input terminal receives a high-level signal, the driving enhanced bias branch controls the first discharge branch and the second discharge branch to discharge the gate capacitance of the external PMOS transistor to the second preset value. 3. the PMOS drive circuit with gate voltage clamp protection function as claimed in claim 2, is characterized in that: The first discharge branch includes a first NMOS transistor and a fifth NMOS transistor, the second clamping branch includes a first PMOS transistor and a second NMOS transistor; the drive-enhanced bias branch includes a third PMOS transistor tube, the first clamping component, the third NMOS tube, and the fourth NMOS tube; The drain of the first NMOS transistor is connected to the second-stage output node, the gate of the first NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the first NMOS transistor The source is connected to the drain of the fifth NMOS transistor; The gate of the fifth NMOS transistor is connected to the two-stage open-loop comparator circuit, and the gate of the fifth NMOS transistor is grounded; The source of the first PMOS transistor is connected to the second-stage output node and the second end of the second clamping branch, and the gate of the first PMOS transistor is connected to the bias branch of the driving enhancement , the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor; The gate of the second NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the source of the second NMOS transistor is grounded; The source of the third PMOS transistor is connected to the power supply terminal, the gate of the third PMOS transistor is connected to the first-stage output node, and the drain of the third PMOS transistor is connected to the second PMOS transistor. grid; The first end of the first clamping component is connected to the power supply end, and the second end is connected to the third PMOS transistor; The gate of the third NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the two-stage open-loop comparator circuit, and the source of the fourth NMOS transistor is grounded ; The fourth NMOS transistor is in a conduction state. 4. the PMOS drive circuit with gate voltage clamp protection function as claimed in claim 3, is characterized in that: The first clamping component includes a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor connected in series; The source of the fourth PMOS transistor is connected to the power supply terminal, and the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor; The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor; The source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is connected to The gate of the first PMOS transistor and the drain of the third NMOS transistor. 5. the PMOS drive circuit with gate voltage clamp protection function as claimed in claim 4, is characterized in that: The second clamping branch includes a second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, and the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor. The drain of the second PMOS transistor is connected to the output node of the second stage and the source of the first PMOS transistor. 6. The PMOS drive circuit with gate voltage clamp protection function as claimed in any one of claims 1 to 5, characterized in that: The two-stage open-loop comparator circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a current source; The source of the seventh PMOS transistor is connected to the power supply terminal, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh PMOS transistor, and the seventh PMOS transistor The drain of the transistor is connected to the drain of the eighth NMOS transistor; The gate of the eighth NMOS transistor is connected to the first input terminal and the input terminal of the inverter, and the source of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor; The source of the eighth PMOS transistor is connected to the power supply terminal, the gate of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the drain of the eighth PMOS transistor is connected to the ninth NMOS transistor. the drain of the transistor and the gate of the ninth PMOS transistor; The gate of the ninth NMOS transistor is connected to the output terminal of the inverter, and the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor; The first stage output node is set at the drain of the eighth PMOS transistor; the second stage output node is set at the drain of the ninth PMOS transistor; The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the seventh NMOS transistor is grounded; The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded; The gate of the sixth NMOS transistor is connected to the first discharge branch and the enhanced pull-down drive clamping circuit; One end of the current source is connected to the drain and gate of the sixth NMOS transistor, the other end of the current source is grounded, and the current direction of the current source is to flow into the drain of the sixth NMOS transistor; A first end of the first clamping branch is connected to the power supply terminal, and a second end of the first clamping branch is connected to the gate of the ninth PMOS transistor. 7. The PMOS drive circuit with gate voltage clamp protection function as claimed in claim 6, characterized in that: The first clamping branch includes a second clamping assembly. 8. The PMOS drive circuit with gate voltage clamp protection function as claimed in claim 7, characterized in that: The second clamping component includes a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; The source of the tenth PMOS transistor is connected to the power supply terminal, the gate of the tenth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the eleventh PMOS transistor. The source of the PMOS tube; The source of the eleventh PMOS transistor is connected to the drain of the tenth PMOS transistor, the gate of the eleventh PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the eleventh PMOS transistor The drain is connected to the source of the twelve PMOS transistors; The source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, the gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor, and the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor. The drain of the transistor is connected to the gate of the ninth PMOS transistor. 9. A PMOS drive circuit with grid voltage clamping protection function, comprising a two-stage open-loop comparator circuit, is characterized in that, also includes: The second clamping branch, the first discharging branch, and the enhanced pull-down drive clamping circuit; The first end of the first discharge branch is connected to the power supply end, and the second end is grounded; The first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit; The first end of the first discharge branch is connected to the second-stage output node, and the second end of the first discharge branch is grounded; The drive pull-down drive clamp circuit is connected to the first-stage output node and the second-stage output node; An inverter is connected between the first input terminal and the second input terminal of the two-stage open-loop comparator, the input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter connected to the second input terminal; When the first input terminal receives a low-level signal, the second-stage output node outputs a first driving voltage to the gate of an external PMOS transistor; When the first input terminal receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamp circuit control the discharge of the gate capacitance of the external PMOS transistor to a second preset value, and the second clamp The bit branch clamps the voltage of the second-stage output node to be the second driving voltage. 10. An enabling translation circuit with a gate voltage clamping protection function, comprising a two-stage open-loop comparator circuit, characterized in that it also includes: the first clamping branch; The first end of the first clamping branch is connected to the power supply terminal, and the second end is connected to the first-stage output node of the two-stage open-loop comparator circuit; An inverter is connected between the first input terminal and the second input terminal of the two-stage open-loop comparator, the input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter connected to the second input terminal; When the first input terminal receives a low-level signal, the first clamping branch clamps the voltage of the first-stage output node.

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