CN115274847A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate, the substrate includes a first region and a second region adjacent to each other; a plurality of first fins located on the first region and separated from each other; A plurality of second fins separated from each other on the second region; a first dielectric layer on the first region, the surface of the first dielectric layer is lower than the top surface of the first fin; a channel layer on the exposed surface of the first fin ; A cover layer on the surface of the channel layer. The semiconductor structure enables the semiconductor device to have better performance while reducing flicker noise.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing, and are widely used in various integrated circuits. According to the main carrier and the doping type during manufacture, MOS transistors are divided into NMOS transistors and PMOS transistors.

However, the performance of existing semiconductor devices still needs to be improved.

Contents of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, which can reduce the flicker noise of the semiconductor device and at the same time make the performance and performance controllability of the semiconductor device better.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a first region and a second region adjacent to each other; several first regions separated from each other on the first region fins; a plurality of second fins separated from each other on the second region; a first dielectric layer on the first region, the surface of the first dielectric layer is lower than the top surface of the first fin; and an exposed surface of the first fin A channel layer; a cover layer located on the surface of the channel layer.

Optionally, the cover layer is made of the same material as the first fin, or the channel layer is made of the same material as the first fin.

Optionally, the material of the channel layer includes silicon germanium, and the material of the covering layer includes silicon.

Optionally, the material of the first fin includes silicon or silicon germanium.

Optionally, the carrier mobility of the material of the channel layer is greater than the carrier mobility of the material of the covering layer.

Optionally, the thickness of the channel layer is less than or equal to 2 nanometers.

Optionally, the thickness of the covering layer is less than or equal to 4 nanometers.

Optionally, it further includes: a second dielectric layer on the second region, the surface of the second dielectric layer is lower than the top surface of the second fin.

Optionally, the first dielectric layer is also located on the second region, and the surface of the first dielectric layer is also lower than the top surface of the second fin.

Optionally, the first region is used to form a PMOS transistor, and the second region is used to form an NMOS transistor.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region; forming a plurality of first fins on the first region; A first dielectric layer is formed on the region, and the surface of the first dielectric layer is lower than the top surface of the first fin; after the formation of the first dielectric layer, a channel layer is formed on the exposed surface of the first fin; on the surface of the channel layer Form an overlay.

Optionally, a selective epitaxial growth process is used to form a channel layer on the exposed surface of the first fin.

Optionally, a capping layer is formed on the surface of the channel layer by using a selective epitaxial growth process.

Optionally, the substrate further includes a second region adjacent to the first region, and there are several second fins on the second region; the method for forming the semiconductor structure further includes: forming the covering After layering, a second dielectric layer is formed on the second region, and the surface of the second dielectric layer is lower than the top surface of the second fin.

Optionally, the method for forming the first dielectric layer and the second dielectric layer includes: forming an initial dielectric layer on the first region and the second region, the initial dielectric layer covering the side wall surfaces of the first fin and the second fin ; forming a mask layer on the surface of the initial dielectric layer, the mask layer exposing the initial dielectric layer on the first region; using the mask layer as a mask, etching the initial dielectric layer on the first region, until the first dielectric layer is formed on the first region; after forming the cover layer, etch the initial dielectric layer on the second region until the surface of the initial dielectric layer on the second region is in contact with the first dielectric layer The surfaces are flush, and a second dielectric layer is formed on the second region.

Optionally, the method for forming the channel layer further includes: before forming the initial dielectric layer, forming an oxide layer on the top surfaces of the first fin and the second fin; using the mask layer as a mask In the process of etching the initial dielectric layer on the first region, the oxide layer on the first region is also etched using the mask layer as a mask, so as to expose the top surface of the first fin.

Optionally, the first dielectric layer is also located on the second region, and the surface of the first dielectric layer is also lower than the top surface of the second fin.

Optionally, the method for forming the channel layer and the cover layer further includes: after forming the first dielectric layer and before forming the channel layer, forming an oxide film on the exposed surface of the second fin; The forming method of the structure further includes: after forming the covering layer, removing the oxide film on the surface of the second fin.

Optionally, further comprising: forming a plurality of gates across the first fin and the second fin on the substrate, the gates including an initial oxide film on the surface of the first fin and the second fin , a dummy gate located on the surface of the initial oxide film; after forming the gate, an intermediate dielectric layer is formed on the surface of the first dielectric layer, and the intermediate dielectric layer is also located on the side wall surface of the gate; after forming the intermediate After the dielectric layer, the dummy gate is removed, and several gate openings are formed in the intermediate dielectric layer, and the bottom of the gate openings exposes the initial oxide film; the method for forming an oxide film on the exposed surface of the second fin includes: After forming the gate opening, the initial oxide film exposed in the first region is removed.

Optionally, the method for forming an oxide film on the exposed surface of the second fin includes: after forming the first dielectric layer, forming an initial oxide film on the exposed surfaces of the first fin and the second fin; A dielectric layer and a mask layer are formed on the surface of the initial oxide film, and the mask layer exposes the initial oxide film on the first region; using the mask layer as a mask, etching the initial oxide film until the first layer is removed an initial oxide film on the first region to form the oxide film on the exposed surface of the second fin.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the semiconductor structure provided by the technical solution of the present invention, the channel layer located on the surface of the first fin and the covering layer located on the surface of the channel layer can form a buried channel structure. In the structure of the buried channel, the channel layer and the gate oxide layer of the transistor are separated by the covering layer, thereby reducing the trapping of carriers in the channel of the transistor by the gate oxide layer and reducing the current carrying capacity. The sub-fluctuation realizes the reduction of the flicker noise of the semiconductor device. At the same time, the choice of channel layer materials is high, and materials with high carrier mobility can be used, so the performance of the transistor is better. In summary, the semiconductor device has better performance while reducing flicker noise.

Correspondingly, in the method for forming a semiconductor structure provided by the technical solution of the present invention, a channel layer is formed on the surface of the first fin, and a covering layer is formed on the surface of the channel layer to form a buried channel structure, thereby realizing Noise reduction of semiconductor devices. At the same time, since the channel layer and the cover layer are separated, the material of the channel layer is not easily affected by the process of forming the cover layer compared to the way of forming the inversion doped region through the ion implantation process. At the same time, the material selection of the channel layer The degree of freedom is high, and materials with high carrier mobility can be used. Therefore, the performance and controllability of the performance of the transistor are relatively good. To sum up, while the semiconductor device reduces flicker noise, the performance and controllability of the semiconductor device are relatively good.

Further, since the channel layer is formed by a selective epitaxial growth process, the material properties of the channel layer are less affected by the high-temperature process, thereby helping to better improve the performance controllability of the transistor.

Further, since the capping layer is formed by the selective epitaxial growth process, the material properties of the channel layer are less affected by the high temperature process, thereby helping to better improve the performance controllability of the transistor.

Description of drawings

1 to 7 are schematic cross-sectional structure diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the present invention;

8 to 15 are schematic cross-sectional structure diagrams of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed ways

As mentioned in the background, the performance of existing semiconductor devices still needs to be improved.

Specifically, in the application of high-precision analog signals or mixed signals, flicker noise of MOS transistors is one of the important design requirements. The flicker noise of MOS transistors is mainly related to the state of carriers. Specifically, the gate oxide layer in the existing MOS transistor is adjacent to the channel, and at the interface where the gate oxide layer is adjacent to the channel, when the carriers in the channel are captured by traps in the gate oxide layer, the MOS transistor The number of carriers and the amount of carrier mobility fluctuate, therefore, affecting the flicker noise of the MOS transistor. At the same time, since the carrier type of PMOS transistor is hole, the carrier type of NMOS transistor is electron. On the one hand, compared with NMOS transistor, the carrier scattering factor of PMOS transistor is larger. On the other hand, , the mobility of holes is worse than that of electrons, which makes the trap density of PMOS transistors trapping carriers larger. Therefore, compared with NMOS transistors, the number of carriers and carrier mobility of PMOS transistors The amount fluctuates more, thus, the PMOS transistor becomes the main source of the flicker noise.

In order to reduce the flicker noise of the PMOS transistor, a semiconductor device and its formation method are proposed, in which an inversion doped region is formed in the well region of the PMOS transistor by using an ion implantation process, so that the carriers will flow along the PMOS transistor during operation. The transmission in the vicinity of PN is formed between the inversion doped region and the well region, therefore, the carrier transmission channel of the PMOS transistor is located inside the semiconductor substrate, that is, the channel of the PMOS transistor is spaced from the gate oxide layer, thus, By increasing the distance between the channel of the PMOS transistor and the gate oxide layer, the influence of the gate oxide layer on the carriers of the PMOS transistor is reduced, and the carrier fluctuation of the PMOS transistor is reduced, so as to reduce the flicker noise of the PMOS transistor and realize the flicker of the semiconductor device Noise reduction.

However, on the one hand, since the ion implantation process is used to form the inversion-doped region, the subsequent high-temperature process is likely to cause ion diffusion in the inversion-doped region, which changes the performance of the semiconductor device, resulting in poor controllability of the performance of the semiconductor device. . On the other hand, since it is necessary to dope inversion ions in the well region of the PMOS transistor to form an inversion doped region, the transconductance (Gm) of the PMOS transistor will be affected by the doped inversion ions and deteriorate, thereby , The control ability of the gate in the PMOS transistor to the current is poor, resulting in poor performance of the PMOS transistor.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a semiconductor structure and its formation method, by forming a channel layer on several first fins in the first region, and forming a covering layer on the surface of the channel layer layer, so that the performance of the semiconductor device is better while reducing the flicker noise.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 7 are schematic cross-sectional structure diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 1 , a substrate 100 is provided.

The material of the substrate 100 includes semiconductor material.

In this embodiment, the material of the substrate 100 includes silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI) and the like. Wherein, the multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, the substrate 100 includes a first region I. Moreover, the substrate 100 further includes a second region II adjacent to the first region I.

Specifically, the first region I in this embodiment is used to form a PMOS transistor, and the second region II is used to form an NMOS transistor.

In this embodiment, the first fin, the channel layer located on the surface of the first fin, and the cover layer located on the surface of the channel layer are subsequently formed in the first region for forming the PMOS transistor, so as to reduce the flicker noise of the semiconductor device . Since the PMOS transistor in the semiconductor device is the main source of flicker noise, in this embodiment, by improving the flicker noise of the semiconductor device in the first region I, the overall flicker noise of the semiconductor device can be improved more efficiently.

In other embodiments, the first region and the second region are respectively used to form other devices, for example, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

Referring to FIG. 2 , a plurality of first fins 101 are formed on the first region I and are separated from each other.

In this embodiment, the method for forming the first fin 101 includes: forming a fin structure patterned layer on the first region I; using the fin structure patterned layer as a mask, patterning the first region I The substrate 100 is used to form a plurality of first fins 101 separated from each other on the first region I.

Specifically, in this embodiment, the material of the first fin 101 includes silicon.

In yet another embodiment, the material of the first fin includes silicon germanium.

In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of second fins 102 separated from each other on the second region II.

In this embodiment, the patterned layer of the fin structure is also located on the second region II. The method for forming the second fin 102 includes: while patterning the substrate 100 in the first region I, patterning the substrate 100 in the second region II by using the fin structure patterning layer as a mask, so as to A plurality of second fins 102 separated from each other are formed on the second region II.

Likewise, in this embodiment, the material of the second fin 102 includes silicon.

Next, before the channel layer is subsequently formed, a first dielectric layer is formed on the first region I, and the surface of the first dielectric layer is lower than the top surface of the first fin 101 . Please refer to FIG. 3 to FIG. 4 for the specific process of forming the first dielectric layer.

Referring to FIG. 3 , an initial dielectric layer 120 is formed on the first region I and the second region II, and the initial dielectric layer 120 covers the sidewall surfaces of the first fin 101 and the second fin 102 .

In this embodiment, the initial dielectric layer 120 provides materials for the subsequent formation of the first dielectric layer on the first region I. Moreover, the initial dielectric layer 120 also provides materials for the subsequent formation of the second dielectric layer on the second region II.

In this embodiment, the process of forming the initial dielectric layer 120 includes a deposition process. The deposition process includes one or a combination of chemical vapor deposition (CVD), fluid chemical vapor deposition (FCVD) and physical vapor deposition (PVD). In other embodiments, the process of forming the initial dielectric layer includes a spin-coating process and the like.

In this embodiment, before forming the initial dielectric layer 120 , an oxide layer 110 is formed on the top surfaces of the first fin 101 and the second fin 102 .

In this embodiment, on the one hand, during the subsequent etching process for forming the first dielectric layer and the second dielectric layer, the loss to the first fin 101 and the second fin 102 can be reduced through the oxide layer 110, thereby The topography of the first fin 101 and the second fin 102 is well protected, so as to reduce the impact of the etching process on the performance of the semiconductor device. On the other hand, in the subsequent selective epitaxial growth process to form a channel layer on the exposed surface of the first fin 101, due to the oxide layer 110 on the top surface of the second fin 102, the first dielectric layer, and The material of the initial dielectric layer 120 on the second region II is different from that of the first fin 101 , so that the selectivity of the epitaxial growth process can be realized to form the channel layer.

In this embodiment, the material of the oxide layer 110 includes silicon oxide.

Referring to FIG. 4 , a mask layer 130 is formed on the surface of the initial dielectric layer 120 , and the mask layer 130 exposes the initial dielectric layer 120 on the first region I. Referring to FIG.

The mask layer 130 is used to pattern the initial dielectric layer 120 in the first region I to form a first dielectric layer on the first region I.

Please continue to refer to FIG. 4, using the mask layer 130 as a mask, etch the initial dielectric layer 120 on the first region I until the first dielectric layer 121 is formed on the first region I, the first dielectric layer The surface of 121 is lower than the top surface of the first fin 101 .

In this embodiment, during the process of etching the initial dielectric layer 120 on the first region I by using the mask layer 130 as a mask, the first region I is also etched by using the mask layer 130 as a mask. The oxide layer 110 on the top surface is exposed to expose the top surface of the first fin 101 .

Thus, the surface of the first dielectric layer 121 exposes the top surface and at least part of the sidewall surface of the first fin 101 .

In this embodiment, since the thickness of the oxide layer 110 is much smaller than the thickness of the etched initial dielectric layer 120 on the first region I, during the process of etching the initial dielectric layer 120 on the first region I, by The loss of the oxide layer 110 exposed to the first region I can realize the removal of the oxide layer 110 on the first region I. Thus, the efficiency of forming the semiconductor structure is improved.

Specifically, the first dielectric layer 121 is located on the surface of the substrate 100 in the first region I and part of the sidewall surface of the first fin 101 connected to the surface of the substrate 100 . At the same time, after the first dielectric layer 121 is formed, the top surface of the first fin 101 and part of the side wall connected to the top surface are exposed.

In other embodiments, in order to better control the etching process and improve the etching precision, the initial dielectric layer and the oxide layer on the first region are respectively etched using the mask layer as a mask, that is, through two The independent etching steps respectively remove the oxide layer on the first region and etch the initial dielectric layer on the first region.

In this embodiment, the process of etching the initial dielectric layer 120 on the first region I includes one or both of a dry etching process and a wet etching process.

In this embodiment, the mask layer 130 is removed after the first dielectric layer 121 is formed.

Referring to FIG. 5 , after the formation of the first dielectric layer 121 , a selective epitaxial growth process is used to form a channel layer 140 on the exposed surface of the first fin 101 .

Since the oxide layer 110 on the top surface of the second fin 102, the first dielectric layer 121, and the initial dielectric layer 120 on the second region II are all different from the material of the first fin 101, by using a selective epitaxial growth process, it is possible to The channel layer 140 is formed only on the exposed surface of the first fin 101 .

In this embodiment, since the channel layer 140 is formed by a selective epitaxial growth process, the material properties of the channel layer 140 are less affected by the high-temperature process, which is beneficial to better improve the performance of the transistor. controlling.

Specifically, compared with the method of forming the inversion doped region by ion implantation, the channel layer 140 is directly grown and formed by selective epitaxial growth, so that the stability of the material properties of the formed channel layer 140 is higher. It is less affected by the high-temperature process, so the controllability is also higher, thereby helping to better improve the performance controllability of the transistor. In this embodiment, the carrier mobility of the material of the channel layer 140 is greater than the carrier mobility of the material of the first fin 101 .

Specifically, the material of the channel layer 140 includes silicon germanium.

In this embodiment, the thickness of the channel layer 140 is less than or equal to 2 nanometers.

If the channel layer 140 is too thick, the subsequently formed covering layer needs to cover a larger area, resulting in unnecessary waste of materials. Therefore, making the thickness of the channel layer 140 less than or equal to 2 nanometers can improve the flicker noise of the semiconductor device, make the performance of the semiconductor device, and the controllability of the performance better, and reduce the amount of material used in the formation of the semiconductor device. waste.

It should be noted that, the thickness of the channel layer 140 refers to the thickness dimension of the channel layer 140 in a direction perpendicular to the surface of the first fin 101 .

Referring to FIG. 6 , a covering layer 150 is formed on the surface of the channel layer 140 .

By forming the channel layer 140 on the surface of the first fin 101 and forming a covering layer on the surface of the channel layer 140, a buried channel structure is formed, thereby reducing the noise of the semiconductor device. At the same time, since the channel layer 140 and the covering layer 150 are formed separately, the material of the channel layer 140 is not easily affected by the process of forming the covering layer 150 compared to the way of forming the inversion doped region through the ion implantation process. The material selection of the channel layer 140 has a high degree of freedom, and materials with high carrier mobility can be used. Therefore, the performance of the transistor and the controllability of the performance are relatively good. To sum up, while the semiconductor device reduces flicker noise, the performance and controllability of the semiconductor device are relatively good.

Not only that, since the channel layer 140 is formed on the surface of the first fin 101, the surface area of the channel layer 140 is larger than that of the first fin 101, so that the channel layer 140 is compatible with the source-drain structure of the transistor (the first fin formed subsequently) The source-drain structure) has a larger contact area, thus, it is beneficial to reduce the contact resistance of the transistor, increase the working current of the transistor, and make the performance of the transistor better.

The carrier mobility of the material of the channel layer 140 is greater than the carrier mobility of the material of the capping layer 150 . Therefore, the carrier mobility of the material of the channel layer 140 is greater than the carrier mobility of the material of the capping layer 150 and the material of the first fin 101 at the same time. Therefore, in this embodiment, the main channel of the transistor is in the channel layer 140 .

In this embodiment, the material of the channel layer 140 is different from that of the covering layer 150 , and the material of the first fin 101 is the same as that of the covering layer 150 .

Specifically, the material of the covering layer 150 includes silicon. Specifically, since the materials of the first fin 101 and the cover layer 150 include silicon, and the material of the channel layer 140 includes silicon germanium, the cover layer plays a role of burying the main channel of the transistor, so that the main channel of the transistor The channel is in the channel layer 140 to realize the structure of the buried channel. At the same time, since the material of the cover layer 150 is silicon, the cover layer 150 can be used as a secondary channel of the transistor to reduce flicker noise. and further performance improvements.

In yet another embodiment, the material of the channel layer is different from that of the cover layer, and the material of the channel layer is the same as that of the first fin. Specifically, the material of the channel layer and the first fin includes silicon germanium, and the material of the covering layer includes silicon.

In this embodiment, the process of forming the capping layer 150 includes a selective epitaxial growth process.

In this embodiment, since the capping layer 150 is formed by a selective epitaxial growth process, the material properties of the channel layer 140 are less likely to be affected by the high-temperature process, thereby helping to better improve the performance of the transistor. Controllability.

In this embodiment, the thickness of the covering layer 150 is less than or equal to 4 nanometers.

If the thickness of the covering layer 150 is too large, the distance between the sidewalls of adjacent channel layers 140 will be too small, which is not conducive to subsequent material filling, and will affect the performance and reliability of the semiconductor device. For example, when the gate is subsequently formed, the material filling quality of the gate is poor, and some defects such as voids are formed in the structure of the gate, which reduces the performance and reliability of the semiconductor device. Therefore, making the thickness of the covering layer 150 less than or equal to 4 nanometers can reduce the risk of performance and reliability degradation of the semiconductor device while improving the flicker noise of the semiconductor device.

Referring to FIG. 7 , after the capping layer 150 is formed, a second dielectric layer 122 is formed on the second region II, and the surface of the second dielectric layer 122 is lower than the top surface of the second fin 102 .

Specifically, after the covering layer 150 is formed, the initial dielectric layer 120 on the second region II is etched until the surface of the initial dielectric layer 120 on the second region II is flush with the surface of the first dielectric layer 121, A second dielectric layer 122 is formed on the second region II.

In this embodiment, the method for etching the initial dielectric layer 120 on the second region II includes: forming a second dielectric patterned layer (not shown) on the surface of the first region I and the surface of the cover layer 150, the second The dielectric patterning layer exposes the initial dielectric layer 120 on the second region II; using the second dielectric patterning layer as a mask, etch the initial dielectric layer 120 on the second region II to form the second dielectric layer Layer 122.

In this embodiment, during the process of etching the initial dielectric layer 120 on the second region II using the second dielectric patterning layer as a mask, the second dielectric patterning layer is also used as a mask to etch Oxide layer 110 on the second region II to expose the top surface of the second fin 102 .

In this embodiment, since the thickness of the oxide layer 110 is much smaller than the thickness of the etched initial dielectric layer 120 on the second region II, during the process of etching the initial dielectric layer 120 on the second region II, by The loss of the oxide layer 110 exposed to the second region II enables removal of the oxide layer 110 on the second region II. Thus, the efficiency of forming the semiconductor structure is improved.

In other embodiments, in order to better control the etching process and improve the etching precision, the initial dielectric layer and the oxide layer on the second region are respectively etched using the mask layer as a mask, that is, through two The independent etching steps respectively remove the oxide layer on the second region and etch the initial dielectric layer on the second region.

In this embodiment, the process of etching the initial dielectric layer 120 on the second region II includes one or both of a dry etching process and a wet etching process.

In this embodiment, the second dielectric patterned layer is removed after the second dielectric layer 122 is formed.

It should be noted that, in this embodiment, for ease of understanding, it is only schematically shown that there is a height difference between the top surface of the cover layer 150 and the top surface of the second fin 102 in the direction perpendicular to the surface of the substrate 100 . In other embodiments, before forming the channel layer 140 , the first fin 101 may be etched to reduce the height of the first fin 101 , so that the top surface of the capping layer 150 is flush with the top surface of the second fin 102 .

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to FIG. 7 , which includes: a substrate 100, the substrate 100 includes adjacent first regions I and second regions II; A plurality of first fins 101 separated from each other on the first region I; a plurality of second fins 102 separated from each other on the second region I; a first dielectric layer 121 located on the first region I, the first The surface of a dielectric layer 121 is lower than the top surface of the first fin 101 ; the channel layer 140 is located on the exposed surface of the first fin 101 ; and the covering layer 150 is located on the surface of the channel layer 140 .

The channel layer 140 on the surface of the first fin 101 and the covering layer 150 on the surface of the channel layer 140 can form a buried channel structure. In the structure of the buried channel, the channel layer 140 and the gate oxide layer of the transistor are separated by the cover layer 150, thereby reducing the trapping of carriers in the channel of the transistor by the gate oxide layer and reducing the Fluctuation of currents realizes the reduction of flicker noise of semiconductor devices. At the same time, the material of the channel layer 140 has high freedom of choice, and materials with higher carrier mobility than those of the first fin 101 and the covering layer 150 can be used. Therefore, the performance of the transistor is better. In summary, the semiconductor device has better performance while reducing flicker noise.

Not only that, since the channel layer 140 is located on the surface of the first fin 101, the surface area of the channel layer 140 is larger than that of the first fin 101, so there is a larger contact between the channel layer 140 and the source-drain structure of the transistor. Therefore, it is beneficial to reduce the contact resistance of the transistor, increase the operating current of the transistor, and make the performance of the transistor better.

The material of the substrate 100 includes semiconductor material.

In this embodiment, the material of the substrate 100 includes silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI) and the like. Wherein, the multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

Specifically, the first region I in this embodiment is used to form a PMOS transistor, and the second region II is used to form an NMOS transistor.

Since the PMOS transistor in the semiconductor device is the main source of flicker noise, in this embodiment, by improving the flicker noise of the semiconductor device in the first region I, the overall flicker noise of the semiconductor device can be improved more efficiently.

In other embodiments, the first region and the second region are respectively used to form other devices, for example, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

In this embodiment, the carrier mobility of the material of the channel layer 140 is greater than the carrier mobility of the material of the covering layer 150, and the carrier mobility of the material of the channel layer 140 is greater than The carrier mobility of the material of the first fin 101 . Thus, the main channel of the transistor is within said channel layer 140 .

In this embodiment, the material of the channel layer 140 is different from that of the covering layer 150 , and the material of the first fin 101 is the same as that of the covering layer 150 .

Specifically, the material of the first fin 101 and the cover layer 150 includes silicon, and the material of the channel layer 140 includes silicon germanium. Therefore, the cover layer 150 plays a role of burying the main channel of the transistor, so that the main channel of the transistor A channel is in the channel layer 140 to realize the structure of the buried channel. At the same time, since the material of the covering layer 150 is silicon, the covering layer 150 can also serve as a secondary channel of the transistor, so as to reduce the flicker noise and further improve the performance.

In yet another embodiment, the material of the channel layer is different from that of the cover layer, and the material of the channel layer is the same as that of the first fin. Specifically, the material of the channel layer and the first fin includes silicon germanium, and the material of the covering layer includes silicon.

In this embodiment, the material of the second fin 102 includes silicon.

In this embodiment, the thickness of the channel layer 140 is less than or equal to 2 nanometers.

In this embodiment, the thickness of the covering layer 150 is less than or equal to 4 nanometers.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 122 located on the second region II, and the surface of the second dielectric layer 122 is lower than the top surface of the second fin 102 .

8 to 15 are schematic cross-sectional structure diagrams of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

Referring to FIG. 8 , a substrate 200 is provided.

The material of the substrate 200 includes semiconductor material.

In this embodiment, the material of the substrate 200 includes silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI) and the like. Wherein, the multi-element semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, the substrate 200 includes a first region I. Moreover, the substrate 200 further includes a second region II adjacent to the first region I.

Specifically, the first region I in this embodiment is used to form a PMOS transistor, and the second region II is used to form an NMOS transistor.

In this embodiment, the first fin, the channel layer located on the surface of the first fin, and the cover layer located on the surface of the channel layer are subsequently formed in the first region for forming the PMOS transistor, so as to reduce the flicker of the semiconductor device noise. Since the PMOS transistor in the semiconductor device is the main source of flicker noise, in this embodiment, by improving the flicker noise of the semiconductor device in the first region I, the overall flicker noise of the semiconductor device can be improved more efficiently.

In other embodiments, the first region and the second region are respectively used to form other devices, for example, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

Referring to FIG. 9 , a plurality of first fins 201 are formed on the first region I and are separated from each other.

In this embodiment, the method for forming the first fin 201 includes: forming a fin structure patterned layer on the first region I; using the fin structure patterned layer as a mask, patterning the first region I The substrate 200 is used to form a plurality of first fins 201 separated from each other on the first region I.

Specifically, in this embodiment, the material of the first fin 201 includes silicon.

In yet another embodiment, the material of the first fin includes silicon germanium.

In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of second fins 202 separated from each other on the second region II.

In this embodiment, the patterned layer of the fin structure is also located on the second region II. The method for forming the second fin 202 includes: while patterning the substrate 200 in the first region I, patterning the substrate 200 in the second region II by using the fin structure patterning layer as a mask, so as to A plurality of second fins 202 separated from each other are formed on the second region II.

In this embodiment, the material of the second fin 202 includes silicon.

Please refer to FIG. 10 , a first dielectric layer 220 is formed on the first region I and the second region II, and the surface of the first dielectric layer 220 is lower than the top surface of the first fin 201 and the top surface of the second fin 202 .

Thus, the surface of the first dielectric layer 220 exposes the top surface and at least part of the sidewall surface of the first fin 201 , the top surface and at least part of the sidewall surface of the second fin 202 .

On the one hand, in the subsequent selective epitaxial growth process to form a channel layer on the exposed surface of the first fin 101, due to the first dielectric layer 220 and the subsequently formed oxide film on the surface of the second fin 202 and the first The materials of the fins 201 are different, therefore, the selectivity of the epitaxial growth process to form the channel layer can be achieved. On the other hand, the first dielectric layer 220 is also used to equally space between the substrate 200 and other semiconductor structures, and between the plurality of first fins 201 and the plurality of second fins 202 , so as to play an insulating role.

In this embodiment, the method for forming the first dielectric layer 220 includes: forming an initial dielectric layer (not shown) on the first region I and the second region II, the initial dielectric layer covering the second The side wall surfaces of the first fin 201 and the second fin 202 ; the initial dielectric layer is etched to expose part of the side wall surfaces of the first fin 201 and the second fin 202 to form the first dielectric layer 220 .

In this embodiment, the process of forming the initial dielectric layer includes a deposition process. The deposition process includes one or a combination of chemical vapor deposition process, fluid chemical vapor deposition process and physical vapor deposition process. In other embodiments, the process of forming the initial dielectric layer includes a spin-coating process and the like.

In this embodiment, the process of etching the initial dielectric layer includes one or both of a dry etching process and a wet etching process.

Referring to FIG. 11 , after the first dielectric layer 220 is formed, a plurality of gates 230 are formed on the substrate 200 across the first fin 201 and the second fin 202 .

In this embodiment, the gate 230 includes: an initial oxide film 231 located on the surfaces of the first fin 201 and the second fin 202 ; and a dummy gate 232 located on the surface of the initial oxide film 231 .

The dummy gate 232 defines the shape of the subsequently formed metal gate.

The initial oxide film 231 provides material for subsequent formation of an oxide film.

In this embodiment, the method for forming the gate 230 includes: forming a gate oxide material film (not shown) covering the surfaces of the first fin 201 and the second fin 202 on the substrate 200, the The gate oxide material film provides materials for forming the initial oxide film 231; a dummy gate material film (not shown) is formed on the surface of the gate oxide material film, and the dummy gate material film provides materials for forming the dummy gate 232; The dummy gate material film and the gate oxide material film are formed until the gate 230 is formed on the substrate 200 until the surface of the first dielectric layer 220 is exposed.

In this embodiment, the method for forming the semiconductor structure further includes: after forming the gate 230, forming an intermediate dielectric material layer (not shown) covering the surface of the gate 230 on the surface of the first dielectric layer 220; Thinning the intermediate dielectric material layer until the top surface of the gate 230 is exposed to form an intermediate dielectric layer (not shown).

On the one hand, the intermediate dielectric layer provides support for subsequent formation of metal gates. On the other hand, by covering the surfaces of the first fin 201 and the second fin 202 that are not in contact with the metal gate, the intermediary layer can protect the channel during the subsequent formation of the channel layer and the cover layer. The positions of the layer and the cover layer are further limited, that is, the channel layer and the cover layer are only formed on the surface of the first fin 201 exposed by the subsequently formed gate opening.

In this embodiment, since the initial oxide film 231 in the gate 230 is used as the material of the oxide film subsequently formed on the surface of the second fin 202, the existing material (initial oxide film 231) in the existing process is used. The subsequent formation of the channel layer and the covering layer is implemented in a relatively simple manner, thereby improving the efficiency, cost and compatibility of the method for forming the semiconductor structure.

In this embodiment, after forming the gate 230 and before forming the intermediate dielectric layer, the first source and drain are respectively formed in the first fin 201 and the second fin 202 on both sides of the gate 230 and a second source and drain opening, and a first source and drain structure is formed in the first source and drain opening, and a second source and drain structure is formed in the second source and drain opening.

Referring to FIG. 12 , after the intermediate dielectric layer is formed, the dummy gate 232 is removed, and several gate openings 233 are formed in the intermediate dielectric layer, and the initial oxide film 231 is exposed at the bottom of the gate openings 233 .

The gate opening 233 provides a space for subsequent metal gate filling.

In this embodiment, the process of removing the dummy gate 232 includes one or both of a dry etching process and a wet etching process.

Please continue to refer to FIG. 12 , after the gate opening 233 is formed, the initial oxide film 231 exposed in the first region I is removed, so that an oxide film 234 is formed on the exposed surface of the second fin 202 .

In this embodiment, the method for removing the initial oxide film 231 exposed in the first region I includes: forming an oxide film patterned layer (not shown) on the intermediate dielectric layer and in the gate opening 233 of the second region II, The patterned layer exposes the gate opening 233 of the first region I; using the oxide film patterned layer as a mask, etch the initial oxide film 231 exposed in the gate opening 233 in the first region I until the first region I is removed. An initial oxide film 231 exposed in a region I.

In this embodiment, the oxide film patterning layer is removed after the oxide film 234 is formed.

In this embodiment, the material of the oxide film 234 includes silicon oxide.

Referring to FIG. 13 , a channel layer 240 is formed on the exposed surface of the first fin 201 by using a selective epitaxial growth process.

Since the material of the intermediate dielectric layer, the first dielectric layer 220, and the oxide film 234 on the surface of the second fin 202 is different from that of the first fin 201, by adopting the selective epitaxial growth process, only the gate opening 233 can be exposed. The channel layer 240 is formed on the surface of the first fin 101 .

In this embodiment, since the channel layer 240 is formed by a selective epitaxial growth process, the material properties of the channel layer 240 are less affected by the high-temperature process, which is beneficial to better improve the performance of the transistor. controlling.

Specifically, compared with the method of forming the inversion doped region by ion implantation, the channel layer 240 is directly grown and formed by selective epitaxial growth, so that the stability of the material properties of the formed channel layer 240 is higher. It is less affected by the high-temperature process, so the controllability is also higher, thereby helping to better improve the performance controllability of the transistor.

In this embodiment, the carrier mobility of the material of the channel layer 240 is greater than the carrier mobility of the material of the first fin 201 .

Specifically, the material of the channel layer 240 includes silicon germanium.

In this embodiment, the thickness of the channel layer 240 is less than or equal to 2 nanometers.

If the channel layer 240 is too thick, the subsequently formed covering layer needs to cover a larger area, resulting in redundant waste of materials. Therefore, making the thickness of the channel layer 240 less than or equal to 2 nanometers can improve the flicker noise of the semiconductor device, make the performance and controllability of the semiconductor device better, and reduce the amount of material used in the formation of the semiconductor device. waste.

It should be noted that, the thickness of the channel layer 240 refers to the thickness dimension of the channel layer 240 in a direction perpendicular to the surface of the first fin 201 .

Referring to FIG. 14 , a covering layer 250 is formed on the surface of the channel layer 240 .

By forming the channel layer 240 on the surface of the first fin 201 and forming a cover layer on the surface of the channel layer 240, a buried channel structure is formed, thereby reducing the noise of the semiconductor device. At the same time, since the channel layer 240 and the covering layer 250 are formed separately, the material of the channel layer 240 is not easily affected by the process of forming the covering layer 250 compared to the way of forming the inversion doped region through the ion implantation process. The material selection of the channel layer 240 has a high degree of freedom, and materials with high carrier mobility can be used. Therefore, the performance of the transistor and the controllability of the performance are relatively good. To sum up, while the semiconductor device reduces flicker noise, the performance and controllability of the semiconductor device are relatively good.

Furthermore, since the channel layer 240 is formed on the surface of the first fin 201, the surface area of the channel layer 240 is larger than that of the first fin 201, so that between the channel layer 240 and the first source-drain structure, The larger contact area is beneficial to reduce the contact resistance of the transistor, increase the working current of the transistor, and make the performance of the transistor better.

In this embodiment, the carrier mobility of the material of the channel layer 240 is greater than the carrier mobility of the material of the capping layer 250 . Therefore, the carrier mobility of the material of the channel layer 240 is greater than the carrier mobility of the material of the capping layer 250 and the material of the first fin 201 at the same time. Therefore, in this embodiment, the main channel of the transistor is in the channel layer 240 .

In this embodiment, the material of the channel layer 240 is different from that of the covering layer 250 , and the material of the first fin 201 is the same as that of the covering layer 250 .

Specifically, the material of the covering layer 250 includes silicon.

Specifically, since the material of the first fin 201 and the cover layer 250 includes silicon, and the material of the channel layer 240 includes silicon germanium, the cover layer 250 plays a role of burying the main channel of the transistor, so that the transistor The main channel of the main channel is in the channel layer 240 to realize the structure of the buried channel. At the same time, since the material of the cover layer 250 is silicon, the cover layer 250 can be used as a secondary channel of the transistor to take care of the flicker noise reduction and further performance improvement.

In yet another embodiment, the material of the channel layer is different from that of the cover layer, and the material of the channel layer is the same as that of the first fin. Specifically, the material of the channel layer and the first fin includes silicon germanium, and the material of the covering layer includes silicon.

In this embodiment, the process of forming the capping layer 250 includes a selective epitaxial growth process.

In this embodiment, since the cover layer 250 is formed by a selective epitaxial growth process, the material properties of the surface of the first fin structure 241 are less likely to be affected by the high-temperature process, thereby facilitating better improvement. Transistor performance controllability.

In this embodiment, the thickness of the covering layer 250 is less than or equal to 4 nanometers.

If the thickness of the covering layer 250 is too large, the distance between the sidewalls of adjacent first fin structures 241 will be too small, which is not conducive to subsequent material filling, and will affect the performance and reliability of the semiconductor device. For example, when the metal gate is subsequently formed, the material filling quality of the metal gate is poor, and some defects such as voids are formed in the structure of the metal gate, which reduces the performance and reliability of the semiconductor device. Therefore, making the thickness of the covering layer 250 less than or equal to 4 nanometers can reduce the risk of performance and reliability degradation of the semiconductor device while improving the flicker noise of the semiconductor device.

In this embodiment, after the capping layer 250 is formed, the oxide film 234 on the surface of the second fin 201 is removed.

In other embodiments, the channel layer and the covering layer may also be formed after forming the first dielectric layer and before forming the gate. Specifically, the method for forming the channel layer and the cover layer includes: after forming the first dielectric layer, forming an oxide film on the exposed surface of the second fin; after forming the oxide film, using a selective epitaxial growth process, A channel layer is formed on the exposed surface of the first fin; a covering layer is formed on the surface of the channel layer by using a selective epitaxial growth process; after the covering layer is formed, the oxide film on the surface of the second fin is removed. Wherein, the method for forming an oxide film on the exposed surface of the second fin includes: after forming the first dielectric layer and before forming the gate, forming an initial oxide film on the exposed surfaces of the first fin and the second fin; A mask layer is formed on the surface of the first dielectric layer and the initial oxide film, and the mask layer exposes the initial oxide film on the first region; using the mask layer as a mask, etch the initial oxide film until it is removed an initial oxide film on the first region to form the oxide film on the exposed surface of the second fin.

Referring to FIG. 15 , after removing the oxide film 234 on the surface of the second fin 201 , a metal gate 260 is formed in the gate opening 233 .

The method for forming the metal gate 260 includes: after removing the oxide film 234 on the surface of the second fin 201, forming a metal gate material layer (not shown) on the surface of the intermediate dielectric layer and in the gate opening 233; The metal gate material layer is removed until the intermediate dielectric layer is exposed.

It should be noted that, in this embodiment, for ease of understanding, it is only schematically shown that there is a height difference between the top surface of the cover layer 250 and the top surface of the second fin 202 in the direction perpendicular to the surface of the substrate 200 . In other embodiments, the second fin 202 may be higher than the first fin 201 by patterning the first fin 201 and the second fin 202 respectively, so that the top surface of the cover layer 250 and the top surface of the second fin 202 flush.

Correspondingly, another embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to FIG. 15 , including: a substrate 200, the substrate 200 includes adjacent first regions I and second regions II ; a plurality of first fins 201 separated from each other on the first region I; a plurality of second fins 202 separated from each other on the second region I; a first medium located on the first region I and the second region II Layer 220, the surface of the first dielectric layer 220 is lower than the top surface of the first fin 101 and the top surface of the second fin 201; the channel layer 240 located on the exposed surface of the first fin 201; the channel layer 240 located on the surface of the channel layer 240 Overlay 250 .

The channel layer 240 on the surface of the first fin 201 and the covering layer 250 on the surface of the channel layer 240 can form a buried channel structure. In the structure of the buried channel, the channel layer 240 and the gate oxide layer of the transistor are separated by the cover layer 250, thereby reducing the trapping of carriers in the channel of the transistor by the gate oxide layer and reducing the Fluctuation of currents realizes the reduction of flicker noise of semiconductor devices. At the same time, the material of the channel layer 240 has high freedom of choice, and materials with higher carrier mobility than the first fin 201 and the covering layer 250 can be used. Therefore, the performance of the transistor is better. In summary, the semiconductor device has better performance while reducing flicker noise.

Furthermore, since the channel layer 240 is located on the surface of the first fin 201, the surface area of the channel layer 240 is larger than that of the first fin 201, so there is a larger contact between the channel layer 240 and the first source-drain structure. Therefore, it is beneficial to reduce the contact resistance of the transistor, increase the operating current of the transistor, and make the performance of the transistor better.

The material of the substrate 200 includes semiconductor material.

In this embodiment, the material of the substrate 200 includes silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI) and the like. Wherein, the multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

Specifically, the first region I in this embodiment is used to form a PMOS transistor, and the second region II is used to form an NMOS transistor.

Since the PMOS transistor in the semiconductor device is the main source of flicker noise, in this embodiment, by improving the flicker noise of the semiconductor device in the first region I, the overall flicker noise of the semiconductor device can be improved more efficiently.

In other embodiments, the first region and the second region are respectively used to form other devices, for example, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

In this embodiment, the carrier mobility of the material of the channel layer 240 is greater than the carrier mobility of the material of the covering layer 250, and the carrier mobility of the material of the channel layer 240 is greater than The carrier mobility of the material of the first fin 201 . Thus, the main channel of the transistor is within said channel layer 240 .

In this embodiment, the material of the channel layer 240 is different from that of the covering layer 250 , and the material of the first fin 201 is the same as that of the covering layer 250 .

Specifically, the material of the first fin 201 and the cover layer 250 includes silicon, and the material of the channel layer 240 includes silicon germanium. Therefore, the cover layer 250 plays a role of burying the main channel of the transistor, so that the main channel of the transistor A channel is in the channel layer 240 to realize the structure of the buried channel. At the same time, since the material of the covering layer 250 is silicon, the covering layer 250 can also serve as a secondary channel of the transistor, so as to reduce flicker noise and further improve performance.

In yet another embodiment, the material of the channel layer is different from that of the cover layer, and the material of the channel layer is the same as that of the first fin. Specifically, the material of the channel layer and the first fin includes silicon germanium, and the material of the covering layer includes silicon.

In this embodiment, the material of the second fin 202 includes silicon.

In this embodiment, the thickness of the channel layer 240 is less than or equal to 2 nanometers.

In this embodiment, the thickness of the covering layer 250 is less than or equal to 4 nanometers.

In this embodiment, the semiconductor structure further includes: an intermediate dielectric layer (not shown) located on the first dielectric layer 220, in which there are several The gate opening 233 of the fin 202 (as shown in FIG. 14 ), and the channel layer 240 and the cover layer 250 are only located on the surface of the first fin 201 exposed by the gate opening 233 .

In this embodiment, the semiconductor structure further includes: a metal gate 260 located in the gate opening 233 , and the metal gate 260 straddles the capping layer 250 and the second fin 202 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure, comprising:

a substrate comprising a first region and a second region that are contiguous;

a plurality of first fins located on the first region and separated from each other;

a plurality of second fins located on the second region and separated from each other;

the first dielectric layer is positioned on the first area, and the surface of the first dielectric layer is lower than the top surface of the first fin;

a channel layer on an exposed surface of the first fin;

and the covering layer is positioned on the surface of the channel layer.

2. The semiconductor structure of claim 1, in which a material of the cap layer and the first fin is the same, or a material of the channel layer and the first fin is the same.

3. The semiconductor structure of claim 1, wherein the material of the channel layer comprises silicon germanium and the material of the cap layer comprises silicon.

4. The semiconductor structure of claim 3, in which a material of the first fin comprises silicon or silicon germanium.

5. The semiconductor structure of claim 1, wherein a carrier mobility of a material of the channel layer is greater than a carrier mobility of a material of the cap layer.

6. The semiconductor structure of claim 1, wherein the channel layer has a thickness of less than or equal to 2 nanometers.

7. The semiconductor structure of claim 1, wherein the capping layer has a thickness of less than or equal to 4 nanometers.

8. The semiconductor structure of claim 1, further comprising: and the surface of the second dielectric layer is lower than the top surface of the second fin.

9. The semiconductor structure of claim 1, wherein the first dielectric layer is further located on the second region, and a surface of the first dielectric layer is further below a top surface of the second fin.

10. The semiconductor structure of claim 1, wherein the first region is used to form a PMOS transistor and the second region is used to form an NMOS transistor.

11. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first region;

forming a plurality of first fins on the first region;

forming a first dielectric layer on the first region, wherein the surface of the first dielectric layer is lower than the top surface of the first fin;

forming a channel layer on the exposed surface of the first fin after forming the first dielectric layer;

and forming a covering layer on the surface of the channel layer.

12. The method of forming a semiconductor structure of claim 11, wherein a channel layer is formed on an exposed surface of the first fin using a selective epitaxial growth process.

13. The method of forming a semiconductor structure of claim 11, wherein a capping layer is formed on a surface of the channel layer using a selective epitaxial growth process.

14. The method of forming a semiconductor structure of claim 11, wherein the substrate further comprises a second region adjacent to the first region, the second region having a plurality of second fins thereon; the method for forming the semiconductor structure further comprises the following steps: and after the covering layer is formed, forming a second dielectric layer on the second area, wherein the surface of the second dielectric layer is lower than the top surface of the second fin.

15. The method of forming a semiconductor structure of claim 14, wherein forming the first dielectric layer and the second dielectric layer comprises: forming an initial dielectric layer on the first region and the second region, wherein the initial dielectric layer covers the side wall surfaces of the first fin and the second fin; forming a mask layer on the surface of the initial dielectric layer, wherein the mask layer exposes the initial dielectric layer on the first area; etching the initial dielectric layer on the first area by taking the mask layer as a mask until the first dielectric layer is formed on the first area; and after the covering layer is formed, etching the initial dielectric layer on the second area until the surface of the initial dielectric layer on the second area is flush with the surface of the first dielectric layer, and forming a second dielectric layer on the second area.

16. The method of forming a semiconductor structure of claim 15, wherein the method of forming the channel layer further comprises: forming an oxide layer on the top surfaces of the first fin and the second fin before forming the initial dielectric layer; and in the process of etching the initial dielectric layer on the first area by taking the mask layer as a mask, etching the oxide layer on the first area by taking the mask layer as a mask to expose the top surface of the first fin.

17. The method of forming a semiconductor structure of claim 14, wherein the first dielectric layer is further on the second region, and a surface of the first dielectric layer is further below a top surface of the second fin.

18. The method of forming a semiconductor structure of claim 17, wherein the method of forming the channel layer and the cap layer further comprises: forming an oxide film on the exposed surface of the second fin after the first dielectric layer is formed and before the channel layer is formed; the forming method of the semiconductor structure further comprises the following steps: after the forming of the covering layer, the oxide film on the surface of the second fin is removed.

19. The method of forming a semiconductor structure of claim 18, further comprising: forming a plurality of gates crossing the first fin and the second fin on the substrate, wherein the gates comprise initial oxide films on the surfaces of the first fin and the second fin and dummy gates on the surfaces of the initial oxide films; after the grid electrode is formed, forming an intermediate dielectric layer on the surface of the first dielectric layer, wherein the intermediate dielectric layer is also positioned on the side wall surface of the grid electrode; after forming an intermediate dielectric layer, removing the pseudo grid, forming a plurality of grid openings in the intermediate dielectric layer, and exposing the initial oxidation film at the bottoms of the grid openings; the method for forming the oxide film on the exposed surface of the second fin comprises the following steps: after the gate opening is formed, the initial oxide film exposed by the first region is removed.

20. The method of forming a semiconductor structure of claim 18, wherein forming an oxide film on the exposed second fin surface comprises: after the first dielectric layer is formed, forming an initial oxide film on the exposed surfaces of the first fin and the second fin; forming a mask layer on the surfaces of the first dielectric layer and the initial oxide film, wherein the mask layer exposes the initial oxide film on the first area; and etching the initial oxide film by taking the mask layer as a mask until the initial oxide film on the first region is removed, so as to form the oxide film on the exposed surface of the second fin.

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