CN115172406A - Vertical Hall device array and preparation method thereof - Google Patents

Abstract

A vertical Hall device array and a preparation method, the vertical Hall device array comprising: a P-type substrate; an N-type well arranged on the P-type substrate; a groove isolation structure, arranged on the P-type substrate The surface of the N-type well; a plurality of vertical Hall devices are distributed on the N-type well at equal intervals; and the plurality of the vertical Hall devices are connected by an alternate interconnection method. The vertical Hall device array and preparation method of the present application improve the measurement accuracy of the magnetic induction of the device and the stability of the working state of the vertical Hall device, and at the same time can effectively reduce the area of the vertical Hall array and the area of the magnetic induction area, Improve the integration of the Hall chip.

Description

A vertical Hall device array and preparation method thereof

technical field

The present application relates to the technical field of integrated circuit design, and in particular, to a vertical Hall device array and a preparation method.

Background technique

With the development of science and technology, Hall sensors based on CMOS technology have attracted more and more attention because they are easy to integrate with CMOS circuits, and can achieve low cost and high integration. Integrated Hall chips are also increasingly used in automobile manufacturing, medical electronics, mobile communications and other fields. Hall sensors are mainly divided into horizontal Hall devices and vertical Hall devices. Horizontal Hall sensors are mainly used to detect the magnetic field component perpendicular to the chip surface direction. The Hall sensor is mainly used to detect the magnetic field component parallel to the surface of the chip. When the vertical Hall device works, the bias current needs to flow into the device from the surface input electrode first, and then pass through the "U"-shaped path inside the device and then pass through the surface. The output electrode flows out, and such a complex path will affect the Hall sensing accuracy of the vertical Hall device, and there will be mismatched voltages. Even in the case of zero magnetic field, the two Hall electrode ports also have a potential difference.

In order to reduce the mismatch voltage of the vertical Hall device, the alternate interconnection method is usually adopted, and each signal flows through the same area of the Hall device through the alternate connection between different electrodes of multiple vertical Hall devices, so as to effectively Reduce the initial offset disturbance of the device. The traditional alternate interconnection method is realized by interconnecting multiple separate vertical Hall devices, but this will occupy a large chip area and bring challenges to the high integration of the chip.

SUMMARY OF THE INVENTION

In order to solve the shortcomings of the prior art, the purpose of the present application is to provide a vertical Hall device array and a preparation method, which utilizes an N-type well and a plurality of N-type buried layer structures located in the N-type well to improve the vertical Hall device array. The magnetic induction precision of the device makes the device have lower mismatch disturbance under the condition of low magnetic field, reducing the area of the device.

In order to achieve the above purpose, the vertical Hall device array provided by this application includes:

P-type substrate;

an N-type well disposed on the P-type substrate;

a trench isolation structure, arranged on the surface of the N-type well;

A plurality of vertical Hall devices are distributed on the N-type well at equal intervals;

A plurality of the vertical Hall devices are connected by an alternate interconnection method.

Further, the number of the vertical Hall devices is 4N, where N is a positive integer greater than or equal to 1.

Further, the depth of the trench isolation structure is greater than 0.5 μm.

Further, the vertical Hall device further includes an N-type buried layer disposed at the bottom of the N-type well, and a port structure located above the N-type buried layer.

Further, the relationship between the distance between the vertical Hall devices and the width of the N-type buried layer is:

Among them, L1 is the distance between the vertical Hall devices, and L2 is the width of the N-type buried layer.

Further, the port structure includes a first ohmic electrode, a second ohmic electrode, a first Hall electrode, and a second Hall electrode, wherein,

The second Hall electrodes are located at both ends of the port structure and are short-circuited through metal wires;

An N+ region is provided under the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode The electrode, the first Hall electrode and the second Hall electrode respectively form ohmic contact with the N-type well.

Further, the slot isolation structure is respectively located between the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode, and the vertical Hall device between.

Further, the relationship between the spacing between the first Hall electrode and the first ohmic electrode and the spacing between the second ohmic electrode and the first Hall electrode is:

Wherein, L3 is the distance between the first Hall electrode and the first ohmic electrode, and L4 is the distance between the second ohmic electrode and the first Hall electrode.

Further, the multiple vertical Hall devices are connected by an alternate interconnection method, including:

The first ohmic electrode of the 1+m-th Hall device, the first Hall electrode of the 2+m-th Hall device, the second ohmic electrode of the 3+m-th Hall device, and the 4+m-th Hall device The second Hall electrodes of the Hall device are connected to each other to form a current excitation signal input port;

The second ohmic electrode of the 1+m-th Hall device, the second Hall electrode of the 2+m-th Hall device, the first ohmic electrode of the 3+m-th Hall device, and the 4+m-th Hall device The first Hall electrodes of the Hall device are connected to each other to form a current excitation signal output port;

The first Hall electrode of the 1+m-th Hall device, the second ohmic electrode of the 2+m-th Hall device, the second Hall electrode of the 3+m-th Hall device, and the 4+m-th Hall device The first ohmic electrodes of the Hall device are connected to each other to form a first Hall potential detection port;

The second Hall electrode of the 1+m-th Hall device, the first ohmic electrode of the 2+m-th Hall device, the first Hall electrode of the 3+m-th Hall device, and the 4+m-th Hall device The second ohmic electrodes of the Hall device are connected to each other to form a second Hall potential detection port;

Wherein, m=4(M-1), and M is an integer greater than or equal to 1.

In order to achieve the above purpose, the present application also provides a method for preparing a vertical Hall device array, comprising the following steps:

Forming an N-type well on a P-type substrate;

Implanting high-energy N-type ions into the N-type well to form an N-type buried layer;

A trench structure is etched on the surface of the N-type well by dry etching;

An N+ region is formed on the surface of the N-type well by high-energy phosphorus ion implantation;

A metal electrode lead-out hole is etched on the surface of the N+ region, and a metal layer is deposited to form a metal contact.

Further, the step of etching the trench structure on the surface of the N-type well by dry etching further includes: using chemical vapor deposition to fill the trench area with silicon dioxide.

Compared with the prior art, the present application has the following advantages:

(1) Using an N-type buried layer structure, a low-resistance region can be introduced at the bottom of the N-type well. After the current flows into the device from the input electrode, the current will preferentially flow downward due to the attraction of the low-resistance buried layer region, and then flow out from the surface output electrode after forming a "U"-shaped path inside the device. As shown in Figure 4, after the current flows into the vertical Hall device from the first ohmic electrode, it will preferentially move down to the low-resistance region with the buried layer, then the current will move along the buried layer region, and finally flow out from the second ohmic electrode Vertical Hall device, so the current path is "U" shaped as a whole. The "U"-shaped current path can enhance the vertical current component in the vertical Hall device. According to the left-hand rule, the higher the longitudinal current ratio is, the more electrons in motion will be deflected by the Lorentz force, resulting in a larger Hall potential difference at the Hall electrodes and improving the measurement of the magnetic field. precision.

(2) A plurality of N-type buried layer structures with a certain distance are used to limit the current flow area flowing into the vertical Hall device array by using the characteristics that current tends to flow through the low resistance area, so that each vertical Hall device array is limited. The current flow path in the device is concentrated in the corresponding N-type buried layer region (as shown in Figure 5). Through the introduction of multiple N-type buried layers, multiple vertical Hall devices can ensure the independent flow of the internal current of each vertical Hall device under the condition of sharing one N-type well, and ensure the working state of each vertical Hall device. Stablize.

(3) The slot isolation structure between the device electrodes increases the surface equivalent resistance by extending the current path between the electrodes, which can not only achieve isolation between devices and block the flow of surface current, but also avoid the Short circuit effect caused by current flowing along a surface. The improvement of the surface resistance can further increase the longitudinal current component and improve the measurement accuracy of the magnetic induction of the device.

(4) The trench isolation structure on the surface of the vertical Hall device array and the N-type buried layer structure with multiple intervals inside realize the integration of multiple vertical Hall devices in one N-type well and the simultaneous integration of each vertical Hall device. The working states do not affect each other, which can effectively reduce the area of the vertical Hall array, reduce the area of the magnetic induction area, and improve the integration degree of the Hall chip.

Description of drawings

The accompanying drawings are used to provide further understanding of the application, and are used to explain the application together with the embodiments of the application, and do not constitute a limitation to the application:

1 is a top view of a vertical Hall device array of the application;

Fig. 2 is the vertical type Hall device array A-A' cross-sectional view of the present application of Fig. 1;

Fig. 3 is the vertical type Hall device array B-B' cross-sectional view of the present application of Fig. 1;

Fig. 4 is the current distribution schematic diagram of the vertical Hall device array A-A' section of the present application of Fig. 1;

Fig. 5 is the current distribution schematic diagram of the vertical Hall device array B-B' cross-section of the present application of Fig. 1;

FIG. 6 is a schematic diagram of an alternate connection method adopted by the vertical Hall device array of the present application.

FIG. 7 is a flow chart of the preparation method of the vertical Hall device array of the present application.

In the figure, P-type substrate 1, N-type well 2, N-type buried layer 3, trench isolation structure 4, device port 5, N+ region 6, first ohmic electrode 51, second ohmic electrode 52, first Hall electrode 53 and the second Hall electrode 54 .

Detailed ways

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for the purpose of A more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of the present application are only used for exemplary purposes, and are not used to limit the protection scope of the present application.

It should be understood that the various steps described in the method embodiments of the present application may be performed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of this application is not limited in this regard.

As used herein, the term "including" and variations thereof are open-ended inclusions, ie, "including but not limited to". The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below.

It should be noted that the modifications of "a" and "a plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, they should be understood as "one or a plurality of". multiple". "Plurality" should be understood to mean two or more.

Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

Example 1

In the embodiments of the present application, the vertical Hall device array uses a P-type material as a substrate, has an N-type well in the P-type substrate, and an N+ region is provided on the surface of the N-type well for realizing ohmic contact with the metal electrode; The metal electrodes of the vertical Hall device array are arranged according to certain lateral and vertical spacings to form a metal electrode array; the slot isolation structure between the metal electrodes isolates the metal electrode array to form electrodes of each vertical Hall device. A plurality of mutually independent N-type buried layers are arranged at the bottom of the N-type well, and the N-type buried layers are located directly under each vertical Hall device to form a vertical Hall device with a buried layer structure, and each vertical device constitutes Vertical Hall device array with segmented buried layer structure.

1 is a top view of the vertical Hall device array of the present application, FIG. 2 is a cross-sectional view of the vertical Hall device array AA' of the present application of FIG. 1 , and FIG. 3 is the vertical Hall device of the present application of FIG. 1 . The cross-sectional view of the array BB', as shown in Figures 1-3, the vertical Hall device array of the present application includes a P-type substrate 1, an N-type well 2, a plurality of N-type buried layers 3, and a plurality of vertical type Hall device, and the trench isolation structure 4, wherein,

N-type well 2 is located in P-type substrate 1;

A plurality of N-type buried layers 3 are arranged at the bottom of the N-type well 2 .

A plurality of vertical Hall devices are distributed in the N-type well 2 at equal intervals to form a vertical Hall device array.

The trench isolation structure 4, which is a multi-trench structure, is located on the surface of the N-type well 2 (the surface of the vertical Hall device array), and each trench is filled with silicon dioxide.

Each vertical Hall device includes an N-type buried layer 3 , a trench isolation structure 4 , a device port 5 , and an N+ region 6 .

A plurality of N+ regions for forming ohmic contact with the metal are provided on the top of the N-type well 2;

A metal electrode lead-out hole is formed on the upper part of each N+ region, and the metal layer forms a metal contact as the device port 5 .

In the embodiment of the present application, the number of vertical Hall devices in the N-type well 2 is 4*N, where N is a positive integer greater than or equal to 1.

In the embodiment of the present application, the number of N-type buried layers 3 is 4*N, where N is a positive integer greater than or equal to 1, and is consistent with the number of one vertical Hall device.

In the embodiment of the present application, each vertical Hall device has a five-port structure, which are respectively located directly above the N-type buried layer 3, wherein the two outer ports are short-circuited by metal wires, so that the five ports constitute four signal electrodes , which are the first ohmic electrode 51 , the second ohmic electrode 52 , the first Hall electrode 53 and the second Hall electrode 54 respectively.

Under the first ohmic electrode 51 , the second ohmic electrode 52 , the first Hall electrode 53 and the second Hall electrode 54 , N+ regions 6 composed of high-concentration N-type doping are respectively provided, so that the metal electrodes are connected to the N-type Well 2 forms an ohmic contact.

第一霍尔电极53和第一欧姆电极51之间的间距L3与第二欧姆电极52和第一霍尔电极53之间的间距L4的关系为:

In the embodiment of the present application, the relationship between the distance L1 between the vertical Hall devices and the width L2 of the N-type buried layer 3 is:

The relationship between the distance L3 between the first Hall electrode 53 and the first ohmic electrode 51 and the distance L4 between the second ohmic electrode 52 and the first Hall electrode 53 is:

In the embodiment of the present application, the trench depth (H) of the trench isolation structure 4 is greater than 0.5 μm.

FIG. 4 is a schematic diagram of the current distribution of the cross-section of the vertical Hall device array AA' of the present application in FIG. 1 . As shown in FIG. 4 , after the current flows into the vertical Hall device from the first ohmic electrode, it will preferentially move downward. To the low-resistance region with the buried layer, then the current will move along the buried layer region, and finally flow out of the vertical Hall device from the second ohmic electrode, so that the current path is "U" shaped as a whole. The "U"-shaped current path can enhance the vertical current component in the vertical Hall device. According to the left-hand rule, the higher the longitudinal current ratio is, the more electrons in motion will be deflected by the Lorentz force, resulting in a larger Hall potential difference at the Hall electrodes and improving the measurement of the magnetic field. precision.

FIG. 5 is a schematic diagram of the current distribution of the cross-section of the vertical Hall device array BB' of the present application in FIG. 1 . As shown in FIG. 5 , the vertical Hall device of the present application adopts an N-type buried layer structure. The characteristics that tend to flow through the low-resistance region restrict the current flow region flowing into the vertical Hall device array, so that the current flow paths in each vertical Hall device are concentrated in the corresponding N-type buried layer region (such as Figure 5). Through the introduction of multiple N-type buried layers, multiple vertical Hall devices can ensure the independent flow of the internal current of each vertical Hall device under the condition of sharing one N-type well, and ensure the working state of each vertical Hall device. Stablize.

FIG. 6 is a schematic diagram of the alternate connection method adopted by the vertical Hall device array of the present application. As shown in FIG. 6 , the alternate interconnection method is adopted between the signal electrodes of a plurality of vertical Hall devices in the vertical Hall device array of the present application. , the four signals flow through the four signal electrodes of the vertical Hall device alternately. The specific connection method is as follows:

(1) the first ohmic electrode 51 of the 1+m-th Hall device, the first Hall electrode 53 of the 2+m-th Hall device, the second ohmic electrode 52 of the 3+m-th Hall device, and The second Hall electrodes 54 of the 4+mth Hall devices are connected to each other to form a current excitation signal input port Iin. Wherein, m=4(M-1), and M is 1, 2, 3 . . .

(2) the second ohmic electrode 52 of the 1+m-th Hall device, the second Hall electrode 54 of the 2+m-th Hall device, the first ohmic electrode 51 of the 3+m-th Hall device, and The first Hall electrodes 53 of the 4+mth Hall devices are connected to each other to form a current excitation signal output port Iout. Wherein, m=4(M-1), and M is 1, 2, 3 . . .

(3) the first Hall electrode 53 of the 1st+mth Hall device, the second ohmic electrode 52 of the 2nd+mth Hall device, and the second Hall electrode 54 of the 3rd+mth Hall device, And the first ohmic electrodes 51 of the 4+mth Hall devices are connected to each other to form a first Hall potential detection port Vhall1. Wherein, m=4(M-1), and M is 1, 2, 3 . . .

(4) the second Hall electrode 54 of the 1st+mth Hall device, the first ohmic electrode 51 of the 2nd+mth Hall device, and the first Hall electrode 53 of the 3rd+mth Hall device, And the second ohmic electrodes 52 of the 4+mth Hall devices are connected to each other to form a second Hall potential detection port Vhall2; wherein, m=4(M−1), and M is 1, 2, 3 . . .

Example 2

FIG. 7 is a flow chart of the preparation method of the vertical Hall device array of the present application. The preparation method of the vertical Hall device array of the present application will be described in detail below with reference to FIG. 7 .

First, in the first step, the P-type substrate 1 is pre-cleaned, and then an N-type well 2 is formed by N-type ion implantation and then high-temperature annealing, as shown in (a) of FIG. 7 .

In the second step, the N-type buried layer 3 is formed by implanting high-energy N-type ions. As shown in (b) of FIG. 7 .

In the third step, dry etching is used to etch the trench structure 4 on the surface of the N-type well 2, as shown in (c) in FIG. 7; and then chemical vapor deposition is used to fill the trench area with silicon dioxide, As shown in (d) of FIG. 7 .

In the fourth step, an N+ region 6 is formed in the N-type well 2 by high-energy phosphorus ion implantation for forming an ohmic contact with the metal, as shown in (e) of FIG. 7 .

In the fifth step, a metal electrode lead-out hole is etched on the N+ region 6, a metal layer is deposited, and excess metal is etched to form a metal contact, as shown in (f) of FIG. 7 .

Finally, it should be noted that although the present application has been described in detail with reference to the embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or equate some of the technical features therein. Replacement, but any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (11)

1. a vertical type Hall device array, is characterized in that, comprises, P-type substrate; an N-type well disposed on the P-type substrate; a trench isolation structure, arranged on the surface of the N-type well; A plurality of vertical Hall devices are distributed on the N-type well at equal intervals; A plurality of the vertical Hall devices are connected by an alternate interconnection method. 2 . The vertical Hall device array according to claim 1 , wherein the number of the vertical Hall devices is 4N, wherein N is a positive integer greater than or equal to 1. 3 . 3 . The vertical Hall device array according to claim 1 , wherein the depth of the trench isolation structure is greater than 0.5 μm. 4 . 4. The vertical Hall device array according to claim 1, wherein the vertical Hall device further comprises an N-type buried layer disposed at the bottom of the N-type well, and an N-type buried layer located at the bottom of the N-type well. The port structure above the buried layer. 5. The vertical Hall device array according to claim 4, wherein the relationship between the distance between the vertical Hall devices and the width of the N-type buried layer is:

, Among them, L1 is the distance between the vertical Hall devices, and L2 is the width of the N-type buried layer. 6. The vertical Hall device array according to claim 4, wherein the port structure comprises a first ohmic electrode, a second ohmic electrode, a first Hall electrode, and a second Hall electrode, in, The second Hall electrodes are located at both ends of the port structure and are short-circuited through metal wires; An N+ region is provided under the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode The electrode, the first Hall electrode and the second Hall electrode respectively form ohmic contact with the N-type well. 7 . The vertical Hall device array according to claim 6 , wherein the trench isolation structure is located on the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the between the second Hall electrodes and between the vertical Hall devices. 8 . The vertical Hall device array according to claim 7 , wherein the distance between the first Hall electrode and the first ohmic electrode is the same as the distance between the second ohmic electrode and the first Hall electrode. 9 . The relationship of the spacing is:

, Wherein, L3 is the distance between the first Hall electrode and the first ohmic electrode, and L4 is the distance between the second ohmic electrode and the first Hall electrode. 9. The vertical Hall device array according to claim 1, wherein the plurality of vertical Hall devices are connected by an alternate interconnection method, comprising: The first ohmic electrode of the 1+m-th Hall device, the first Hall electrode of the 2+m-th Hall device, the second ohmic electrode of the 3+m-th Hall device, and the 4+m-th Hall device The second Hall electrodes of the Hall device are connected to each other to form a current excitation signal input port; The second ohmic electrode of the 1+m-th Hall device, the second Hall electrode of the 2+m-th Hall device, the first ohmic electrode of the 3+m-th Hall device, and the 4+m-th Hall device The first Hall electrodes of the Hall device are connected to each other to form a current excitation signal output port; The first Hall electrode of the 1+m-th Hall device, the second ohmic electrode of the 2+m-th Hall device, the second Hall electrode of the 3+m-th Hall device, and the 4+m-th Hall device The first ohmic electrodes of the Hall device are connected to each other to form a first Hall potential detection port; The second Hall electrode of the 1+m-th Hall device, the first ohmic electrode of the 2+m-th Hall device, the first Hall electrode of the 3+m-th Hall device, and the 4+m-th Hall device The second ohmic electrodes of the Hall device are connected to each other to form a second Hall potential detection port; Among them, m=4 (M-1), and M is an integer greater than or equal to 1. 10. A preparation method of a vertical Hall device array, comprising the following steps: Forming an N-type well on a P-type substrate; Implanting high-energy N-type ions into the N-type well to form an N-type buried layer; A trench structure is etched on the surface of the N-type well by dry etching; An N+ region is formed on the surface of the N-type well by high-energy phosphorus ion implantation; A metal electrode lead-out hole is etched on the surface of the N+ region, and a metal layer is deposited to form a metal contact. 11. The method for preparing a vertical Hall device array according to claim 10, wherein the step of using a dry etching method to etch a trench structure on the surface of the N-type well further comprises: using chemical Vapour deposition fills the trench areas with silicon dioxide.

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