CN115144740B - A power-on latch circuit, a power-on latch device and a power-on latch method - Google Patents

Abstract

The present invention discloses a power-on latch circuit, a power-on latch device and a power-on latch method, which relate to the technical field of digital circuits, and are used to latch the input signal of a target chip pin unit to reduce the occupation of chip pins. The power-on latch circuit includes a reset control unit, a latch control unit and a signal register unit. The output end of the reset control unit is electrically connected to the input end of the latch control unit, the output end of the latch control unit is electrically connected to the enable end of the signal register unit, the target chip pin unit is electrically connected to the data input end of the signal register unit, and the output end of the signal register unit is electrically connected to the external test mode signal end. The power-on latch device includes the power-on latch circuit mentioned in the above technical solution. The power-on latch circuit, the power-on latch device and the power-on latch method provided by the present invention are applied to digital circuits.

Description

A power-on latch circuit, a power-on latch device and a power-on latch method

Technical Field

The present invention relates to the field of digital circuits, and in particular to a power-on latching circuit, a power-on latching device and a power-on latching method.

Background Art

At present, with the rapid development of integrated circuits, the chip integration is getting higher and higher, resulting in increasingly complex logic scale and working mode. Chip-level DFT (Design for test) is becoming more and more important.

In existing DFT test solutions, it is usually necessary to provide a dedicated chip pin to provide the signal level of the test mode to control the chip to be in DFT mode or in functional mode. When the signal level input signal of the chip pin is signal "1", the chip is in DFT mode and the chip can be tested by DFT; when the signal level input signal of the chip pin is signal "0", the chip is in functional mode and the chip can work normally. However, after the chip is packaged and shipped, there is no need to switch to DFT mode to test the chip. The chip pin can only be used as an idle pin connected to signal "0". In the case of limited chip pins, it will cause a loss of chip pin resources.

Summary of the invention

The object of the present invention is to provide a power-on latch circuit, a power-on latch device and a power-on latch method for latching an input signal of a target chip pin unit to avoid the loss of chip pin resources.

In a first aspect, the present invention provides a power-on latch circuit for latching an input signal of a target chip pin unit, comprising a reset control unit, a latch control unit and a signal register unit. The output end of the reset control unit is electrically connected to the input end of the latch control unit, the output end of the latch control unit is electrically connected to the enable end of the signal register unit, the target chip pin unit is electrically connected to the data input end of the signal register unit, and the output end of the signal register unit is electrically connected to the external test mode signal end.

During the latching period, the reset control unit is used to provide a latching start signal to the latching control unit, and the latching control unit is used to generate a latching control signal under the action of the latching start signal, and send the latching control signal to the signal register unit; the signal register unit is used to latch the input signal of the target chip pin unit according to the latching control signal, and transmit the latched input signal to the external test mode signal terminal.

After the latching period, the latching control unit is further used to generate a latching stop signal and send the latching stop signal to the signal registering unit; the signal registering unit is used to stop latching the input signal of the target chip pin unit according to the latching stop signal.

Compared with the prior art, in the power-on latch circuit provided by the present invention, the output end of the reset control unit is electrically connected to the input end of the latch control unit, the output end of the latch control unit is electrically connected to the enable end of the signal register unit, the target chip pin unit is electrically connected to the data input end of the signal register unit, and the output end of the signal register unit is electrically connected to the external test mode signal end. Based on this, during the latch period, the reset control unit provides a latch start signal to the latch control unit, and the latch control unit can generate a latch control signal according to the latch start signal, and send the latch control signal to the signal register unit. The signal register unit can latch the input signal of the target chip pin unit according to the latch control signal, and finally transmit the latched input signal to the external test mode signal end. When the latched input signal is a signal "1", the signal received by the external test mode signal end is also a signal "1", and finally a signal "1" can be output to control the chip to be in DFT test mode. When the latched input signal is signal "0", the signal received by the external test mode signal terminal is also signal "0", and finally the signal "0" can be output to control the chip to be in the functional mode. After the latch period, the latch control unit can generate a latch stop signal, and send the latch stop signal to the signal register unit to stop latching the input signal of the latched target chip pin unit, so that the input signal jump of the target chip pin unit will not affect the signal received by the external test mode signal terminal, that is, no matter how the input signal of the target chip pin unit changes, the working mode of the chip will not be changed. Thus, the target chip pin unit can not only be used as other chip function pins, but also can provide a signal to the external test mode signal terminal through the power-on latch circuit provided by the present invention to complete the switching of the chip working mode. Compared with the prior art, a special chip pin needs to be set to switch the chip working mode. The present invention does not need to set a special chip pin, thereby avoiding the loss of chip pin resources.

In a second aspect, the present invention further provides a power-on latching device, comprising the power-on latching circuit described in the first aspect.

Compared with the prior art, the beneficial effects of the power-on latch device provided by the present invention are the same as the beneficial effects of the power-on latch circuit described in the above technical solution, which will not be described in detail here.

In a third aspect, the present invention further provides a power-on latching method, which is applied to the power-on latching circuit described in the first aspect, and the power-on latching method comprises:

During the latching period, the reset control unit is controlled to provide a latching start signal to the latching control unit;

In response to the latch start signal, the latch control unit provides a latch control signal to the signal register unit;

In response to the latch control signal, the signal register unit latches the input signal of the target chip pin unit and transmits the latched input signal to the external test mode signal terminal;

After the latching period, the latching control unit provides a latching stop signal to the signal registering unit;

In response to the latch stop signal, the signal register unit stops latching the input signal of the target chip pin unit.

Compared with the prior art, the beneficial effects of the power-on latching method provided by the present invention are the same as the beneficial effects of the power-on latching circuit described in the above technical solution, and will not be described in detail here.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

FIG1 is a power-on latch circuit provided in an embodiment of the present invention;

FIG. 2 is a timing diagram of a power-on latch circuit provided in an embodiment of the present invention.

Reference numerals:

1- Reset control unit, 11- Power-on reset module,

12-Reset synchronization module, 13-Filter module,

2-Latch control unit, 21-Counting register module,

211-counter, 212-second register,

22-clock module, 221-clock signal terminal,

222-Clock gate controller, 3-Signal register unit,

31-third register, 32-fourth register,

4-Target chip pin unit.

DETAILED DESCRIPTION

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

In the present invention, "at least one" means one or more, and "plurality" means two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

As shown in FIG. 1 , an embodiment of the present invention provides a power-on latch circuit for latching an input signal of a target chip pin unit 4 , including a reset control unit 1 , a latch control unit 2 and a signal register unit 3 .

The output end of the reset control unit 1 is electrically connected to the input end of the latch control unit 2, the output end of the latch control unit 2 is electrically connected to the enable end E of the signal register unit 3, the target chip pin unit 4 is electrically connected to the data input end D of the signal register unit 3, and the output end of the signal register unit 3 is electrically connected to the external test mode signal end TM.

During the latching period, the reset control unit 1 is used to provide a latching start signal to the latching control unit 2, and the latching control unit 2 is used to generate a latching control signal under the action of the latching start signal, and send the latching control signal to the signal register unit 3; the signal register unit 3 is used to latch the input signal of the target chip pin unit 4 according to the latching control signal, and transmit the latched input signal to the external test mode signal terminal TM.

After the latching period, the latching control unit 2 is further used to generate a latching stop signal and send the latching stop signal to the signal register unit 3; the signal register unit 3 is used to stop latching the input signal of the target chip pin unit 4 according to the latching stop signal.

In specific implementation: when it is necessary to latch the input signal of the target chip pin unit 4, the control reset control unit 1 generates a latch start signal, and sends the latch start signal to the latch control unit 2. Under the action of the latch start signal, the latch control unit 2 is started. After being started, the latch control unit 2 generates a latch control signal, and sends the latch control signal to the signal register unit 3. Under the action of the latch control signal, the signal register unit 3 latches the input signal of the target chip pin unit 4, that is, the input signal of the target chip pin unit 4 is stored in the signal register unit 3, and then provided to the external test mode signal terminal TM by the signal register unit 3. When the latched input signal is a signal "1", the signal received by the external test mode signal terminal TM is also a signal "1", and finally the signal "1" can be output, and the control chip is in the DFT test mode. When the latched input signal is a signal "0", the signal received by the external test mode signal terminal TM is also a signal "0", and finally the signal "0" can be output, and the control chip is in the functional mode. After the latching is completed, the latch control unit 2 generates a latch stop signal and sends the latch stop signal to the signal register unit 3. Under the action of the latch stop signal, the signal register unit 3 stops latching the input signal of the target chip pin unit 4, that is, no matter how the input signal of the target chip pin unit 4 changes, the input signal will not be stored by the chip register unit, nor will it affect the output signal of the external test mode signal terminal TM.

Through the circuit structure and specific implementation process of the above-mentioned power-on latch circuit, it can be known that in the power-on latch circuit provided by the embodiment of the present invention, the output end of the reset control unit 1 is electrically connected to the input end of the latch control unit 2, the output end of the latch control unit 2 is electrically connected to the enable end E of the signal register unit 3, the target chip pin unit 4 is electrically connected to the data input end D of the signal register unit 3, and the output end of the signal register unit 3 is electrically connected to the external test mode signal end TM. Based on this, during the latch period, the reset control unit 1 provides a latch start signal to the latch control unit 2, and the latch control unit 2 can generate a latch control signal according to the latch start signal, and send the latch control signal to the signal register unit 3. The signal register unit 3 can latch the input signal of the target chip pin unit 4 according to the latch control signal, and finally transmit the latched input signal to the external test mode signal end TM. When the latched input signal is a signal "1", the signal received by the external test mode signal end TM is also a signal "1", and finally a signal "1" can be output to control the chip to be in DFT test mode. When the latched input signal is signal "0", the signal received by the external test mode signal terminal TM is also signal "0", and finally the signal "0" can be output to control the chip to be in the functional mode. After the latch period, the latch control unit 2 can generate a latch stop signal, and send the latch stop signal to the signal register unit 3 to stop latching the input signal of the latch target chip pin unit 4, so that the input signal jump of the target chip pin unit 4 will not affect the signal received by the external test mode signal terminal TM, that is, no matter how the input signal of the target chip pin unit 4 changes, it will not change the working mode of the chip. Therefore, the target chip pin unit 4 can not only be used as other chip function pins, but also can provide a signal to the external test mode signal terminal TM through the power-on latch circuit provided by the embodiment of the present invention to complete the switching of the chip working mode. Compared with the prior art that needs to set a special chip pin to switch the chip working mode, the embodiment of the present invention does not need to set a special chip pin, thereby avoiding the loss of chip pin resources.

In practice, the target chip pin unit 4 includes a chip pin PIN0 and a silicon chip pin PAD0 electrically connected to the chip pin PIN0. The silicon chip pin PAD0 has three input and output terminals, namely, a PAD terminal, a C terminal and an I terminal, and also has an output enable OEN terminal for controlling the silicon chip pin to be in output mode or input mode. When the output enable OEN terminal is electrically connected to the signal "1", the silicon chip pin PAD0 is in input mode, that is, it receives the input signal from the PAD terminal and outputs the signal from the C terminal; when the output enable OEN terminal is electrically connected to the signal "0", the silicon chip pin PAD0 is in output mode, that is, it receives the signal from the I terminal and outputs the signal from the PAD terminal. In an embodiment of the present invention, when the chip pin PIN0 is electrically connected to the PAD end of the silicon chip pin PAD0, the output enable OEN end needs to be electrically connected to the signal "1" so that the input signal received by the chip pin PIN0 is transmitted to the data input end D of the signal register unit 3 through the C end of the silicon chip pin PAD0; when the chip pin PIN0 is electrically connected to the I end of the silicon chip pin PAD0, the output enable OEN end needs to be electrically connected to the signal "0" so that the input signal received by the chip pin PIN0 is transmitted to the data input end D of the signal register unit 3 through the PAD end of the silicon chip pin PAD0.

In a possible implementation, the reset control unit 1 includes a power-on reset module 11 and a reset synchronization module 12. The output end of the power-on reset module 11 is electrically connected to the data input end D of the reset synchronization module 12, and is used to provide a power-on reset signal to the reset synchronization module 12. The output end of the reset synchronization module 12 is electrically connected to the input end of the latch control unit 2, the reset end of the latch control unit 2, and the reset end of the signal register unit 3, and is used to provide a latch start signal to the input end of the latch control unit 2, the reset end of the latch control unit 2, and the reset end of the signal register unit 3 according to the power-on reset signal. The latch start signal is used to control the latch control unit 2 to start, and control the latch control unit 2 and the signal register unit 3 to stop resetting.

In specific implementation, when the input signal of the target chip pin unit 4 needs to be latched, the power-on reset module 11 is first controlled to be powered on. During the power-on process of the power-on reset module 11, its output is a signal "0". After the reset synchronization module 12 receives the signal "0", the signal "0" is transmitted to the input end of the latch control unit 2, the reset end of the latch control unit 2, and the reset end of the signal register unit 3. Since the reset end is generally low-level valid, when the signal "0" is received, the latch control unit 2 and the signal register unit 3 are always maintained in the reset state under the action of the low-level signal "0". After the power-on reset module 11 is powered on, its output signal jumps to a signal "1" after a delay of milliseconds. At this time, the signal "1" is the power-on reset signal generated by the power-on reset module 11. The reset synchronization module 12 provides a latch start signal to the input end of the latch control unit 2, the reset end of the latch control unit 2 and the reset end of the signal register unit 3 according to the received signal "1". At this time, the latch start signal is signal "1". After receiving the high-level signal "1", the latch control unit 2 and the signal register unit 3 stop resetting, and the latch control unit 2 is started under the action of the signal "1".

Based on this, when the input signal of the target chip pin unit 4 needs to be latched, the power-on reset module 11 is controlled to be powered on, and then the signal "1" generated after the power-on reset module 11 is powered on is used to control the latch signal circuit to be in the latch period. For example, when the input signal of the target chip pin unit 4 is signal "0", if the signal "0" needs to be latched at this time, the power-on reset module 11 needs to be controlled to be powered on.

It is understandable that, within a latching period, the signal register unit 3 can only latch the input signal of the target chip pin unit 4 within the period. After the last latching period ends, if the input signal of the current target chip pin unit 4 needs to be latched, the power-on reset module 11 needs to be controlled to be powered on again to control the latch signal circuit to enter another latching period.

In some embodiments, as shown in Figure 1, the reset control unit 1 also includes a filtering module 13, the data input end of the filtering module 13 is electrically connected to the output end of the power-on reset module 11, and the output end of the filtering module 13 is electrically connected to the data input end of the reset synchronization module 12. The filtering module 13 is used to filter the power-on reset signal and transmit the filtered power-on reset signal to the reset synchronization module 12.

It should be understood that during the power-on process, the output jitter of the power supply will directly affect the power-on reset signal output by the power-on reset module 11, causing the power-on reset signal to jump unnecessarily, which in turn causes the latch start signal to jump. For example, when the latch start signal is a signal "1", if it jumps to a signal "0", the latch signal control unit and the signal register unit 3 will be reset, causing latch confusion. Based on this, the filter module 13 can filter the output signal of the power-on reset module 11, filter out the burrs in the power-on reset signal, so that the power-on reset signal can always maintain a stable output of the signal "1". In practice, in order to avoid circuit abnormalities caused by timing problems or metastable problems in the power-on latch circuit, the reset synchronization module 12 needs to delay several clock cycles after receiving the power-on reset signal after passing through the filter module 13, and then synchronously output the latch start signal. The specific number of delayed cycles is related to the frequency of the clock signal in the actual application, and the embodiment of the present invention does not limit this.

In one embodiment, as shown in FIG1 , the filter module 13 includes a plurality of first registers and an OR gate. The plurality of first registers are connected in series, and the output of each first register is also electrically connected to the corresponding input of the OR gate, and the output of the OR gate is electrically connected to the input of the reset synchronization module 12 .

Exemplarily, as shown in FIG1 , the filtering module 13 may include three first registers, the three first registers are connected end to end in sequence, and the output ends of the three first registers are electrically connected to the input end of the OR gate. When the power-on reset module 11 is powered on, its output signal becomes a signal "1", at which time, the signal "1" is a power-on reset signal generated by the power-on reset module 11. After the first first register receives the signal "1", the signal "1" is transmitted to the second first register, and the signal "1" is also transmitted to the first input end of the OR gate. After the second first register receives the signal "1", the signal "1" is transmitted to the third first register, and the signal "1" is also transmitted to the second input end of the OR gate. After the third first register receives the signal "1", the signal "1" is transmitted to the third input end of the OR gate. After one of the input ends of the OR gate receives the "signal 1", the signal "1" is transmitted to the reset synchronization module 12. If during the process of the power-on reset module 11 outputting the signal "1", the signal jumps due to the presence of glitches, so that the first first register receives the signal "0", since the register will only collect the signal of the data input terminal D to the output terminal when the rising edge of the clock signal arrives, at this time, the signal sent by the second first register to the third first register is still the signal "1", and the signal sent by the second first register to the OR gate is also the signal "1", so that the OR gate can continue to output the signal "1". Based on this, the filter circuit can filter out the low-level glitches in the power-on reset signal, so that the reset synchronization module 12 can receive a stable power-on reset signal. It can be understood that the filter module 13 can also include 2, 4 or 5 first registers, and the embodiment of the present invention does not specifically limit this.

In a possible implementation, as shown in FIG1 , the latch control unit 2 includes a counting register module 21 and a clock module 22. The input end of the counting register module 21 is electrically connected to the output end of the reset control unit 1, and is used to start counting under the control of the latch start signal. The reset end of the counting register module 21 is electrically connected to the output end of the reset control unit 1, and is used to stop resetting under the action of the latch start signal.

The first output end of the counting register module 21 is electrically connected to the enable end E of the clock module 22, and is used to control the clock module 22 to turn on. The first output end of the clock module 22 is electrically connected to the counting end of the counting register module 21. The counting register module 21 is used to count the output signal of the clock module 22; the counting register module 21 is also used to control the clock module 22 to turn off when the counting value of the counting register module 21 reaches the target value.

The second output end of the counting register module 21 is electrically connected to the enable end E of the signal register unit 3, and is used to generate a latch control signal when the count value of the counting register module 21 reaches the target value. The latch control signal is used to control the signal register unit 3 to latch the input signal of the target chip pin unit 4.

After the latching period, the counting register module 21 is further used to generate a latching stop signal, and the latching stop signal is used to control the signal register unit 3 to stop latching the input signal of the target chip pin unit 4.

The second output end of the clock module 22 is electrically connected to the clock input end of the reset control unit 1, the clock input end of the counting register module 21 and the clock input end of the signal register unit 3 respectively, and is used to provide a clock signal to the reset control unit 1, the counting register module 21 and the signal register unit 3.

In specific implementation, after the counting register module 21 receives the signal "1" sent by the reset synchronization module 12, it starts counting, and stops resetting under the action of the signal "1". At this time, after the counting register module 21 stops resetting, the first output terminal of the counting register module 21 outputs the signal "1", and after the enable terminal E of the clock module 22 receives the signal "1", the clock module 22 is turned on and outputs the signal to the counting terminal of the counting register module 21. The counting register module 21 counts the output signal of the clock module 22. When the count value of the counting register module 21 reaches the target value, that is, the counting register module 21 counts fully, the first output terminal of the counting register module 21 outputs the signal "0", and after the enable terminal E of the clock module 22 receives the signal "0", the clock module 22 is turned off. At the same time, after the counting register module 21 is started, before the counting register module 21 counts fully, the second output end of the counting register module 21 outputs a signal "0" to the enable end E of the signal register unit 3. When the enable end E of the signal register unit 3 receives the signal "0", the signal received by the data input end D will not be stored. After the counting register module 21 counts fully, the second output end of the counting register module 21 outputs a signal "1" to the enable end E of the signal register unit 3. Only after the enable end E of the signal register unit 3 receives the signal "1" will the signal received by the data input end D be stored.

After the input signal of the target pin unit is stored in the signal register unit 3, the latch period ends, and the second output end of the counting register module 21 outputs a signal "0" to the enable end E of the signal register unit 3 to stop latching the input signal of the target chip pin unit 4. After the latch period, the signal register unit 3 will not register the input signal of the target chip pin unit 4. At this time, no matter how the input signal of the target chip pin unit 4 changes, it will not affect the output signal of the signal register unit 3.

In some embodiments, as shown in FIG1 , the counting register module 21 includes a counter 211 and a second register 212. The input terminal and the reset terminal of the counter 211 are electrically connected to the output terminal of the reset control unit 1, the first output terminal Q1 of the counter 211 is electrically connected to the enable terminal E of the clock module 22, the first output terminal Q of the clock module 22 is electrically connected to the counting terminal of the counter 211, and the counter 211 is used to control the clock module 22 to turn on under the control of the latch start signal, and count the output signal of the clock module 22.

The second output terminal Q2 of the counter 211 is electrically connected to the data input terminal of the second register 212, and the output terminal of the second register 212 is electrically connected to the enable terminal E of the signal register unit 3. The second register 212 is used to transmit the latch control signal or latch stop signal generated by the counter 211 to the enable terminal E of the signal register unit 3.

The second output terminal of the clock module 22 is also electrically connected to the clock input terminal of the second register 212 for providing a clock signal to the second register 212 .

In specific implementation, after the counter 211 receives the signal "1" sent by the reset synchronization module 12, it starts counting, and the counter 211 and the second register 212 stop resetting under the action of the signal "1". At this time, after the counter 211 stops resetting, the first output terminal Q1 of the counter 211 outputs the signal "1", and after the enable terminal E of the clock module 22 receives the signal "1", the clock module 22 is turned on and outputs the signal to the counting terminal of the counter 211. The counter 211 counts the output signal of the clock module 22. When the count value of the counter 211 reaches the target value, that is, the counter 211 counts fully, the first output terminal Q1 of the counter 211 outputs the signal "0", and after the enable terminal E of the clock module 22 receives the signal "0", the clock module 22 is turned off. At the same time, after the counter 211 is started and before the counter 211 counts fully, the second output terminal Q2 of the counter 211 outputs a signal "0" to the second register 212. When the rising edge of the clock signal arrives, the second register 212 transmits the signal "0" to the enable terminal E of the signal register unit 3. At this time, the signal register unit 3 does not store the signal received by the data input terminal D. After the counter 211 counts fully, the second output terminal of the counter 211 outputs a signal "1" to the second register 212. When the rising edge of the clock signal arrives, the second register 212 transmits the signal "1" to the enable terminal E of the signal register unit 3. After the enable terminal E of the signal register unit 3 receives the signal "1", it stores the signal received by the data input terminal.

In some embodiments, as shown in FIG1 , the clock module 22 includes a clock gate controller 222 and a clock signal terminal 221. The clock signal terminal 221 is electrically connected to the clock input terminal of the reset control unit 1, the clock input terminal of the counting register module 21, the clock input terminal of the signal register unit 3, and the clock input terminal CP of the clock gate controller 222, respectively, and is used to provide a clock signal to the reset control unit 1, the counting register module 21, the signal register unit 3, and the clock gate controller 222.

The enable terminal E of the clock gating controller 222 is electrically connected to the first output terminal of the counting register module 21 , and the output terminal of the clock gating controller 222 is electrically connected to the counting terminal of the counting register module 21 .

In a specific implementation, when the enable terminal E of the clock gate controller 222 receives the signal "1" output by the counter 211, the clock gate controller 222 is turned on, and the clock signal terminal 221 provides a clock signal to the counter 211 through the clock gate controller 222. The counter 211 counts the clock signal. For example, the cycle of 1 clock signal is recorded as 1, and the cycle of 2 clock signals is recorded as 2. Therefore, when the counter 211 is full, the counter 211 outputs a signal "0" to the enable terminal E of the clock gate controller to control the clock gate controller 222 to be closed, so that the counter 211 stops counting.

In practical applications, the clock signal terminal 221 is used to provide a clock signal to the reset control unit 1, the counting register module 21, the signal register unit 3 and the clock gate controller 222. Using the same clock signal terminal 221 to provide a clock signal can avoid the timing confusion of the latch circuit to the greatest extent. The clock signal provided by the clock signal terminal 221 can be generated using a crystal oscillator clock.

In a possible implementation, as shown in FIG1 , the signal register unit 3 includes a third register 31 and a fourth register 32. The output end of the latch control unit 2 is electrically connected to the enable end E of the third register 31, the data input end D of the third register 31 is electrically connected to the target chip pin unit 4, and the output end of the third register 31 is electrically connected to the data input end D of the fourth register 32. The output end of the fourth register 32 is electrically connected to the external test mode signal end TM.

Specifically, when the enable terminal E of the third register 31 receives a signal "0", the third register 31 is in a non-enabled state. At this time, regardless of whether the rising edge of the clock signal arrives, the third register 31 will not transmit the signal received by the data input terminal D to the output terminal Q. When the enable terminal E of the third register 31 receives a signal "1", the third register 31 is in an enabled state. At this time, when the rising edge of the clock signal arrives, the third register 31 will transmit the signal received by the data input terminal D to the output terminal Q. After receiving the signal, the fourth register 32 will transmit the collected signal to the output terminal Q when the rising edge of the next clock cycle arrives, and then provide the signal to the external test mode signal terminal TM.

It should be noted that the first register, the second register 212, the third register 31 and the fourth register 32 in the above embodiments may be rising edge registers, that is, the signal at the data input terminal D can be transmitted to the output terminal Q only when the rising edge of the clock signal arrives, or the first register, the second register 212, the third register 31 and the fourth register 32 in the above embodiments may be falling edge registers, that is, the signal at the data input terminal D can be transmitted to the output terminal Q only when the falling edge of the clock signal arrives, and the embodiments of the present invention do not make specific limitations on this.

1 and 2 , taking the input signal of the target chip pin unit 4 as a signal “1” as an example, the working principle of the power-on latch circuit provided by the embodiment of the present invention will be described in detail. The following description is only for explanation and is not intended to be limiting.

First, the power-on reset module 11 is controlled to power on the chip, and the clock signal terminal 221 provides a clock signal.

During the power-on process, the power-on reset module 11 outputs a signal "0"; the output signals of the multiple first registers in the filtering module 13 and the reset synchronization module 12 are all signal "0"; the counting end and the reset end of the counter 211 simultaneously receive the signal "0", the reset end of the counter 211 takes effect and is in a reset state, the first output end Q1 of the counter 211 outputs a signal "1" by default, and the second output end Q2 outputs a signal "0" by default, the reset end of the second register 212, the reset end of the third register 31 and the reset end of the fourth register 32 receive the signal "0", the reset end takes effect, the second register 212, the third register 31 and the fourth register 32 are all in a reset state, and the output is a signal "0", and the external test mode signal end TM also receives a signal "0".

After power-on is completed, the output signal of the power-on reset module 11 changes from signal "0" to signal "1", the output signal of the filter module 13 changes from signal "0" to signal "1", and the output signal in the reset synchronization module 12 changes from signal "0" to signal "1". Finally, the signals received by the counting end and reset end of the counter 211, the reset end of the second register 212, the reset end of the third register 31, and the reset end of the fourth register 32 all change from signal "0" to signal "1". At this time, the chip is in a non-reset state, and the counter 211 starts counting. The first output end Q1 of the counter 211 and the second output end Q2 of the counter 211 are still in the initial state, that is, Q1=1, Q2=0, the gating of the clock gating controller 222 is still open, and the signal received by the enable end E of the third register 31 is still signal "0", which is in a non-enabled state.

When the counter 211 counts full in the current clock cycle, the first output terminal Q1 of the counter 211 is 1, and the second output terminal Q2 of the counter 211 is 1. At this time, the input terminal of the second register 212 starts to change to a signal “1”.

In the second clock cycle after the counter 211 counts full, the first output terminal Q1 of the counter 211 is 0, the clock gate controller 222 is closed, and the counter 211 stops counting. The second output terminal Q2 of the counter 211 is 0, and when the rising edge of the clock signal arrives, the second register 212 collects the signal "1" received at the data input terminal in the previous cycle to the output terminal, so that the signal received by the enable terminal E of the third register 31 is signal "1", and the third register 31 is in the enabled state. Afterwards, the data input terminal of the second register 212 becomes signal "0" again.

In the third clock cycle after the counter 211 is full, since the signal received by the enable terminal E of the third register 31 in the second clock cycle is signal "1", the signal received by the data input terminal D of the third register 31, that is, the input signal of the target chip pin unit 4, can be transmitted to the output terminal Q of the third register 31 in the third clock cycle. At this time, the output terminal of the second register 212 collects the second output terminal Q2=0 of the counter 211 in the second clock cycle, and the enable terminal E of the third register 31 is also signal "0".

In the 4th clock cycle after the counter 211 is full, the fourth register 32 collects the output of the third register 31 in the 3rd clock cycle, which is the input signal of the target chip pin unit 4. Since the enable terminal E of the third register 31 receives the signal "0", the output terminal Q of the third register 31 always keeps the output signal of the target chip pin unit 4 in the 3rd clock cycle after the counter 211 is full unchanged.

After the latching process is completed, unless the power-on reset module 11 is powered on again, the fourth register 32 keeps outputting the input signal of the target chip pin unit 4 during the latching period.

An embodiment of the present invention further provides a power-on latching device, comprising the power-on latching circuit provided in the above embodiment.

Compared with the prior art, the beneficial effects of the power-on latch device provided by the embodiment of the present invention are the same as the beneficial effects of the power-on latch circuit described in the above technical solution, which will not be described in detail here.

An embodiment of the present invention further provides a power-on latching method, which is applied to the power-on latching circuit provided in the above embodiment. The power-on latching method includes:

During the latching period, the reset control unit is controlled to provide a latching start signal to the latching control unit;

In response to the latch start signal, the latch control unit provides a latch control signal to the signal register unit;

In response to the latch control signal, the signal register unit latches the input signal of the target chip pin unit and transmits the latched input signal to the external test mode signal terminal;

After the latching period, the latching control unit provides a latching stop signal to the signal registering unit;

In response to the latch stop signal, the signal register unit stops latching the input signal of the target chip pin unit.

Compared with the prior art, the beneficial effects of the power-on latching method provided by the embodiment of the present invention are the same as the beneficial effects of the power-on latching circuit described in the above technical solution, which will not be described in detail here.

Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims (9)

1. A power-on latch circuit, characterized in that it is used to latch the input signal of the target chip pin unit, comprising a reset control unit, a latch control unit and a signal register unit, wherein: The output end of the reset control unit is electrically connected to the input end of the latch control unit, the output end of the latch control unit is electrically connected to the enable end of the signal register unit, the target chip pin unit is electrically connected to the data input end of the signal register unit, and the output end of the signal register unit is electrically connected to the external test mode signal end; The reset control unit includes a power-on reset module and a reset synchronization module, wherein: The output end of the power-on reset module is electrically connected to the data input end of the reset synchronization module, and is used to provide a power-on reset signal to the reset synchronization module; the output end of the reset synchronization module is electrically connected to the input end of the latch control unit, the reset end of the latch control unit, and the reset end of the signal register unit, and is used to provide a latch start signal to the input end of the latch control unit, the reset end of the latch control unit, and the reset end of the signal register unit according to the power-on reset signal; During the latch period, the reset control unit is used to provide a latch start signal to the latch control unit, and the latch control unit is used to generate a latch control signal under the action of the latch start signal, and send the latch control signal to the signal register unit; the signal register unit is used to latch the input signal of the target chip pin unit according to the latch control signal, and transmit the latched input signal to the external test mode signal terminal; After the latch period, the latch control unit is further used to generate a latch stop signal and send the latch stop signal to the signal register unit; the signal register unit is used to stop latching the input signal of the target chip pin unit according to the latch stop signal. 2. The power-on latch circuit according to claim 1 is characterized in that the reset control unit also includes a filtering module, a data input end of the filtering module is electrically connected to an output end of the power-on reset module, an output end of the filtering module is electrically connected to a data input end of the reset synchronization module, and the filtering module is used to filter the power-on reset signal and transmit the filtered power-on reset signal to the reset synchronization module. 3. The power-on latch circuit according to claim 2, wherein the filtering module comprises a plurality of first registers and an OR gate, wherein: The multiple first registers are connected in series, and the output end of each of the first registers is also electrically connected to the corresponding input end of the OR gate, and the output end of the OR gate is electrically connected to the input end of the reset synchronization module. 4. The power-on latch circuit according to claim 1, wherein the latch control unit comprises a counting register module and a clock module, wherein: The input end of the counting register module is electrically connected to the output end of the reset control unit, and is used to start counting under the control of the latch start signal; the reset end of the counting register module is electrically connected to the output end of the reset control unit, and is used to stop resetting under the action of the latch start signal; The first output end of the counting register module is electrically connected to the enable end of the clock module, and is used to control the clock module to be turned on. The first output end of the clock module is electrically connected to the counting end of the counting register module, and the counting register module is used to count the output signal of the clock module; the counting register module is also used to control the clock module to be turned off when the count value of the counting register module reaches the target value; The second output end of the counting register module is electrically connected to the enable end of the signal register unit, and is used to generate the latch control signal when the count value of the counting register module reaches the target value, and the latch control signal is used to control the signal register unit to latch the input signal of the target chip pin unit; After the latch period, the counting register module is further used to generate the latch stop signal, and the latch stop signal is used to control the signal register unit to stop latching the input signal of the target chip pin unit; The second output end of the clock module is electrically connected to the clock input end of the reset control unit, the clock input end of the counting register module and the clock input end of the signal register unit respectively, and is used to provide a clock signal to the reset control unit, the counting register module and the signal register unit. 5. The power-on latch circuit according to claim 4, characterized in that the counting register module comprises a counter and a second register, wherein: The input terminal and the reset terminal of the counter are both electrically connected to the output terminal of the reset control unit, the first output terminal of the counter is electrically connected to the enable terminal of the clock module, the first output terminal of the clock module is electrically connected to the counting terminal of the counter, and the counter is used to control the clock module to turn on under the control of the latch start signal and count the output signal of the clock module; The second output end of the counter is electrically connected to the data input end of the second register, the output end of the second register is electrically connected to the enable end of the signal register unit, and the second register is used to transmit the latch control signal or the latch stop signal generated by the counter to the enable end of the signal register unit; The second output terminal of the clock module is also electrically connected to the clock input terminal of the second register, and is used to provide the clock signal to the second register. 6. The power-on latch circuit according to claim 4, characterized in that the clock module comprises a clock gate controller and a clock signal terminal, wherein: The clock signal terminal is electrically connected to the clock input terminal of the reset control unit, the clock input terminal of the counting register module, the clock input terminal of the signal register unit and the clock input terminal of the clock gate controller, respectively, and is used to provide the clock signal to the reset control unit, the counting register module, the signal register unit and the clock gate controller; The enable end of the clock gating controller is electrically connected to the first output end of the counting register module, and the output end of the clock gating controller is electrically connected to the counting end of the counting register module. 7. The power-on latch circuit according to claim 1, wherein the signal register unit comprises a third register and a fourth register, wherein: The output end of the latch control unit is electrically connected to the enable end of the third register, the data input end of the third register is electrically connected to the target chip pin unit, and the output end of the third register is electrically connected to the data input end of the fourth register; The output terminal of the fourth register is electrically connected to the external test mode signal terminal. 8. A power-on latch device, characterized by comprising the power-on latch circuit according to any one of claims 1 to 7. 9. A power-on latching method, characterized in that it is applied to the power-on latching circuit according to any one of claims 1 to 7, and the power-on latching method comprises: During the latching period, the reset control unit is controlled to provide a latching start signal to the latching control unit; In response to the latch start signal, the latch control unit provides a latch control signal to the signal register unit; In response to the latch control signal, the signal register unit latches the input signal of the target chip pin unit, and transmits the latched input signal to the external test mode signal terminal; After the latch period, the latch control unit provides a latch stop signal to the signal register unit; In response to the latch stop signal, the signal register unit stops latching the input signal of the target chip pin unit.