CN115019731B

CN115019731B - Driving circuit, driving method, driving module and display device

Info

Publication number: CN115019731B
Application number: CN202210691387.4A
Authority: CN
Inventors: 袁粲; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-06-17
Filing date: 2022-06-17
Publication date: 2025-04-01
Anticipated expiration: 2042-06-17
Also published as: CN115019731A

Abstract

The invention provides a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a first node control circuit, a second node control circuit, a control node control circuit and an output circuit, wherein the first node control circuit controls the potential of a first node, the control node control circuit controls the potential of a control node according to a second clock signal under the control of a first scanning control signal, a first control voltage, a second scanning control signal and a second control voltage, the control node control circuit is connected or disconnected with a first voltage end under the control of the second clock signal to maintain the potential of the control node, the second node control circuit controls the potential of a second node, and the output circuit controls the driving signal output end to output a driving signal under the control of the potential of the first node and the potential of the second node. The invention can realize the adjustable pulse width of the driving signal output by the device and can be applied to forward scanning and backward scanning.

Description

Driving circuit, driving method, driving module and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method, a driving module, and a display device.

Background

In recent years, with the advancement of intelligent display technology, an Organic LIGHT EMITTING Diode (OLED) has become one of the hot spots in the current display research field, and with the thinning of a display panel, a frame has become narrower, so that the optimal design of the display panel has become more and more serious.

The related driving circuit cannot realize the pulse width adjustment of the driving signal outputted by the driving circuit, and cannot be applied to both forward scanning and backward scanning.

Disclosure of Invention

In one aspect, an embodiment of the present invention provides a driving circuit including a first node control circuit, a second node control circuit, a control node control circuit, and an output circuit;

The first node control circuit is used for controlling the potential of the first node according to the first control voltage provided by the first control voltage end and the second control voltage provided by the second control voltage end under the control of a first scanning control signal provided by the first scanning control end, a first clock signal provided by the first clock signal end and a second scanning control signal provided by the second scanning control end;

The control node control circuit is used for controlling the potential of a control node according to a second clock signal provided by a second clock signal end under the control of the first scanning control signal, the first control voltage, the second scanning control signal and the second control voltage, controlling the connection or disconnection between the control node and the first voltage end under the control of the second clock signal, and maintaining the potential of the control node;

The second node control circuit is electrically connected with the first node, the second node, the connection node, the control node, the first clock signal end and the second voltage end respectively and is used for controlling the connection or disconnection between the second node and the second voltage end under the control of the potential of the first node, controlling the connection or disconnection between the first clock signal end and the connection node under the control of the potential of the control node and controlling the connection or disconnection between the connection node and the second node under the control of the first clock signal;

The output circuit is respectively and electrically connected with the first node, the second node, the first voltage end, the second voltage end and the driving signal output end, and is used for controlling the connection or disconnection between the driving signal output end and the first voltage end under the control of the potential of the first node, and controlling the connection or disconnection between the driving signal output end and the second voltage end under the control of the potential of the second node.

Optionally, the driving circuit according to at least one embodiment of the present invention further includes a first tank circuit and a second tank circuit;

the first end of the first energy storage circuit is electrically connected with the first node, and the second end of the first energy storage circuit is electrically connected with the driving signal output end and is used for controlling the potential of the first node according to the driving signal output by the driving signal output end;

the second energy storage circuit is electrically connected with the second node and is used for maintaining the potential of the second node.

Optionally, the first node control circuit is electrically connected with a first node, a first control voltage end, a second control voltage end, a first scanning control end, a second scanning control end and a first clock signal end, and is used for controlling the first node to be connected with or disconnected from the first control voltage end under the control of a first scanning control signal provided by the first scanning control end and a first clock signal provided by the first clock signal end, and controlling the first node to be connected with or disconnected from the second control voltage end under the control of a second scanning control signal provided by the second scanning control end and the first clock signal;

The control node control circuit is respectively and electrically connected with the control node, the first control voltage end, the second control voltage end, the first scanning control end, the second clock signal end and the first voltage end, and is used for controlling the connection or disconnection between the control node and the second clock signal end under the control of the first scanning control signal and the first control voltage provided by the first control voltage end, and controlling the connection or disconnection between the control node and the second clock signal end under the control of the second scanning control signal and the second control voltage provided by the second control voltage end, and controlling the connection or disconnection between the control node and the first voltage end under the control of the second clock signal provided by the second clock signal end.

Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

The control electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the first control voltage end, and the second electrode of the first transistor is electrically connected with the first electrode of the second transistor;

the control electrode of the second transistor is electrically connected with the first scanning control end, and the second electrode of the second transistor is electrically connected with the first node;

A control electrode of the third transistor is electrically connected with the second scanning control end, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor;

The control electrode of the fourth transistor is electrically connected with the first clock signal end, and the second electrode of the fourth transistor is electrically connected with the second control voltage end.

Optionally, the driving circuit according to at least one embodiment of the present invention further includes a first leakage preventing circuit;

The first leakage protection circuit is electrically connected with the first node, the first voltage end, the second pole of the first transistor and the second pole of the third transistor respectively, and is used for controlling the communication between the first voltage end and the second pole of the first transistor and the communication between the first voltage end and the second pole of the third transistor under the control of the potential of the first node.

Optionally, the control node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a storage capacitor;

the control electrode of the fifth transistor is electrically connected with the first control voltage end, the first electrode of the fifth transistor is electrically connected with the second clock signal end, and the second electrode of the fifth transistor is electrically connected with the first electrode of the sixth transistor;

The control electrode of the sixth transistor is electrically connected with the first scanning control end, and the second electrode of the sixth transistor is electrically connected with the control node;

a control electrode of the seventh transistor is electrically connected with the second scanning control end, a first electrode of the seventh transistor is electrically connected with the control node, and a second electrode of the seventh transistor is electrically connected with a first electrode of the eighth transistor;

The control electrode of the eighth transistor is electrically connected with the second control voltage end, and the second electrode of the eighth transistor is electrically connected with the second clock signal end;

a control electrode of the ninth transistor is electrically connected with the second clock signal end, a first electrode of the ninth transistor is electrically connected with the first voltage end, and a second electrode of the ninth transistor is electrically connected with the control node;

the first end of the storage capacitor is electrically connected with the control node, and the second end of the storage capacitor is electrically connected with the connection node.

Optionally, the second node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

The control electrode of the tenth transistor is electrically connected with the control node, the first electrode of the tenth transistor is electrically connected with the first clock signal end, and the second electrode of the tenth transistor is electrically connected with the connection node;

The control electrode of the eleventh transistor is electrically connected with the first clock signal end, the first electrode of the eleventh transistor is electrically connected with the connection node, and the second electrode of the eleventh transistor is electrically connected with the second node;

The control electrode of the twelfth transistor and the control electrode of the thirteenth transistor are electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the second voltage end, the second electrode of the twelfth transistor is electrically connected with the first electrode of the thirteenth transistor, and the second electrode of the thirteenth transistor is electrically connected with the second node.

Optionally, the output circuit includes a first output transistor and a second output transistor;

The control electrode of the first output transistor is electrically connected with the first node, the first electrode of the first output transistor is electrically connected with the first voltage end, and the second electrode of the first output transistor is electrically connected with the driving signal output end;

The control electrode of the second output transistor is electrically connected with the second node, the first electrode of the second output transistor is electrically connected with the driving signal output end, and the second electrode of the second output transistor is electrically connected with the second voltage end.

Optionally, the output circuit includes a first output transistor, a second output transistor, and a third output transistor;

The control electrode of the second output transistor is electrically connected with the second node, the first electrode of the second output transistor is electrically connected with the driving signal output end, and the second electrode of the second output transistor is electrically connected with the first electrode of the third output transistor;

the control electrode of the third output transistor is electrically connected with the second node, and the second electrode of the third output transistor is electrically connected with the second voltage end.

Optionally, the driving circuit according to at least one embodiment of the present invention further includes a second leakage preventing circuit;

The second leakage protection circuit is respectively and electrically connected with the driving signal output end, the first voltage end and the second pole of the second output transistor, and is used for controlling the communication between the first voltage end and the second pole of the second output transistor under the control of the driving signal provided by the driving signal output end.

Optionally, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the driving signal output end;

the first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the second voltage end.

Optionally, the first leakage protection circuit includes a fourteenth transistor;

The control electrode of the fourteenth transistor is electrically connected with the first node, the first electrode of the fourteenth transistor is electrically connected with the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected with the second electrode of the first transistor and the second electrode of the third transistor.

Optionally, the second leakage protection circuit includes a fifteenth transistor;

the control electrode of the fifteenth transistor is electrically connected with the driving signal output end, the first electrode of the fifteenth transistor is electrically connected with the first voltage end, and the second electrode of the fifteenth transistor is electrically connected with the second electrode of the second output transistor.

Optionally, the driving circuit according to at least one embodiment of the present invention further includes a driving output terminal, an output resistor, and an output capacitor;

The first end of the output resistor is electrically connected with the output end of the driving signal, the second end of the output resistor is electrically connected with the driving output end, the first end of the output capacitor is electrically connected with the second end of the output resistor, the second end of the output capacitor is grounded, or

The driving circuit further comprises a driving output end, M output resistors and M output capacitors, wherein M is an integer greater than 1;

the first end of the first output resistor is electrically connected with the driving signal output end, and the second end of the Mth output resistor is electrically connected with the driving output end;

the first end of the mth output resistor is electrically connected with the second end of the mth-1 output resistor, wherein M is an integer smaller than or equal to M and larger than 1;

A first end of a first output capacitor is electrically connected with a second end of the first output resistor, and a second end of the first output capacitor is grounded;

The first end of the mth output capacitor is electrically connected with the second end of the mth output resistor, and the second end of the mth output capacitor is grounded.

In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the driving circuit described above, and includes:

The first node control circuit controls the potential of the first node according to a first control voltage provided by a first control voltage end and a second control voltage provided by a second control voltage end under the control of a first scanning control signal, a first clock signal and a second scanning control signal;

The control node control circuit controls the potential of the control node under the control of a first scanning control signal, a first control voltage, a second scanning control signal and a second control voltage according to a second clock signal provided by a second clock signal end, and controls the connection or disconnection between the control node and a first voltage end under the control of the second clock signal;

the second node control circuit controls the connection or disconnection between the second node and the second voltage end under the control of the potential of the first node, controls the potential of the connection node according to the potential of the control node, and controls the connection or disconnection between the first clock signal end and the connection node under the control of the potential of the control node, and controls the connection or disconnection between the connection node and the second node under the control of the first clock signal;

The output circuit controls the connection or disconnection between the driving signal output end and the first voltage end under the control of the potential of the first node, and controls the connection or disconnection between the driving signal output end and the second voltage end under the control of the potential of the second node.

Optionally, the driving circuit further comprises a first energy storage circuit and a second energy storage circuit, wherein when the driving circuit performs forward scanning, the first scanning control end provides a third voltage signal, the second scanning control end provides a fourth voltage signal, and the driving period comprises a first normal scanning stage, a second normal scanning stage, a third normal scanning stage and a fourth normal scanning stage which are sequentially arranged;

the driving method includes that when the driving circuit performs forward scanning,

In the first normal scanning stage, a first clock signal end provides a sixth voltage signal, and a second node control circuit controls the connection node to be disconnected from the second node under the control of the first clock signal;

In the second positive scanning stage, the first control voltage end provides a fifth voltage signal, the first clock signal end provides a fifth voltage signal, the second clock signal end provides a sixth voltage signal, the control node control circuit controls the second clock signal end to be communicated with the control node under the control of the first control voltage and the first scanning control signal, the second node control circuit controls the first clock signal end to be disconnected from the connection node under the control of the potential of the control node;

In the third positive scanning stage, the first control voltage end provides a sixth voltage signal, the first clock signal end provides a sixth voltage signal, the second clock signal end provides a fifth voltage signal, the control node control circuit controls the communication between the control node and the first voltage end under the control of the second clock signal, the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal, the first energy storage circuit maintains the potential of the first node, and the output circuit controls the communication between the driving signal output end and the first voltage end under the control of the potential of the first node;

In the fourth positive scanning stage, the first control voltage end provides a sixth voltage signal, the first clock signal end provides a fifth voltage signal, the second clock signal end provides a sixth voltage signal, the first node control circuit controls the first node to be communicated with the first control voltage end under the control of a first scanning control signal and the first clock signal, the control node control circuit maintains the potential of the control node, the second node control circuit controls the first clock signal end to be communicated with the connecting node under the control of the potential of the control node and controls the connecting node to be communicated with the second node under the control of the first clock signal, and the output circuit controls the driving signal output end to be communicated with the second voltage end under the control of the potential of the second node.

Optionally, the driving circuit further comprises a first energy storage circuit and a second energy storage circuit, wherein when the driving circuit performs reverse scanning, the first scanning control end provides a fourth voltage signal, the second scanning control end provides a third voltage signal, the driving period comprises a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are sequentially arranged, the driving method comprises that when the driving circuit performs reverse scanning,

In the first reverse scanning stage, a first clock signal end provides a sixth voltage signal, and a second node control circuit controls disconnection between the connecting node and the second node under the control of the first clock signal;

In the second back scanning stage, the second control voltage end provides a fifth voltage signal, the first clock signal end provides a fifth voltage signal, the second clock signal end provides a sixth voltage signal, the control node control circuit controls the second clock signal end to be communicated with the control node under the control of the second control voltage and the second scanning control signal, the second node control circuit controls the first clock signal end to be disconnected from the connection node under the control of the potential of the control node;

in the third back-sweeping stage, the second control voltage end provides a sixth voltage signal, the first clock signal end provides a sixth voltage signal, the second clock signal end provides a fifth voltage signal, the control node control circuit controls the communication between the control node and the first voltage end under the control of the second clock signal, the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal, the first energy storage circuit maintains the potential of the first node, and the output circuit controls the communication between the driving signal output end and the first voltage end under the control of the potential of the first node;

In the fourth back scanning stage, the second control voltage end provides a sixth voltage signal, the first clock signal end provides a fifth voltage signal, the second clock signal end provides a sixth voltage signal, the first node control circuit controls the first node to be communicated with the second control voltage end under the control of the second scanning control signal and the first clock signal, the control node control circuit maintains the potential of the control node, the second node control circuit controls the first clock signal end to be communicated with the connecting node under the control of the potential of the control node and controls the connecting node to be communicated with the second node under the control of the first clock signal, and the output circuit controls the driving signal output end to be communicated with the second voltage end under the control of the potential of the second node.

In a third aspect, an embodiment of the present invention provides a driving module, including a plurality of stages of the driving circuits described above;

The first control voltage end of the first-stage driving circuit is electrically connected with the initial voltage end;

the first control voltage end of the a-1 st stage driving circuit is electrically connected with the driving signal output end of the a-1 st stage driving circuit;

the second control voltage end of the b-th stage driving circuit is electrically connected with the driving signal output end of the b+1th stage driving circuit;

a is an integer greater than 1, and b is a positive integer.

In a fourth aspect, an embodiment of the present invention provides a display device, including the driving module described above.

Drawings

FIG. 1 is a block diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 2 is a block diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 3 is a block diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 4 is a block diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 6 is a first timing diagram illustrating operation of at least one embodiment of the driving circuit shown in FIG. 5 according to the present invention;

FIG. 7 is a second timing diagram illustrating operation of at least one embodiment of the driving circuit shown in FIG. 5 according to the present invention;

FIG. 8 is a third timing diagram illustrating operation of at least one embodiment of the driving circuit shown in FIG. 5 according to the present invention;

FIG. 9 is a fourth timing diagram illustrating operation of at least one embodiment of the driving circuit shown in FIG. 5 according to the present invention;

FIG. 10 is a schematic diagram of each driving signal output end sequentially outputting corresponding driving signals from top to bottom when the driving module performs forward scanning according to at least one embodiment of the present invention;

FIG. 11 is a schematic diagram of each driving signal output end sequentially outputting corresponding driving signals from bottom to top when the driving module performs forward scanning according to at least one embodiment of the present invention;

FIG. 12 is a schematic diagram of each driving signal output end sequentially outputting corresponding driving signals from top to bottom when the driving module performs forward scanning according to at least one embodiment of the present invention;

FIG. 13A is a schematic diagram of a driving module according to at least one embodiment of the present invention, in which each driving signal output end sequentially outputs corresponding driving signals from bottom to top when performing a reverse scan;

FIG. 13B is a schematic diagram of the driving module according to at least one embodiment of the present invention, in which each driving signal output end sequentially outputs corresponding driving signals from bottom to top when the driving module performs a reverse scan;

FIG. 14 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 15 is a schematic diagram of a connection of parity row minimum repeating units;

FIG. 16 is a block diagram of a driving module according to at least one embodiment of the present invention;

FIG. 17 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 18 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

FIG. 19 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

fig. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In actual operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode, or the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source, or the control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.

As shown in fig. 1, the driving circuit according to at least one embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a control node control circuit 13, and an output circuit 14;

The first node control circuit 11 is electrically connected to the first scan control terminal CN, the first clock signal terminal XCK, the second scan control terminal CNB, the first control voltage terminal STU, the second control voltage terminal STD, and the first node Q, and is configured to control the potential of the first node Q under control of the first scan control signal provided by the first scan control terminal CN, the first clock signal provided by the first clock signal terminal XCK, and the second scan control signal provided by the second scan control terminal CNB, according to the first control voltage provided by the first control voltage terminal STU, and the second control voltage provided by the second control voltage terminal STD;

The control node control circuit 13 is electrically connected to the first scan control terminal CN, the first control voltage terminal STU, the second scan control terminal CNB, the second control voltage terminal STD, the second clock signal terminal CK, the control node QP, and the first voltage terminal V1, and is configured to control, under control of the first scan control signal, the first control voltage, the second scan control signal, and the second control voltage, the potential of the control node QP according to the second clock signal provided by the second clock signal terminal CK, and under control of the second clock signal, control the connection or disconnection between the control node QP and the first voltage terminal V1, and be configured to maintain the potential of the control node QP;

The second node control circuit 12 is electrically connected to the first node Q, the second node QB, the connection node J1, the control node QP, the first clock signal terminal XCK, and the second voltage terminal V2, and is configured to control, under the control of the potential of the first node Q, connection or disconnection between the second node QB and the second voltage terminal V2, and control, under the control of the potential of the control node QP, connection or disconnection between the first clock signal terminal XCK and the connection node J1, and control, under the control of the first clock signal, connection or disconnection between the connection node J1 and the second node QB;

The output circuit 14 is electrically connected to the first node Q, the second node QB, the first voltage terminal V1, the second voltage terminal V2, and the driving signal output terminal GN, and is configured to control the connection or disconnection between the driving signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q, and control the connection or disconnection between the driving signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

The driving circuit provided by the embodiment of the invention can realize the adjustable pulse width of the driving signal output by the driving circuit and can be applied to forward scanning and backward scanning.

The driving circuit according to the embodiment of the invention can be used for providing the compensation control signal for the compensation transistor in the internal compensation pixel circuit, and can also be used for providing the light-emitting control signal for the light-emitting control transistor in the external compensation pixel circuit, but is not limited thereto.

In at least one embodiment of the present invention, the first voltage terminal V1 may be a high voltage terminal, and the second voltage terminal V2 may be a low voltage terminal, but not limited thereto.

At least one embodiment of the driving circuit shown in fig. 1 may be an nth stage driving circuit, and the driving signal output GN may be an nth stage driving signal output, where N is a positive integer.

In at least one embodiment of the present invention, the first node control circuit is electrically connected to a first node, a first control voltage terminal, a second control voltage terminal, a first scan control terminal, a second scan control terminal, and a first clock signal terminal, and is configured to control, under control of a first scan control signal provided by the first scan control terminal and a first clock signal provided by the first clock signal terminal, connection or disconnection between the first node and the first control voltage terminal, and control, under control of a second scan control signal provided by the second scan control terminal and the first clock signal, connection or disconnection between the first node and the second control voltage terminal;

In operation, at least one embodiment of the driving circuit shown in fig. 1 of the present invention, the first node control circuit 11 controls the connection or disconnection between the first node Q and the first control voltage terminal STU under the control of the first scan control signal provided by the first scan control terminal CN and the first clock signal provided by the first clock signal terminal, and controls the connection or disconnection between the first node Q and the second control voltage terminal STD under the control of the second scan control signal provided by the second scan control terminal CNB and the first clock signal;

The control node control circuit 13 controls the connection or disconnection between the control node QP and the second clock signal terminal CK under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal STU, and controls the connection or disconnection between the control node QP and the second clock signal terminal CK under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal STD, and controls the connection or disconnection between the control node QP and the first voltage terminal V1 under the control of the second clock signal provided by the second clock signal terminal CK.

As shown in fig. 2, on the basis of at least one embodiment of the driving circuit shown in fig. 1, the driving circuit according to at least one embodiment of the present invention further includes a first tank circuit 21 and a second tank circuit 22;

a first end of the first tank circuit 21 is electrically connected to the first node Q, and a second end of the first tank circuit 21 is electrically connected to the driving signal output terminal GN, for controlling the potential of the first node Q according to the driving signal output by the driving signal output terminal GN;

The second tank circuit 22 is electrically connected to the second node QB, and is configured to maintain the potential of the second node QB.

In at least one embodiment of the present invention, the third voltage signal may be a high voltage signal, and the fourth voltage signal may be a low voltage signal, but not limited thereto.

In operation, at least one embodiment of the driving circuit shown in fig. 2, when the driving circuit performs forward scanning, the first scanning control end CN provides a high voltage signal, the second scanning control end CNB provides a low voltage signal, and the driving period includes a first normal scanning stage, a second normal scanning stage, a third normal scanning stage and a fourth normal scanning stage which are sequentially arranged;

In the first normal scan stage, the first clock signal terminal XCK provides a sixth voltage signal, and the second node control circuit 12 controls the connection node J1 to be disconnected from the second node QB under the control of the first clock signal;

In the second positive scan stage, the first control voltage terminal STU provides a fifth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, the second clock signal terminal CK provides a sixth voltage signal, the control node control circuit 13 controls the communication between the second clock signal terminal CK and the control node QP under the control of the first control voltage and the first scan control signal, the second node control circuit 12 controls the disconnection between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, the first node control circuit 11 controls the communication between the first node Q and the first control voltage terminal STU under the control of the first scan control signal and the first clock signal, and the output circuit 14 controls the communication between the driving signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q;

In the third positive scan stage, the first control voltage terminal STU provides a sixth voltage signal, the first clock signal terminal XCK provides a sixth voltage signal, the second clock signal terminal CK provides a fifth voltage signal, the control node control circuit 13 controls the connection between the control node QP and the first voltage terminal V1 under the control of the second clock signal, the second node control circuit 12 controls the disconnection between the connection node J1 and the second node QB under the control of the first clock signal, the first energy storage circuit 21 maintains the potential of the first node Q, and the output circuit 14 controls the connection between the driving signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q;

In the fourth normal scan stage, the first control voltage terminal STU provides a sixth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, the second clock signal terminal CK provides a sixth voltage signal, the first node control circuit 11 controls communication between the first node Q and the first control voltage terminal STU under the control of the first scan control signal and the first clock signal, the control node control circuit 13 maintains the potential of the control node QP, the second node control circuit 12 controls communication between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, and controls communication between the connection node J1 and the second node QB under the control of the first clock signal, and the output circuit 14 controls communication between the driving signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

In at least one embodiment of the present invention, the fifth voltage signal may be a high voltage signal, and the sixth voltage signal may be a low voltage signal, but is not limited thereto.

In operation, at least one embodiment of the driving circuit shown in fig. 2, when the driving circuit performs reverse scanning, the first scanning control terminal CN provides a low voltage signal, the second scanning control terminal CNB provides a high voltage signal, and the driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are sequentially arranged,

In the first reverse scan stage, the first clock signal terminal XCK provides a sixth voltage signal, and the second node control circuit 12 controls the connection node J1 to be disconnected from the second node QB under the control of the first clock signal, the first tank circuit 21 maintains the potential of the first node Q, and the second tank circuit 22 maintains the potential of the second node QB;

In the second back sweep stage, the second control voltage terminal STD provides a fifth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, the second clock signal terminal CK provides a sixth voltage signal, the control node control circuit 13 controls the communication between the second clock signal terminal CK and the control node QP under the control of the second control voltage and the second scan control signal, the second node control circuit 12 controls the disconnection between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, the first node control circuit 11 controls the communication between the first node Q and the second control voltage terminal STD under the control of the second scan control signal and the first clock signal, and the output circuit controls the communication between the driving signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q;

in the third sweep stage, the second control voltage terminal STD provides a sixth voltage signal, the first clock signal terminal XCK provides a sixth voltage signal, the second clock signal terminal CK provides a fifth voltage signal, the control node control circuit 13 controls the connection between the control node QP and the first voltage terminal V1 under the control of the second clock signal, the second node control circuit 12 controls the disconnection between the connection node J1 and the second node QB under the control of the first clock signal, the first tank circuit 21 maintains the potential of the first node Q, and the output circuit 14 controls the connection between the drive signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q;

in the fourth reverse scan stage, the second control voltage terminal STD provides a sixth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, the second clock signal terminal CK provides a sixth voltage signal, the first node control circuit 11 controls communication between the first node Q and the second control voltage terminal STD under the control of the second scan control signal and the first clock signal, the control node control circuit 13 maintains the potential of the control node QP, the second node control circuit 12 controls communication between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, and controls communication between the connection node J1 and the second node QB under the control of the first clock signal, and the output circuit 14 controls communication between the driving signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

As shown in fig. 3, the first node control circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, based on at least one embodiment of the driving circuit shown in fig. 2;

The gate of the first transistor T1 is electrically connected to the first clock signal terminal XCK, the source of the first transistor T1 is electrically connected to the first control voltage terminal STU, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;

The gate of the second transistor T2 is electrically connected to the first scan control terminal CN, and the drain of the second transistor T2 is electrically connected to the first node Q;

A gate of the third transistor T3 is electrically connected to the second scan control terminal CNB, a source of the third transistor T3 is electrically connected to the first node Q, and a drain of the third transistor T3 is electrically connected to a source of the fourth transistor T4;

the gate of the fourth transistor T4 is electrically connected to the first clock signal terminal XCK, and the drain of the fourth transistor T4 is electrically connected to the second control voltage terminal STD.

The driving circuit according to at least one embodiment of the present invention further includes a first leakage preventing circuit;

As shown in fig. 4, on the basis of at least one embodiment of the driving circuit shown in fig. 3, the driving circuit according to at least one embodiment of the present invention further includes a first leakage preventing circuit 41;

The first leakage protection circuit 41 is electrically connected to the first node Q, the high voltage terminal VGH, the drain of the first transistor T1, and the drain of the third transistor T3, respectively, and is configured to control communication between the high voltage terminal VGH and the drain of the first transistor T1 and control communication between the high voltage terminal VGH and the drain of the third transistor T3 under the control of the potential of the first node Q.

In operation, when the potential of the first node Q is high, the first leakage preventing circuit 41 controls the connection between the first voltage terminal V1 and the drain of the first transistor T1 and controls the connection between the first voltage terminal V1 and the drain of the third transistor T3 under the control of the potential of the first node Q, so as to provide a high voltage signal for the intermediate node of the first transistor T1 and the second transistor T2 and a high voltage signal for the intermediate node of the third transistor T3 and the fourth transistor T4, thereby preventing the first node Q from leaking to the first control voltage terminal STU and the second control voltage terminal STD, and facilitating the maintenance of the potential of the first node Q.

As shown in fig. 5, in at least one embodiment of the driving circuit shown in fig. 3, the control node control circuit 13 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a storage capacitor C0;

A gate of the fifth transistor T5 is electrically connected to the first control voltage terminal STU, a source of the fifth transistor T5 is electrically connected to the second clock signal terminal CK, and a drain of the fifth transistor T5 is electrically connected to a source of the sixth transistor T6;

The gate of the sixth transistor T6 is electrically connected to the first scan control terminal CN, and the drain of the sixth transistor T6 is electrically connected to the control node QP;

A gate of the seventh transistor T7 is electrically connected to the second scan control terminal CNB, a source of the seventh transistor T7 is electrically connected to the control node QP, and a drain of the seventh transistor T7 is electrically connected to a source of the eighth transistor T8;

a gate of the eighth transistor T8 is electrically connected to the second control voltage terminal STD, and a drain of the eighth transistor T8 is electrically connected to the second clock signal terminal CK;

A gate of the ninth transistor T9 is electrically connected to the second clock signal terminal CK, a source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and a drain of the ninth transistor T9 is electrically connected to the control node QP;

A first end of the storage capacitor C0 is electrically connected with the control node QP, and a second end of the storage capacitor C0 is electrically connected with the connection node J1;

the second node control circuit 12 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13;

A gate of the tenth transistor T10 is electrically connected to the control node QP, a source of the tenth transistor T10 is electrically connected to the first clock signal terminal XCK, and a drain of the tenth transistor T10 is electrically connected to the connection node J1;

A gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal XCK, a source of the eleventh transistor T11 is electrically connected to the connection node J1, and a drain of the eleventh transistor T11 is electrically connected to the second node QB;

The grid electrode of the twelfth transistor T12 and the grid electrode of the thirteenth transistor T13 are electrically connected with the first node Q, the source electrode of the twelfth transistor T12 is electrically connected with the low voltage end VGL, and the drain electrode of the twelfth transistor T12 is electrically connected with the source electrode of the thirteenth transistor T13;

The output circuit 14 includes a first output transistor TO1 and a second output transistor TO2;

The gate of the first output transistor TO1 is electrically connected TO the first node Q, the source of the first output transistor TO1 is electrically connected TO the high voltage terminal VGH, and the drain of the first output transistor TO1 is electrically connected TO the driving signal output terminal GN;

The gate of the second output transistor TO2 is electrically connected TO the second node QB, the source of the second output transistor TO2 is electrically connected TO the driving signal output terminal GN, and the source of the second output transistor TO2 is electrically connected TO the low voltage terminal VGL;

the first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

A first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the driving signal output GN;

the first end of the second capacitor C2 is electrically connected to the second node QB, and the second end of the second capacitor C2 is electrically connected to the low voltage terminal VGL.

In at least one embodiment of the driving circuit shown in fig. 5, all the transistors are n-type transistors, but not limited thereto.

In operation, at least one embodiment of the driving circuit shown in fig. 5 performs forward scanning in conjunction with a first control voltage provided by the STU when CN provides a high voltage signal and CNB provides a low voltage signal, and performs reverse scanning in conjunction with a second control voltage provided by the STD when CN provides a high voltage signal and CNB provides a low voltage signal, wherein the first control voltage and the second control voltage may be combined into one voltage signal.

At least one embodiment of the driving circuit of the present invention as shown in figure 5 is operative,

When the pulse width of the first control voltage provided by the STU is changed during forward scanning, the pulse width of the driving signal output by the GN is correspondingly changed;

When the pulse width of the second control voltage supplied from the STD is changed during the reverse scan, the pulse width of the driving signal outputted from the GN is also changed accordingly.

As shown in fig. 6, at least one embodiment of the driving circuit shown in fig. 5 of the present invention provides a high voltage signal CN and a low voltage signal CNB during forward scanning, wherein the driving period includes a first positive scan stage S11, a second positive scan stage S12, a first interval stage S01, a third positive scan stage S13, a second interval stage S02 and a fourth positive scan stage S14, which are sequentially arranged;

In the first positive scanning stage S11, XCK provides a low voltage signal, T11 is closed to control the disconnection between the connection node J1 and the second node QB, C1 maintains the potential of the first node Q, C2 maintains the potential of the second node QB;

in the first positive scan stage S11, CK provides a high voltage signal, STU provides a high voltage signal, T9 is opened, T5 and T6 are opened so that the potential of QP is high voltage, T10 is opened, CK provides a low voltage signal, T9 is closed, the potential of QP is low voltage, T10 is closed, and T11 is closed;

In the second positive scanning stage S12, CK provides a low voltage signal, XCK provides a high voltage signal, STU provides a high voltage signal, STD provides a low voltage signal, T1 and T2 are opened, communication between a first node Q and the STU is controlled, at the moment, the potential of the first node Q is high voltage, since T5 and T6 are continuously opened, QP is low voltage, T10 is closed, T12 and T13 are both opened, the potential of a second node QB is low voltage, TO1 is opened, TO2 is closed, and GN outputs a high voltage signal;

in the first interval stage S01, CK provides a low voltage signal, XCK provides a low voltage signal, STU provides a low voltage signal, T1 is turned off, C1 maintains the potential of the first node Q at a high voltage, C2 maintains the potential of the second node QB at a low voltage, TO1 is turned on, TO2 is turned off, GN continuously outputs a high voltage signal;

in the third normal scan stage S13, CK provides a high voltage signal, XCK provides a low voltage signal, STU provides a low voltage signal, T9 is turned on, QP is at a high voltage, T10 is turned on, T11 is turned off, the second node QB is maintained at a low voltage, TO2 is turned off, T1 and T4 are turned off, the first node Q is maintained at a high voltage, TO1 is turned on, GN outputs a high voltage signal;

In the second interval stage S02, CK provides a low voltage signal, XCK provides a low voltage signal, T9 is closed, the potential of the control node QP is maintained at a high level, T10 is opened, T11 is closed, the potential of the second node QB is maintained at a low voltage, TO2 is closed, T1 and T4 are closed, the potential of the first node Q is maintained at a high voltage, TO1 is opened, and GN outputs a high voltage signal;

In the fourth normal scan stage S14, CK provides a low voltage signal, XCK provides a high voltage signal, STU provides a low voltage signal, T1 is turned on, T2 is turned on, the potential of the first node Q is set TO a low voltage by discharging, T5 is turned off, T9 is turned off, T7 is turned off, the potential of the control node QP is maintained at a high voltage, T10 is turned on, T11 is turned on, the potential of the second node QB is a high voltage, TO1 is turned off, TO2 is turned on, GN outputs a low voltage signal, and then the step-by-step scan is completed TO the final stage.

As shown in fig. 7, a driving module including at least one embodiment of the driving circuit shown in fig. 5 may include a 12-stage driving circuit;

The driving signal output terminal of the first stage is denoted by G1, the driving signal output terminal of the second stage is denoted by G2, the driving signal output terminal of the third stage is denoted by G3, the driving signal output terminal of the fourth stage is denoted by G4, the driving signal output terminal of the fifth stage is denoted by G5, the driving signal output terminal of the sixth stage is denoted by G6, the driving signal output terminal of the seventh stage is denoted by G7, the driving signal output terminal of the eighth stage is denoted by G8, the driving signal output terminal of the ninth stage is denoted by G9, the driving signal output terminal of the tenth stage is denoted by G10, the driving signal output terminal of the eleventh stage is denoted by G11, and the driving signal output terminal of the twelfth stage is denoted by G12.

As shown in fig. 8, at least one embodiment of the driving circuit shown in fig. 5 of the present invention provides a low voltage signal for CN and a high voltage signal for CNB during forward scanning, wherein the driving period includes a first back-scan stage S21, a second back-scan stage S22, a third interval stage S03, a third back-scan stage S23, a fourth interval stage S04 and a fourth back-scan stage S24, which are sequentially arranged;

In the first reverse scanning stage S21, XCK provides a low voltage signal, T11 is closed to control the disconnection between the connection node J1 and the second node QB, C1 maintains the potential of the first node Q, C2 maintains the potential of the second node QB;

In the first back sweep stage S21, CK provides a high voltage signal, STD provides a high voltage signal, T9 is turned on, T7 and T8 are turned on so that the potential of the control node QP is high voltage, T10 is turned on, CK provides a low voltage signal, T9 is turned off, the potential of the control node QP is low voltage, T10 is turned off, and T11 is turned off;

In the second back scanning stage S22, CK provides a low voltage signal, XCK provides a high voltage signal, STD provides a high voltage signal, STU provides a low voltage signal, T3 and T4 are opened, communication between the first node Q and the STD is controlled, and the potential of the first node Q is high voltage at the moment;

In the third interval stage S03, CK provides a low voltage signal, XCK provides a low voltage signal, STD provides a low voltage signal, T1 is turned off, C1 maintains the potential of the first node Q at a high voltage, C2 maintains the potential of the second node QB at a low voltage, TO1 is turned on, TO2 is turned off, GN continuously outputs a high voltage signal;

in the third inverting stage S23, CK provides a high voltage signal, XCK provides a low voltage signal, STD provides a low voltage signal, T9 is turned on, the potential of the control node QP is high, T10 is turned on, T11 is turned off, the potential of the second node QB is maintained at a low voltage, TO2 is turned off, T1 and T4 are turned off, the potential of the first node Q is maintained at a high voltage, TO1 is turned on, GN outputs a high voltage signal;

In the third interval stage S03, CK provides a low voltage signal, XCK provides a low voltage signal, T9 is closed, the potential of the control node QP is maintained at a high level, T10 is opened, T11 is closed, the potential of the second node QB is maintained at a low voltage, TO2 is closed, T1 and T4 are closed, the potential of the first node Q is maintained at a high voltage, TO1 is opened, and GN outputs a high voltage signal;

In the fourth reverse scan stage S24, CK provides a low voltage signal, XCK provides a high voltage signal, STD provides a low voltage signal, T3 is turned on, T4 is turned on, the potential of the first node Q is set TO a low voltage by discharging, T6 is turned off, T9 is turned off, T8 is turned off, the potential of the control node QP is maintained at a high voltage, T10 is turned on, T11 is turned on, the potential of the second node QB is a high voltage, TO1 is turned off, TO2 is turned on, GN outputs a low voltage signal.

As shown in fig. 9, a driving module including at least one embodiment of the driving circuit shown in fig. 5 may include a 12-stage driving circuit;

When the driving module including at least one embodiment of the driving circuit as shown in fig. 5 includes a 24-stage driving circuit,

As shown in fig. 10, when the driving module performs forward scanning, each driving signal output end sequentially outputs corresponding driving signals from top to bottom;

as shown in fig. 11, when the driving module performs forward scanning, each driving signal output end sequentially outputs corresponding driving signals from bottom to top.

In fig. 10 and 11, a first stage drive signal output terminal denoted by G1, a second stage drive signal output terminal denoted by G2, a third stage drive signal output terminal denoted by G3, a fourth stage drive signal output terminal denoted by G4, an eleventh stage drive signal output terminal denoted by G11, a twelfth stage drive signal output terminal denoted by G12, a thirteenth stage drive signal output terminal denoted by G13, a fourteenth stage drive signal output terminal denoted by G14, a fifteenth stage drive signal output terminal denoted by G15, a sixteenth stage drive signal output terminal denoted by G16, a seventeenth stage drive signal output terminal denoted by G17, an eighteenth stage drive signal output terminal denoted by G18, a nineteenth stage drive signal output terminal denoted by G19, and a twentieth stage drive signal output terminal denoted by G20.

When the driving module including at least one embodiment of the driving circuit as shown in fig. 5 includes a 12-stage driving circuit,

As shown in fig. 12, when the driving module performs forward scanning, each driving signal output end sequentially outputs corresponding driving signals from top to bottom, and the forward scanning pulse width is 1 clock cycle;

As shown in fig. 13A, when the driving module performs reverse scanning, each driving signal output end sequentially outputs corresponding driving signals from bottom to top, and the reverse scanning pulse width is 1 clock cycle;

as shown in fig. 13B, when the driving module performs the inverse scanning, each driving signal output end sequentially outputs corresponding driving signals from bottom to top, and the inverse scanning pulse width is 4 clock cycles. In fig. 12, 13A and 13B, a first stage driving signal output terminal denoted by G1, a second stage driving signal output terminal denoted by G2, a third stage driving signal output terminal denoted by G3, a tenth stage driving signal output terminal denoted by G10, an eleventh stage driving signal output terminal denoted by G11, and a twelfth stage driving signal output terminal denoted by G12.

The driving circuit according to at least one embodiment of the present invention further includes a driving output terminal, an output resistor, and an output capacitor;

In a specific implementation, when the driving circuit according to at least one embodiment of the present invention further includes a driving output, the driving signal output is used for cascading, and the driving output is used for providing a driving signal for a corresponding transistor in the pixel circuit.

As shown in fig. 14, based ON at least one embodiment of the driving circuit shown in fig. 5, the driving circuit according to at least one embodiment of the present invention further includes a driving output terminal ON, a first output resistor R1, a second output resistor R2, a third output resistor R3, a fourth output resistor R4, a fifth output resistor R5, a first output capacitor C01, a second output capacitor C02, a third output capacitor C03, a fourth output capacitor C04, and a fifth output capacitor C05;

The first end of R1 is electrically connected with GN, and the second end of R1 is electrically connected with the first end of R2;

the second end of R2 is electrically connected with the first end of R3, and the second end of R3 is electrically connected with the first end of R4;

the second end of R4 is electrically connected with the first end of R5, and the second end of R5 is electrically connected with the drive output end ON;

the first end of C01 is electrically connected with the second end of R1, and the second end of C01 is electrically connected with the ground;

the first end of C02 is electrically connected with the second end of R2, and the second end of C02 is electrically connected with the ground;

the first end of C03 is electrically connected with the second end of R3, and the second end of C03 is electrically connected with the ground;

the first end of C04 is electrically connected with the second end of R4, and the second end of C04 is electrically connected with the ground;

The first end of C05 is electrically connected with the second end of R1, and the second end of C05 is electrically connected with the ground.

FIG. 15 is a schematic diagram of the connection of parity row minimum repeating units.

In at least one embodiment of the driving circuit shown in fig. 14, ON is the nth stage driving output, and N is a positive integer.

In fig. 15, reference numeral 151 is a circuit diagram of an N-th stage driving circuit, and reference numeral 152 is a circuit diagram of an n+1-th stage driving circuit.

In fig. 15, reference sign GN denotes an nth stage drive signal output terminal, gn+1 denotes an n+1th stage drive signal output terminal, ON denotes an nth stage drive output terminal, and on+1 denotes an n+1th stage drive output terminal;

the second control voltage terminal of the nth stage driving circuit 151 is electrically connected to gn+1;

the first control voltage terminal of the n+1st stage driving circuit 152 is electrically connected to GN.

Fig. 16 is a block diagram of a driving module according to at least one embodiment of the invention.

As shown in fig. 16, the driving module according to at least one embodiment of the invention includes a first stage driving circuit GOA1, a second stage driving circuit GOA2, a third stage driving circuit GOA3, an N-2 stage driving circuit GOAN-2, an N-1 stage driving circuit GOAN-1 and an N-th stage driving circuit GOAN;

in at least one embodiment shown in FIG. 16, N is greater than 4;

In fig. 16, XCK is a first clock signal terminal, CK is a second clock signal terminal, CN is a first scan control terminal, and CNB is a second scan control terminal;

The first starting voltage terminal is marked as STV1, the second starting voltage terminal is marked as STV2, the high voltage terminal is marked as VGH, and the low voltage terminal is marked as VGL;

The first stage drive signal output terminal is denoted by G1, and the first stage drive output terminal is denoted by O1;

the second stage drive signal output terminal is denoted by G2, and the second stage drive output terminal is denoted by O2;

the third stage drive signal output is denoted by G3 and the third stage drive output is denoted by O3;

the N-2 stage driving signal output end is marked with GN-2, and the N-2 stage driving output end is marked with O-2;

An N-1 stage driving signal output terminal with the reference sign GN-1, and an N-1 stage driving output terminal with the reference sign ON-1;

The N-th driving signal output end is marked with GN, and the N-th driving output end is marked with ON;

the first control voltage end of the GOA1 is electrically connected with the first starting voltage end STV1, and the second control voltage end of the GOA1 is electrically connected with the G2;

the first control voltage end of the GOA2 is electrically connected with G1, and the second control voltage end of the GOA2 is electrically connected with G3;

The first control voltage end of GOA3 is electrically connected with G2;

the second control voltage terminal of GOAN-2 is electrically connected to GN-1;

The first control voltage terminal of GOAN-1 is electrically connected to GN-2, and the second control voltage terminal of GOAN-1 is electrically connected to GN;

The first control voltage terminal GOAN is electrically connected to GN-1 and the second control voltage terminal GOAN is electrically connected to the second start voltage terminal STV 2.

The driving circuit according to at least one embodiment of the present invention further includes a second leakage preventing circuit;

At least one embodiment of the driving circuit shown in fig. 17 of the present invention differs from at least one embodiment of the driving circuit shown in fig. 5 of the present invention as follows:

The output circuit 14 includes a first output transistor TO1, a second output transistor TO2, and a third output transistor TO3;

The gate of the second output transistor TO2 is electrically connected TO the second node QB, the source of the second output transistor TO2 is electrically connected TO the driving signal output GN, and the drain of the second output transistor TO2 is electrically connected TO the source of the third output transistor TO 3;

the gate of the third output transistor TO3 is electrically connected TO the second node QB, and the drain of the third output transistor TO3 is electrically connected TO the low voltage terminal VGL.

In at least one embodiment of the driving circuit shown in fig. 17, all the transistors are n-type transistors, but not limited thereto.

As shown in fig. 18, based on at least one embodiment of the driving circuit shown in fig. 17, the driving circuit according to at least one embodiment of the present invention further includes a second leakage preventing circuit 181;

The second leakage protection circuit 181 is electrically connected TO the driving signal output terminal GN, the high voltage terminal VGH, and the drain of the second output transistor TO2, and is configured TO control the communication between the high voltage terminal VGH and the drain of the second output transistor TO2 under the control of the driving signal provided by the driving signal output terminal GN.

In operation, according TO at least one embodiment of the driving circuit shown in fig. 18, when GN outputs a high voltage signal, the second leakage preventing circuit 181 controls the connection between the high voltage terminal VGH and the drain of the second output transistor TO2, so that the potential of the drain of the second output transistor TO2 is high, and prevents GN from leaking TO the low voltage terminal VGL.

As shown in fig. 19, in at least one embodiment of the driving circuit shown in fig. 18, the driving circuit according to at least one embodiment of the present invention further includes a first leakage preventing circuit 41;

The first leakage circuit 41 includes a fourteenth transistor T14;

a gate of the fourteenth transistor T14 is electrically connected to the first node Q, a source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and a drain of the fourteenth transistor T14 is electrically connected to a drain of the first transistor T1 and a drain of the third transistor T3;

The second leakage circuit 181 includes a fifteenth transistor T15;

The gate of the fifteenth transistor T15 is electrically connected TO the driving signal output terminal GN, the source of the fifteenth transistor T15 is electrically connected TO the high voltage terminal VGH, and the drain of the fifteenth transistor T15 is electrically connected TO the drain of the second output transistor TO 2.

In at least one embodiment of the driving circuit shown in fig. 19, all the transistors are n-type transistors, but not limited thereto.

As shown in fig. 20, in addition to at least one embodiment of the driving circuit shown in fig. 19, the driving circuit according to at least one embodiment of the present invention further includes a driving output terminal ON, a first output resistor R1, a second output resistor R2, a third output resistor R3, a fourth output resistor R4, a fifth output resistor R5, a first output capacitor C01, a second output capacitor C02, a third output capacitor C03, a fourth output capacitor C04, and a fifth output capacitor C05;

The driving method of the embodiment of the invention is applied to the driving circuit, and comprises the following steps:

In at least one embodiment of the invention, the driving circuit further comprises a first energy storage circuit and a second energy storage circuit, wherein when the driving circuit performs forward scanning, the first scanning control end provides a third voltage signal, the second scanning control end provides a fourth voltage signal, and the driving period comprises a first normal scanning stage, a second normal scanning stage, a third normal scanning stage and a fourth normal scanning stage which are sequentially arranged;

In at least one embodiment of the present invention, the driving circuit further includes a first tank circuit and a second tank circuit, wherein when the driving circuit performs a reverse scan, the first scan control terminal provides a fourth voltage signal, the second scan control terminal provides a third voltage signal, and the driving cycle includes a first reverse scan stage, a second reverse scan stage, a third reverse scan stage, and a fourth reverse scan stage sequentially disposed, and the driving method includes when the driving circuit performs a reverse scan,

In the first back scanning stage, a second control voltage end provides a fifth voltage signal, a first clock signal end provides a sixth voltage signal, a second clock signal end provides a fifth voltage signal, and a second node control circuit controls disconnection between the connecting node and the second node under the control of the first clock signal;

The driving module comprises a plurality of stages of driving circuits;

a is an integer greater than 1, and b is a positive integer.

The display device according to the embodiment of the invention comprises the driving circuit.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A driving circuit, characterized in that it comprises a first node control circuit, a second node control circuit, a control node control circuit and an output circuit;

The first node control circuit is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal provided by the first scan control terminal, the first clock signal provided by the first clock signal terminal and the second scan control signal provided by the second scan control terminal;

The control node control circuit is used to control the potential of the control node according to the second clock signal provided by the second clock signal terminal under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal, and to maintain the potential of the control node;

The second node control circuit is electrically connected to the first node, the second node, the connection node, the control node, the first clock signal terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and control the connection or disconnection between the connection node and the second node under the control of the first clock signal;

The output circuit is electrically connected to the first node, the second node, the first voltage terminal, the second voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node;

The driving circuit also includes a first energy storage circuit and a second energy storage circuit;

The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output end, and is used to control the potential of the first node according to the drive signal output by the drive signal output end;

The second energy storage circuit is electrically connected to the second node and is used to maintain the potential of the second node;

When the driving circuit performs forward scanning, the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage and a fourth forward scanning stage which are arranged successively;

The second node control circuit is used for controlling the disconnection between the connection node and the second node under the control of the first clock signal in the first positive scanning stage; the first energy storage circuit is used for maintaining the potential of the first node in the first positive scanning stage, and the second energy storage circuit is used for maintaining the potential of the second node in the first positive scanning stage;

The control node control circuit is used to control the connection between the second clock signal terminal and the control node under the control of the first control voltage and the first scan control signal in the second positive scan stage; the second node control circuit is used to control the disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node in the second positive scan stage; the first node control circuit is used to control the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal in the second positive scan stage; the output circuit is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node in the second positive scan stage;

The control node control circuit is used to control the connection between the control node and the first voltage terminal under the control of the second clock signal in the third positive scanning stage; the second node control circuit is used to control the disconnection between the connection node and the second node under the control of the first clock signal in the third positive scanning stage; the first energy storage circuit is used to maintain the potential of the first node in the third positive scanning stage; the output circuit is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node in the third positive scanning stage;

The first node control circuit is used to control the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal in the fourth positive scan stage; the control node control circuit is used to maintain the potential of the control node in the fourth positive scan stage; the second node control circuit is used to control the connection between the first clock signal terminal and the connection node under the control of the potential of the control node in the fourth positive scan stage, and control the connection between the connection node and the second node under the control of the first clock signal; the output circuit is used to control the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node in the fourth positive scan stage.

2. The driving circuit according to claim 1, characterized in that the first node control circuit is electrically connected to the first node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the first control voltage terminal under the control of a first scan control signal provided by the first scan control terminal and a first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the first node and the second control voltage terminal under the control of a second scan control signal provided by the second scan control terminal and the first clock signal;

The control node control circuit is electrically connected to the control node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the second clock signal terminal under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the control node and the second clock signal terminal under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

3. The driving circuit according to claim 2, wherein the first node control circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor;

The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first control voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

The control electrode of the second transistor is electrically connected to the first scan control terminal, and the second electrode of the second transistor is electrically connected to the first node;

The control electrode of the third transistor is electrically connected to the second scan control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

A control electrode of the fourth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second control voltage terminal.

4. The driving circuit according to claim 3, further comprising a first leakage prevention circuit;

The first leakage prevention circuit is electrically connected to the first node, the first voltage terminal, the second electrode of the first transistor and the second electrode of the third transistor, respectively, and is used to control the connection between the first voltage terminal and the second electrode of the first transistor, and to control the connection between the first voltage terminal and the second electrode of the third transistor under the control of the potential of the first node.

5. The driving circuit according to claim 2, wherein the control node control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a storage capacitor;

The control electrode of the fifth transistor is electrically connected to the first control voltage terminal, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;

The control electrode of the sixth transistor is electrically connected to the first scan control terminal, and the second electrode of the sixth transistor is electrically connected to the control node;

The control electrode of the seventh transistor is electrically connected to the second scan control terminal, the first electrode of the seventh transistor is electrically connected to the control node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

The control electrode of the eighth transistor is electrically connected to the second control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal terminal;

The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node;

A first end of the storage capacitor is electrically connected to the control node, and a second end of the storage capacitor is electrically connected to the connection node.

6. The driving circuit according to any one of claims 1 to 5, wherein the second node control circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

The control electrode of the tenth transistor is electrically connected to the control node, the first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the connection node;

The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the connection node, and the second electrode of the eleventh transistor is electrically connected to the second node;

The control electrode of the twelfth transistor and the control electrode of the thirteenth transistor are both electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second voltage terminal, the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second node.

7. The driving circuit according to any one of claims 1 to 5, characterized in that the output circuit comprises a first output transistor and a second output transistor;

The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the second voltage terminal.

8. The driving circuit according to any one of claims 1 to 5, characterized in that the output circuit comprises a first output transistor, a second output transistor and a third output transistor;

The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first electrode of the third output transistor;

A control electrode of the third output transistor is electrically connected to the second node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.

9. The driving circuit according to claim 8, further comprising a second leakage prevention circuit;

The second anti-leakage circuit is electrically connected to the drive signal output terminal, the first voltage terminal and the second electrode of the second output transistor respectively, and is used to control the connection between the first voltage terminal and the second electrode of the second output transistor under the control of the drive signal provided by the drive signal output terminal.

10. The driving circuit according to any one of claims 1 to 5, wherein the first energy storage circuit comprises a first capacitor; the second energy storage circuit comprises a second capacitor;

A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the drive signal output end;

A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the second voltage end.

11. The driving circuit according to claim 4, wherein the first leakage prevention circuit comprises a fourteenth transistor;

The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the second electrode of the first transistor and the second electrode of the third transistor.

12. The driving circuit according to claim 9, wherein the second leakage prevention circuit comprises a fifteenth transistor;

The control electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the second output transistor.

13. The driving circuit according to any one of claims 1 to 5, further comprising a driving output terminal, an output resistor and an output capacitor;

The first end of the output resistor is electrically connected to the drive signal output terminal; the second end of the output resistor is electrically connected to the drive output terminal; the first end of the output capacitor is electrically connected to the second end of the output resistor, and the second end of the output capacitor is grounded; or,

The driving circuit further includes a driving output terminal, M output resistors and M output capacitors, where M is an integer greater than 1;

A first end of a first output resistor is electrically connected to the drive signal output terminal, and a second end of an Mth output resistor is electrically connected to the drive output terminal;

The first end of the m-th output resistor is electrically connected to the second end of the m-1-th output resistor; m is an integer less than or equal to M and greater than 1;

A first end of a first output capacitor is electrically connected to a second end of the first output resistor, and a second end of the first output capacitor is grounded;

A first end of the mth output capacitor is electrically connected to a second end of the mth output resistor, and a second end of the mth output capacitor is grounded.

14. A driving method, applied to the driving circuit according to any one of claims 1 to 13, characterized in that the driving method comprises:

The first node control circuit controls the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal, the first clock signal and the second scan control signal;

The control node control circuit controls the potential of the control node under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage according to the second clock signal provided by the second clock signal terminal, and controls the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal;

The second node control circuit controls the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, controls the potential of the connection node according to the potential of the control node, and controls the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection or disconnection between the connection node and the second node under the control of the first clock signal;

The output circuit controls the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node;

The driving circuit also includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs forward scanning, the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage and a fourth forward scanning stage which are arranged in sequence;

The driving method comprises: when the driving circuit performs forward scanning,

In the first forward scanning stage, the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

In the second forward scanning stage, the control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the first control voltage and the first scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the first control voltage terminal under the control of the first scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

In the third positive scanning stage, the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

In the fourth positive scan stage, the first node control circuit controls the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

15. The driving method according to claim 14, characterized in that when the driving circuit performs reverse scanning, the first scanning control terminal provides a fourth voltage signal, the second scanning control terminal provides a third voltage signal, and the driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are arranged in sequence; the driving method comprises: when the driving circuit performs reverse scanning,

In the first reverse scanning stage, the first clock signal terminal provides a sixth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

In the second reverse scanning stage, the second control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the second control voltage and the second scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

In the third reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

In the fourth reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

16. The driving method according to claim 14, further comprising:

When the driving circuit performs forward scanning, the first scanning control terminal provides a third voltage signal, and the second scanning control terminal provides a fourth voltage signal;

In the first positive scanning stage, the first clock signal terminal provides a sixth voltage signal;

In the second forward scanning stage, the first control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal;

In the third positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal;

In the fourth positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal.

17. A driving module, characterized by comprising a plurality of driving circuits according to any one of claims 1 to 13;

The first control voltage terminal of the first stage driving circuit is electrically connected to the starting voltage terminal;

The first control voltage terminal of the a-th level driving circuit is electrically connected to the driving signal output terminal of the a-1-th level driving circuit;

The second control voltage terminal of the b-th level driving circuit is electrically connected to the driving signal output terminal of the b+1-th level driving circuit;

a is an integer greater than 1, and b is a positive integer.

18. A display device, comprising the driving module according to claim 17.