CN114999544A - An in-memory computing circuit based on SRAM - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and in particular relates to an in-memory computing circuit based on SRAM. The invention proposes an in-memory computing circuit based on SRAM, including a 6T SRAM Cell array and a multiplexing computing unit. The in-memory computing circuit pre-writes weight data into SRAM for storage, and then multiplexes the computing unit with the input data. Perform multiply-accumulate operations to implement in-memory calculations. Although the in-memory computing unit proposed by the present invention increases the area of the memory, the data can be calculated in the memory, and the data handling and power consumption of applications such as convolutional neural networks are significantly reduced.

Description

An in-memory computing circuit based on SRAM

technical field

The invention belongs to the technical field of integrated circuits, and relates to an in-memory computing circuit based on SRAM.

Background technique

With the rapid development and large-scale application of artificial intelligence technology and Internet of Things technology, the amount of data that needs to be processed by neural network algorithms is also increasing. In a computer based on the traditional Von Neumann architecture, the memory and the central processing unit (CPU) are separated from each other. During the calculation process, the memory first transmits the data to the CPU through the bus for calculation, and then calculates the calculation after the calculation is completed. The results are written back to memory over the bus. When the memory and bus speeds are matched, the von Neumann architecture is dominant. However, in recent decades, memory has developed towards a pyramid hierarchy, that is, the farther away the memory is from the CPU, the larger the capacity, the cheaper the price, but the slower the speed, while the speed of the CPU follows Moore's Law to grow rapidly. This also makes today's memory access speed much lower than the data processing speed of the CPU, becoming a "Memory Wall" that limits computer performance, which is also recognized as the biggest bottleneck in the von Neumann architecture. This phenomenon is more pronounced in applications such as deep neural networks that require high-frequency data reading and writing and transmission. As the most widely used algorithm in artificial intelligence image recognition, deep neural network needs to access, multiply and accumulate a large amount of image data. Limited by the limited transmission speed and bandwidth of the system bus and memory, these factors limit the reasoning speed and application scope of deep neural network algorithms.

In order to break through this bottleneck of the von Neumann architecture, the Computing-in-Memory (CIM) architecture was proposed. As the name implies, in-memory computing is performing some computations in memory, such as multiplication, exclusive-or, and accumulation operations. In this way, a large amount of data in the memory does not need to be transmitted to the CPU through the system bus to be calculated, but the results can be calculated by relying on some calculation units and control circuits in the memory, and only the results are output through the system bus, which greatly reduces the number of The bus interaction between the CPU and the memory not only solves the problems of CPU speed and memory speed mismatch and data access power consumption, but also solves the problems of transmission bandwidth and delay limitations on the system bus.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose an in-memory computing unit, the architecture realizes the multiply-accumulate operation of data by introducing a computing unit circuit inside the SRAM memory, avoiding the need to take out the data from the memory through the bus in the Von Neumann architecture, The disadvantage that it can only be calculated by sending it to the CPU through the bus can effectively reduce the amount of data handling and the power consumption of the circuit.

In order to achieve the above object, the present invention discloses an in-memory computing unit based on SRAM, including a 6T SRAMCell array and a multiplex computing cell (Multiplex Computing Cell). Before the calculation, the weight data that needs to be calculated is written into the 6T SRAM Cell through the SRAM peripheral circuit for storage. When working in the in-memory computing mode, the input data is pre-coded first, and the stored weight data is read out at the same time, and the multiplexing computing unit is used to perform the multiply-accumulate operation to realize the in-memory computing function. The multiplexing calculation unit means that every 16 6T SRAM Cells are time-multiplexed with the same calculation unit, and only one 6T Cell is gated during each calculation. Compared with the scheme that each 6T Cell requires one calculation unit, This time-division multiplexing strategy greatly reduces the area of the in-memory computing circuit and is more suitable for edge computing devices.

The technical scheme of the present invention is specifically:

An in-memory computing circuit based on SRAM, the in-memory computing unit includes a 6T SRAM Cell array of 16 rows and 64 columns and a 64-column multiplexing computing unit; The 6T SRAMCell of the row is connected to the read-write signal line WL, and the input data is divided into the first input terminal, the second input terminal and the third input terminal after being encoded and connected to the multiplexing calculation unit, and the multiplexing calculation unit obtains the weight through the signal lines BLP and BLN. Specifically, each multiplexing calculation unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein the gate of the first NMOS transistor is connected to the signal line BLP, and the drain thereof is connected to the first NMOS transistor. The source of the two NMOS transistors; the gate of the second NMOS transistor is connected to the first input terminal, and its drain is connected to the second input terminal; the gate of the third NMOS transistor is connected to the signal line BLN, and its drain is connected to the fourth NMOS transistor. source; the gate of the fourth NMOS tube is connected to the first input terminal, and its drain is connected to the third input terminal; the source of the first NMOS tube is connected to the source of the third NMOS tube as an output terminal;

The input data is encoded and converted into voltage signals of the first input terminal, the second input terminal, and the third input terminal. Specifically, when the input data is 1, the first input terminal is the power supply voltage after encoding, and the second input terminal is the power supply voltage. , the third input terminal is 0 voltage; when the input data is 0, the voltage signals of the first input terminal, the second input terminal and the third input terminal are all 0 after encoding; when the input data is -1, the first input terminal after encoding is the power supply voltage, the second input terminal is 0 voltage, and the third input terminal is the power supply voltage.

The beneficial effects of the present invention are as follows: the present invention proposes an in-memory computing unit based on SRAM, and realizes in-memory computing by multiplexing the computing unit, so that the data can be calculated in the memory, and the convolutional neural network can be significantly reduced. data throughput and power consumption for applications such as

Description of drawings

FIG. 1 is an illustration of the overall circuit structure of the present invention.

FIG. 2 is a schematic diagram of the present invention encoding an input.

FIG. 3 is a schematic diagram of the calculation process of the present invention.

FIG. 4 is a schematic diagram of the calculation result of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and clear, the specific embodiments of the present invention will be described in detail and completely below with reference to the accompanying drawings.

As shown in FIG. 1 , the present invention is mainly composed of an SRAM array and a multiplexing calculation unit. Before the calculation, the weight data that needs to be calculated is written into the 6T SRAM Cell through the SRAM peripheral circuit for storage. When the circuit works in the memory calculation mode, the input encoding circuit encodes the input data according to Figure 2, that is, different inputs correspond to different voltages on INV, INS_N, and INS_P. At the same time, every 16 SRAM Cells time-division multiplex the same computing unit, that is, every clock cycle, only one of every 16 6T SRAMs is turned on for calculation. Compared with the solution that requires one computing unit for each 6T Cell, this time-division multiplexing strategy greatly reduces the area of the in-memory computing circuit and is more suitable for edge computing devices.

The specific calculation process is shown in Figure 3. First, a 6T Cell is gated, and its weight data is reflected on the BLP and BLN. If the data stored in the weight is +1, the BLP voltage is VDD, and the voltage on the BLN is 0; If the data stored in the weight is -1, the BLP voltage is 0, and the voltage on the BLN is VDD. The encoded voltage of the input data is reflected on INV, INS_P and INS_N. If the input is +1, the voltage of INV and INS_P is VDD, and the voltage of INS_N is 0. In this way, the paths of N1 and N2 are turned on, and the paths of N3 and N4 are closed, that is, the OUTPUT is charged. If the calculation result is 1, it is reflected as the charging current on OUTPUT; if the calculation result is 0, it is not conducting, that is, neither charging nor discharging; if the calculation result is -1, it is reflected as the discharge current on OUTPUT. The calculation results of the multiplexed calculation units in the same row act together on one output bit line, as shown in Figure 4.

To sum up, the present invention proposes an in-memory computing unit based on SRAM, including a 6T SRAM Cell array and a multiplexing computing unit. The in-memory computing circuit realizes in-memory computing by pre-writing the weight data into the SRAM for storage, and then performing computation by multiplexing the computing unit and the input data. Although the in-memory computing unit proposed by the present invention increases the area of the memory, the data can be calculated in the memory, which can significantly reduce the data handling and power consumption of applications such as convolutional neural networks.

Claims (2)

1. an in-memory computing circuit based on SRAM, is characterized in that, this in-memory computing unit comprises the 6TSRAM Cell array of 16 rows and 64 columns and 64 columns of multiplexing computing units; The 6T SRAM Cell of each row is connected to the column read-write signal line BLP and BLN, the 6T SRAM Cell in each row is connected to the read-write signal line WL, the input data is divided into the first input terminal, the second input terminal and the third input terminal after being encoded and connected to the multiplexing calculation unit, and the multiplexing calculation unit passes the signal Lines BLP and BLN obtain weight data, and the weight data has been stored in the 6T SRAM Cell through the signal lines BLP and BLN before calculation; specifically, each multiplexing calculation unit includes a first NMOS tube, a second NMOS tube, and a third NMOS tube. The gate of the first NMOS tube is connected to the signal line BLP, the drain of the first NMOS tube is connected to the source of the second NMOS tube; the gate of the second NMOS tube is connected to the first input terminal, and the drain of the second NMOS tube is connected to the first input terminal. Two input terminals; the gate of the third NMOS tube is connected to the signal line BLN, and its drain is connected to the source of the fourth NMOS tube; the gate of the fourth NMOS tube is connected to the first input terminal, and its drain is connected to the third input terminal; The source of the first NMOS transistor and the source of the third NMOS transistor are connected as an output terminal; The input data is encoded and converted into voltage signals of the first input terminal, the second input terminal, and the third input terminal. Specifically, when the input data is 1, the first input terminal is the power supply voltage after encoding, and the second input terminal is the power supply voltage. , the third input terminal is 0 voltage; when the input data is 0, the voltage signals of the first input terminal, the second input terminal and the third input terminal are all 0 after encoding; when the input data is -1, the first input terminal after encoding is the power supply voltage, the second input terminal is 0 voltage, and the third input terminal is the power supply voltage. 2. a kind of in-memory computing circuit based on SRAM according to claim 1, is characterized in that, 16 6TSRAM Cells of each row time-division multiplexing the same computing unit, and only 1 6T Cell is selected during each calculation Pass.

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