CN114978042B - Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit - Google Patents
Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit Download PDFInfo
- Publication number
- CN114978042B CN114978042B CN202210503100.0A CN202210503100A CN114978042B CN 114978042 B CN114978042 B CN 114978042B CN 202210503100 A CN202210503100 A CN 202210503100A CN 114978042 B CN114978042 B CN 114978042B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- transistor
- switched
- resistance
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1203—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier being a single transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明涉及开关电容电路、包括该开关电容电路的压控振荡器以及形成开关电容电路的方法。按照本发明一个方面的开关电容电路包括：第一电容；第二电容；以及晶体管，其设置在所述第一电容和所述第二电容之间，所述晶体管的栅极设置有高阻值电阻。
The invention relates to a switched capacitor circuit, a voltage controlled oscillator including the switched capacitor circuit and a method of forming a switched capacitor circuit. A switched capacitor circuit according to one aspect of the present invention includes: a first capacitor; a second capacitor; and a transistor disposed between the first capacitor and the second capacitor, and a gate of the transistor is provided with a high resistance value resistance.
Description
Technical Field
The present invention relates to the field of circuit technology, and more particularly, to a switched-capacitor circuit, a voltage-controlled oscillator including the switched-capacitor circuit, and a method of forming the switched-capacitor circuit.
Background
In a circuit system, the total energy stored by the system divided by the energy lost in a single cycle is defined as the quality factor (Q). In a circuit system, it is desirable to lose less energy as well as better, i.e., to have a larger Q value.
At present, a switch capacitor array is generally arranged in a voltage-controlled oscillator, and one or more switches in the switch capacitor array are controlled to be closed according to a target oscillation frequency, so that the voltage-controlled oscillator connected with a certain capacitance value can output a frequency closest to the target oscillation frequency.
However, as the signal frequency becomes higher, the performance index requirement of the voltage-controlled oscillator becomes higher. Although the switched capacitor array can effectively enlarge the tuning range of the voltage-controlled oscillator, a certain power loss is generated when a high-frequency signal passes through the switched capacitor array, and the power loss is mainly caused by the equivalent series resistance of the switched capacitor array. The switched capacitor array with a low Q value has poor response capability to high-frequency signals and even causes severe attenuation to the high-frequency signals. In addition, in the conventional switched capacitor array structure, a control voltage from the outside is directly connected to the gate of the transistor to generate large noise interference, and an additional capacitance to ground is generated in the ac path.
Disclosure of Invention
To solve or at least alleviate one or more of the above problems, the following technical solutions are provided.
According to a first aspect of the present invention, there is provided a switched capacitor circuit comprising: a first capacitor; a second capacitor; and a transistor provided between the first capacitor and the second capacitor, a gate of the transistor being provided with a high-resistance resistor.
According to an embodiment of the present invention, a resistance value of the high resistance resistor is greater than 20k ohms.
The switched-capacitor circuit according to an embodiment of the invention or any of the above embodiments, wherein the source of the transistor is connected to the first capacitor, and the drain of the transistor is connected to the second capacitor.
In the switched capacitor circuit according to the embodiment or any one of the above embodiments, the first capacitor and the second capacitor are configured in a first preset manner, and the first preset manner reduces a resistance value of a first parasitic resistor of the first capacitor and a resistance value of a second parasitic resistor of the second capacitor.
The switched capacitor circuit of one or more embodiments of the invention, wherein the first capacitor and the second capacitor are MOM capacitors, the MOM capacitors including a plurality of stacked metal layers, each of the plurality of stacked metal layers including a plurality of interdigitated metals and a common fulcrum connecting the plurality of interdigitated metals.
The switched capacitor circuit according to an embodiment of the invention or any of the above embodiments, wherein when the first capacitor and the second capacitor are MOM capacitors, the first predetermined manner includes one or more of the following manners: increasing the width of the interdigital metal to reduce the resistance value of the resistance of the interdigital metal; increasing the width of the common fulcrum to decrease the resistance of the resistor of the common fulcrum; and providing a plurality of vias between the plurality of stacked metal layers.
In the switched capacitor circuit according to the embodiment or any one of the above embodiments of the invention, the transistor is configured in a second predetermined manner, and the second predetermined manner reduces a resistance value of an equivalent resistor of the transistor.
The switched-capacitor circuit of one or more embodiments of the invention, wherein the second predetermined manner includes increasing a value of W/L of the transistor to a predetermined threshold, wherein W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance between the switched-capacitor circuit and a substrate and a quality factor of the switched-capacitor circuit.
The switched capacitor circuit according to an embodiment of the invention or any of the above embodiments, wherein the transistor is a MOS transistor.
According to a second aspect of the present invention there is provided a voltage controlled oscillator comprising a switched capacitor circuit according to the first aspect of the present invention.
According to a third aspect of the present invention there is provided a method of forming a switched capacitor circuit comprising: setting a first capacitor; setting a second capacitor; a transistor is arranged between the first capacitor and the second capacitor; and setting a high-resistance resistor on the grid of the transistor.
According to an embodiment of the present invention, in the method for forming the switched capacitor circuit, a resistance value of the high resistance resistor is greater than 20k ohms.
The method of forming a switched-capacitor circuit according to an embodiment of the invention or any of the embodiments above, wherein the method further comprises: connecting a source of the transistor to the first capacitor, and connecting a drain of the transistor to the second capacitor.
The method of forming a switched-capacitor circuit according to an embodiment of the invention or any of the embodiments above, wherein the method further comprises: the first capacitor and the second capacitor are configured in a first preset mode, and the resistance value of a first parasitic resistor of the first capacitor and the resistance value of a second parasitic resistor of the second capacitor are reduced in the first preset mode.
The method of forming a switched-capacitor circuit according to an embodiment of the invention or any of the embodiments above, wherein the method further comprises: implementing the first and second capacitors as an MOM capacitor including a plurality of stacked metal layers, each of the plurality of stacked metal layers including a plurality of interdigitated metals and a common fulcrum connecting the plurality of interdigitated metals.
The method for forming a switched capacitor circuit according to an embodiment or any previous embodiment of the invention, wherein when the first capacitor and the second capacitor are implemented as MOM capacitors, the first preset mode includes one or more of the following modes: increasing the width of the interdigital metal to reduce the resistance of the interdigital metal; increasing the width of the common fulcrum to decrease the resistance of the resistor of the common fulcrum; and providing a plurality of vias between the plurality of stacked metal layers.
The method of forming a switched-capacitor circuit according to an embodiment of the invention or any of the embodiments above, wherein the method further comprises: the transistor is configured in a second preset mode, and the resistance value of the equivalent resistor of the transistor is reduced in the second preset mode.
The method of forming a switched-capacitor circuit according to one or more embodiments of the invention, wherein the second predetermined manner includes increasing a value of W/L of the transistor to a predetermined threshold, where W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance between the switched-capacitor circuit and a substrate and a quality factor of the switched-capacitor circuit.
The method of forming a switched capacitor circuit according to one embodiment or any of the above embodiments, wherein the transistor is a MOS transistor.
The switched capacitor circuit according to one or more embodiments of the present invention can reduce noise interference from the outside by providing a high-resistance resistor at the gate of the transistor, and can improve capacitance to ground to differential mode capacitance by making both the source and the drain of the transistor present a high-resistance state to the gate of the transistor, thereby reducing noise interference coupled to ground. In addition, the switched capacitor circuit according to one or more embodiments of the present invention can significantly increase the Q value of the switched capacitor circuit, reduce power loss generated when a high frequency signal passes through the switched capacitor circuit, and improve the response capability of the switched capacitor circuit to the high frequency signal.
Drawings
The above and/or other aspects and advantages of the present invention will become more apparent and more readily appreciated from the following description of the various aspects taken in conjunction with the accompanying drawings, in which like or similar elements are designated with like reference numerals. In the drawings:
FIG. 1 shows a switched-capacitor circuit in accordance with one or more embodiments of the invention.
Fig. 2 illustrates a parasitic equivalent model of the switched-capacitor circuit shown in fig. 1 in accordance with one or more embodiments of the invention.
Fig. 3 shows a single capacitor layer layout structure of the MOM capacitor.
Fig. 4 shows a flow diagram of a method of forming a switched-capacitor circuit in accordance with one or more embodiments of the invention.
Detailed Description
The following description of the specific embodiments is merely exemplary in nature and is in no way intended to limit the disclosed technology or the application and uses of the disclosed technology. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
In the following detailed description of embodiments, numerous specific details are set forth in order to provide a more thorough understanding of the disclosed technology. It will be apparent, however, to one of ordinary skill in the art that the disclosed techniques may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.
Words such as "comprising" and "comprises" mean that, in addition to having elements or steps which are directly and explicitly stated in the description, the solution of the invention does not exclude other elements or steps which are not directly or explicitly stated. Terms such as "first" and "second" do not denote an order of the elements in time, space, size, etc., but rather are used to distinguish one element from another.
Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows a switched-capacitor circuit in accordance with one or more embodiments of the invention.
As shown in fig. 1, the switched capacitor circuit 10 includes a first capacitor C0 and a second capacitor C1, and a transistor provided between the first capacitor C0 and the second capacitor C1. Alternatively, the transistor may be a MOS transistor, and further may be an NMOS transistor, and the gate terminal thereof may be connected to the control voltage.
In fig. 1, S denotes a source of a transistor, G denotes a gate of the transistor, and D denotes a drain of the transistor. The source S of the transistor is connected to the first capacitor C0, and the drain D of the transistor is connected to the second capacitor C1. In the transistor, the resistors Rhs and Rhd are high-resistance resistors connected to the source S and the drain D of the transistor, respectively, and a high-resistance resistor Rhg is provided at the gate G of the transistor. Alternatively, the resistance value of the high resistance resistor Rhg may be greater than 20k ohms.
As shown in fig. 1, by providing a high-resistance resistor Rhg at the gate G of the transistor, noise disturbance from the outside (e.g., noise disturbance due to direct connection of a control voltage from the outside to the gate G of the transistor) can be reduced on the one hand, and on the other hand, both the source S of the transistor and the drain D of the transistor are made to assume a high-resistance state toward the gate G of the transistor, so that capacitance to ground to differential mode capacitance can be improved, thereby reducing noise disturbance of ground coupling.
Fig. 2 illustrates a parasitic equivalent model of the switched-capacitor circuit shown in fig. 1 in accordance with one or more embodiments of the invention.
As shown in fig. 2, the parasitic equivalent model 20 of the switched-capacitor circuit 10 shown in fig. 1 includes a first capacitor C0 and a second capacitor C1, and a transistor provided between the first capacitor C0 and the second capacitor C1. Wherein the resistor Rc0 is a first parasitic resistor as the first capacitor C0, and the resistor Rc1 is a second parasitic resistor as the second capacitor C1. In the transistor, the resistance Rmsw is an equivalent resistance as a transistor, and the resistances Rhs and Rhd are high-resistance resistances connected to the source S and the drain D of the transistor, respectively. The capacitance Cmgnd is a parasitic capacitance between the switched capacitor circuit and the substrate.
Alternatively, the transistor may be a MOS transistor, and further may be an NMOS transistor, and the gate terminal thereof may be connected to the control voltage.
Based on the parasitic equivalent model 20 of the switched-capacitor circuit 10 shown in fig. 1 according to one or more embodiments of the invention shown in fig. 2, the quality factor Q of the switched-capacitor circuit 10 shown in fig. 1 may be represented by the following equation:
wherein,
represents the oscillation frequency of the signal from the voltage-controlled oscillator>
Respectively, represents the capacitance values of the first capacitor C0 and the second capacitor C1, and->
Respectively represents the resistance value of the first parasitic resistor Rc0 of the first capacitor C0 and the resistance value of the second parasitic resistor Rc1 of the second capacitor C1, and ^>
Representing the resistance of the equivalent resistance Rmsw of the transistor.
Based on the above formula, it can be seen that the parallel capacitance can be reduced
Or to reduce the resistance
In order to improve the quality factor Q of the switched-capacitor circuit 10.
Alternatively, the first capacitor C0 and the second capacitor C1 may be configured in a first preset manner that enables the resistance value of the first parasitic resistor Rc0 of the first capacitor C0 and the resistance value of the second parasitic resistor Rc1 of the second capacitor C1 to be reduced.
Alternatively, the transistor may be configured in a second preset manner, where the second preset manner reduces the resistance value of the equivalent resistor Rmsw of the transistor. Optionally, the second preset manner includes increasing a value of W/L of the transistor to a predetermined threshold, where W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance Cmgnd between the switched-capacitor circuit and the substrate and a quality factor Q of the switched-capacitor circuit. It should be noted that an excessive value of W/L may cause the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate to be too large, and the excessive parasitic capacitance Cmgnd may significantly affect the total capacitance of the first capacitor C0 and the second capacitor C1, and thus the desired frequency of the vco. Therefore, the upper threshold value of the value of W/L needs to be selected so that the parasitic capacitance Cmgnd between the switched-capacitor circuit and the substrate does not significantly affect the total capacitance value of the first and second capacitors C0 and C1 and the quality factor Q of the switched-capacitor circuit reaches a desired value. In a preferred embodiment, the upper threshold value for the value of W/L is selected such that the parasitic capacitance Cmgnd between the switched-capacitor circuit and the substrate is less than one twentieth of the total capacitance value of the first and second capacitors C0, C1. In another preferred embodiment, the upper threshold value of the value of W/L is selected such that the quality factor Q of the switched-capacitor circuit is larger than 30, i.e. it is ensured that the quality factor Q of the switched-capacitor circuit is much larger than the quality factor Q of the inductor in the oscillator. In a general process design, the quality factor Q of an inductor in an oscillator is about 3-8, so that the upper threshold of the value of W/L needs to be selected so that the quality factor Q of a switched capacitor circuit is greater than 30. By configuring the transistors in the second preset manner, the resistance value of the equivalent resistor Rmsw of the transistor can be significantly reduced, so that the quality factor Q of the switched capacitor circuit 10 is improved.
In one embodiment, the first capacitor C0 and the second capacitor C1 may be implemented by metal-oxide-metal (MOM) capacitors. The MOM capacitor adopts a method of combining a finger-shaped structure and a lamination layer, and utilizes a capacitor formed by metals on the same layer on the basis of the layout of the original decoupling capacitor, and a structure of stacking multiple layers of metals is connected in parallel with the decoupling capacitor, so that a larger capacitance value can be obtained in a smaller area.
Fig. 3 shows a single capacitor layer layout structure of the MOM capacitor. The capacitance value of the MOM capacitor is mainly formed by the sidewall capacitance of two adjacent interdigital metals, for example, the MOM capacitor disposed longitudinally as shown in fig. 3, which includes 12 interdigital metals 310. Assuming that the capacitance of a unit capacitor formed by two adjacent interdigital metals 310 in the MOM capacitor is Cunit, under the condition that the width and the length of the interdigital metals are not changed, when 12 interdigital metals 310 are included in the MOM capacitor, the capacitance of the MOM capacitor is 11 × Cunit. It is noted that the number of interdigitated metals 310 shown in fig. 3 is merely exemplary, and the number of interdigitated metals 310 may be more than 12 or less than 12 without departing from the spirit and scope of the present invention.
According to a preferred embodiment of the present invention, the MOM capacitor may include a plurality of metal layers shown in fig. 3 arranged in a stack, each of the plurality of metal layers arranged in a stack including a plurality of interdigitated metals 310 and a common anchor 320 connecting the plurality of interdigitated metals 310.
Illustratively, when the number of the interdigital metals 310 shown in fig. 3 is 3, based on the parasitic equivalent model of the MOM capacitance shown in fig. 3, the equivalent resistance R of the MOM capacitance can be obtained pn =2*(((((R 320 +R 310 )//R 310 )+R 320 )//R 310 )+R 320 ) Wherein R is 310 Represents the resistance of a single interdigital metal 310, and R 320 A resistance value of the common fulcrum 320 corresponding to the single interdigital metal 310 is shown.
In one embodiment, when the first capacitor C0 and the second capacitor C1 are MOM capacitors, the first preset manner may include one or more of the followingThe method comprises the following steps: increasing the width w1 of the interdigital metal 310 to reduce the resistance R of the interdigital metal 310 310 (ii) a Increasing the width w2 of the common pivot 320 to reduce the resistance R of the common pivot 320 (ii) a And providing a plurality of vias between the plurality of stacked metal layers. In a preferred embodiment, the width w1 of the interdigitated metal 310 may be increased to the minimum width that the process used can place vias between two adjacent ones of the plurality of stacked metal layers. In another preferred embodiment, the width w2 of the common pivot 320 may be increased to about 8 times the width w1 of the interdigital metal 310, thereby increasing the Q value of the switched capacitor circuit without introducing an unnecessary parasitic capacitance Cmgnd and without introducing an unnecessary capacitance area.
By configuring the first capacitor C0 and the second capacitor C1 in the first predetermined manner, the resistance of the first parasitic resistor Rc0 of the first capacitor C0 and the resistance of the second parasitic resistor Rc1 of the second capacitor C1 can be significantly reduced, thereby improving the quality factor Q of the switched capacitor circuit 10. Experiments show that by configuring the first capacitor C0 and the second capacitor C1 in the first preset manner, the quality factor Q of the first capacitor C0 and the second capacitor C1 can be improved from about 15 to about 190 at a signal frequency of 28 GHz.
Through experimental simulation, compared with the Q value of 9 of the switched capacitor circuit in the conventional process when the signal frequency is 28GHz, the switched capacitor circuit according to one or more embodiments of the invention can obtain the Q value of 34 when the signal frequency is 28 GHz. Thus, the performance of switched-capacitor circuits according to one or more embodiments of the present invention is improved by several times.
The switched capacitor circuit according to one or more embodiments of the present invention can reduce noise interference from the outside by providing a high-resistance resistor at the gate of the transistor, and can improve capacitance to ground to differential mode capacitance by making both the source and the drain of the transistor present a high-resistance state to the gate of the transistor, thereby reducing noise interference coupled to ground. In addition, the switched capacitor circuit according to one or more embodiments of the present invention can significantly increase the Q value of the switched capacitor circuit, reduce power loss generated when a high frequency signal passes through the switched capacitor circuit, and improve the response capability of the switched capacitor circuit to the high frequency signal.
Fig. 4 shows a flow diagram of a method of forming a switched-capacitor circuit in accordance with one or more embodiments of the invention.
As shown in fig. 4, a method of forming a switched-capacitor circuit in accordance with one or more embodiments of the invention includes the steps of:
step 410: setting a first capacitor C0;
step 420: a second capacitor C1 is arranged;
step 430: a transistor is arranged between the first capacitor C0 and the second capacitor C1; and
step 440: a high resistance resistor Rhg is provided at the gate of the transistor.
Alternatively, the transistor may be a MOS transistor, and further may be an NMOS transistor, and the gate terminal thereof may be connected to the control voltage.
Optionally, the method for forming a switched capacitor circuit according to one or more embodiments of the present invention further includes connecting the source S of the transistor to the first capacitor C0, and connecting the drain D of the transistor to the second capacitor C1.
Alternatively, the resistance value of the high resistance resistor Rhg may be greater than 20k ohms.
By providing the high-resistance resistor Rhg at the gate G of the transistor, noise disturbance from the outside (e.g., noise disturbance due to direct connection of a control voltage from the outside to the gate G of the transistor) can be reduced on the one hand, and on the other hand, both the source S of the transistor and the drain D of the transistor are made to assume a high-resistance state toward the gate G of the transistor, so that capacitance to ground to differential-mode capacitance can be improved, thereby reducing noise disturbance of ground coupling.
Optionally, the method of forming a switched capacitor circuit according to one or more embodiments of the present invention may further include configuring the first capacitor C0 and the second capacitor C1 in a first preset manner that enables a reduction in the resistance value of the first parasitic resistor Rc0 of the first capacitor C0 and the resistance value of the second parasitic resistor Rc1 of the second capacitor C1.
Optionally, the method for forming the switched capacitor circuit according to one or more embodiments of the present invention may further include configuring the transistor in a second preset manner, where the second preset manner decreases the resistance value of the equivalent resistance Rmsw of the transistor. Optionally, the second preset manner includes increasing a value of W/L of the transistor to a predetermined threshold, where W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance Cmgnd between the switched-capacitor circuit and the substrate and a quality factor Q of the switched-capacitor circuit. By configuring the transistors in the second preset manner, the resistance value of the equivalent resistor Rmsw of the transistor can be significantly reduced, so that the quality factor Q of the switched capacitor circuit 10 is improved.
In one embodiment, the first capacitor C0 and the second capacitor C1 may be implemented by MOM capacitors. When the first capacitor C0 and the second capacitor C1 are MOM capacitors, the first preset manner may include one or more of the following manners: increasing the width of the interdigital metal to reduce the resistance of the interdigital metal; increasing the width of the common fulcrum to reduce the resistance of the resistor of the common fulcrum; and providing a plurality of vias between the plurality of stacked metal layers. By configuring the first capacitor C0 and the second capacitor C1 in the first predetermined manner, the resistance of the first parasitic resistor Rc0 of the first capacitor C0 and the resistance of the second parasitic resistor Rc1 of the second capacitor C1 can be significantly reduced, thereby improving the quality factor Q of the switched capacitor circuit 10. Experiments show that by configuring the first capacitor C0 and the second capacitor C1 in the first preset manner, the quality factor Q of the first capacitor C0 and the second capacitor C1 can be improved from about 15 to about 190 at a signal frequency of 28 GHz.
The method for forming the switched capacitor circuit according to one or more embodiments of the present invention can reduce noise interference from the outside on the one hand, and can improve capacitance to ground to differential mode capacitance by setting a high resistance value resistor at the gate of the transistor on the other hand, so that the gate of the transistor is in a high resistance value state when viewed from the source and the drain of the transistor, thereby reducing noise interference of ground coupling. In addition, the method for forming the switched capacitor circuit according to one or more embodiments of the invention can significantly increase the Q value of the switched capacitor circuit, reduce the power loss generated when a high-frequency signal passes through the switched capacitor circuit, and improve the response capability of the switched capacitor circuit to the high-frequency signal.
In addition, as described above, the present invention may also be embodied as a voltage controlled oscillator including a switched capacitor circuit according to an aspect of the present invention.
The embodiments and examples set forth herein are presented to best explain embodiments in accordance with the invention and its particular application and to thereby enable those skilled in the art to make and utilize the invention. However, those skilled in the art will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. The description as set forth is not intended to cover all aspects of the invention or to limit the invention to the precise form disclosed.
Claims (13)
1. A switched-capacitor circuit, comprising:
a first capacitor;
a second capacitor; and
a transistor provided between the first capacitor and the second capacitor, a gate of the transistor being provided with a high-resistance resistor;
the first capacitor and the second capacitor are configured in a first preset mode, and the first preset mode enables the resistance value of a first parasitic resistor of the first capacitor and the resistance value of a second parasitic resistor of the second capacitor to be reduced;
the first capacitor and the second capacitor are MOM capacitors, each MOM capacitor includes a plurality of metal layers arranged in a stacked manner, each metal layer of the plurality of metal layers arranged in a stacked manner includes a plurality of interdigital metals and a common supporting point for connecting the plurality of interdigital metals, and the first preset mode includes one or more of the following modes:
increasing the width of the interdigital metal to reduce the resistance of the interdigital metal;
increasing the width of the common fulcrum to decrease the resistance of the resistor of the common fulcrum; and
a plurality of vias is disposed between the plurality of stacked metal layers.
2. The circuit of claim 1, wherein the high resistance resistor has a resistance value greater than 20k ohms.
3. The circuit of claim 1, wherein a source of the transistor is connected to the first capacitance and a drain of the transistor is connected to the second capacitance.
4. The circuit of claim 1, wherein the transistor is configured in a second predetermined manner that causes a decrease in a resistance of an equivalent resistance of the transistor.
5. The circuit of claim 4, wherein the second preset manner comprises increasing a value of W/L of the transistor to a predetermined threshold, wherein W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance between the switched-capacitor circuit and a substrate and a quality factor of the switched-capacitor circuit.
6. The circuit of claim 1, wherein the transistor is a MOS transistor.
7. A voltage controlled oscillator comprising a switched capacitor circuit as claimed in any one of claims 1 to 6.
8. A method of forming a switched-capacitor circuit, the method comprising:
setting a first capacitor;
setting a second capacitor;
a transistor is arranged between the first capacitor and the second capacitor; and
a high resistance resistor is provided at the gate of the transistor,
wherein the method further comprises:
configuring the first capacitor and the second capacitor in a first predetermined manner that reduces a resistance value of a first parasitic resistor of the first capacitor and a resistance value of a second parasitic resistor of the second capacitor,
wherein the method further comprises:
implementing the first and second capacitors as a MOM capacitor, the MOM capacitor including a plurality of stacked metal layers, each of the plurality of stacked metal layers including a plurality of interdigitated metals and a common fulcrum connecting the plurality of interdigitated metals, the first predetermined manner including one or more of:
increasing the width of the interdigital metal to reduce the resistance of the interdigital metal;
increasing the width of the common fulcrum to decrease the resistance of the resistor of the common fulcrum; and
a plurality of vias is disposed between the plurality of stacked metal layers.
9. The method of claim 8, wherein the high resistance resistor has a resistance value greater than 20k ohms.
10. The method of claim 8, wherein the method further comprises:
connecting a source of the transistor to the first capacitor, and connecting a drain of the transistor to the second capacitor.
11. The method of claim 8, wherein the method further comprises:
the transistor is configured in a second preset mode, and the resistance value of the equivalent resistor of the transistor is reduced in the second preset mode.
12. The method of claim 11, wherein the second preset manner comprises increasing a value of W/L of the transistor to a predetermined threshold, wherein W represents an active region width of the transistor and L represents a channel length of the transistor, the predetermined threshold being determined based on a parasitic capacitance between the switched-capacitance circuit and a substrate and a quality factor of the switched-capacitance circuit.
13. The method of claim 8, wherein the transistor is a MOS transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210503100.0A CN114978042B (en) | 2022-05-10 | 2022-05-10 | Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit |
| PCT/CN2022/093604 WO2023216289A1 (en) | 2022-05-10 | 2022-05-18 | Switched-capacitor circuit, voltage-controlled oscillator, and method for forming switched-capacitor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210503100.0A CN114978042B (en) | 2022-05-10 | 2022-05-10 | Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114978042A CN114978042A (en) | 2022-08-30 |
| CN114978042B true CN114978042B (en) | 2023-03-24 |
Family
ID=82980808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210503100.0A Active CN114978042B (en) | 2022-05-10 | 2022-05-10 | Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114978042B (en) |
| WO (1) | WO2023216289A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4465533A1 (en) * | 2023-05-15 | 2024-11-20 | STMicroelectronics International N.V. | Quadrature oscillators |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013102159A1 (en) * | 2011-12-30 | 2013-07-04 | Tensorcom, Inc. | Method and apparatus of a resonant oscillator separately driving two independent functions |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147567A (en) * | 1998-05-29 | 2000-11-14 | Silicon Laboratories Inc. | Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications |
| US9584097B2 (en) * | 2014-04-29 | 2017-02-28 | Infineon Technologies Ag | System and method for a switchable capacitance |
| US10432141B2 (en) * | 2015-12-18 | 2019-10-01 | Qualcomm Incorporated | Multimode voltage controlled oscillator |
| EP3514828B1 (en) * | 2018-01-19 | 2021-08-25 | Socionext Inc. | Semiconductor integrated circuitry |
| CN112003613B (en) * | 2020-09-02 | 2023-11-21 | 重庆西南集成电路设计有限责任公司 | Dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator |
-
2022
- 2022-05-10 CN CN202210503100.0A patent/CN114978042B/en active Active
- 2022-05-18 WO PCT/CN2022/093604 patent/WO2023216289A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013102159A1 (en) * | 2011-12-30 | 2013-07-04 | Tensorcom, Inc. | Method and apparatus of a resonant oscillator separately driving two independent functions |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4465533A1 (en) * | 2023-05-15 | 2024-11-20 | STMicroelectronics International N.V. | Quadrature oscillators |
| FR3148884A1 (en) * | 2023-05-15 | 2024-11-22 | Stmicroelectronics International N.V. | Quadrature oscillators |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114978042A (en) | 2022-08-30 |
| WO2023216289A1 (en) | 2023-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111565040B (en) | Voltage-controlled oscillator based on dual common mode resonance | |
| CN100539396C (en) | Oscillation circuit and L load differential circuit | |
| JP5476196B2 (en) | Circuit structure, design structure and manufacturing method for switchable on-chip slow wave transmission line band elimination filter | |
| KR101719453B1 (en) | Transistor and tunable inductance | |
| CN111865255B (en) | Radio frequency module design method, radio frequency module and communication equipment | |
| JP3892383B2 (en) | Voltage controlled oscillator | |
| US8305151B2 (en) | Resonance type oscillation circuit and semiconductor device | |
| TW201935497A (en) | A switching inductor device and a oscillator device | |
| CN114978042B (en) | Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit | |
| CN110959197A (en) | Distributed LC filter structure | |
| US20080169883A1 (en) | LC resonant circuit | |
| JP7275624B2 (en) | Frequency band variable high frequency amplifier | |
| CN113556089B (en) | LC Oscillator and Related Dual-Core Oscillator | |
| CN108172565A (en) | A kind of MOM capacitor and integrated circuit | |
| JP2007174519A (en) | Microwave circuit | |
| JP2011147090A (en) | Stacked multiplexer, stacked triplexer and filter circuit | |
| CN105517318A (en) | Power supply EBG structure based on open-loop resonator and X-shaped bridge | |
| US6781482B2 (en) | Integrated circuit | |
| Politi et al. | Multi-layer realization of symmetrical differential inductors for RF silicon IC's | |
| CN114257202B (en) | Filter circuit and multiplexer | |
| US6952044B2 (en) | Monolithic bridge capacitor | |
| JP2008130683A (en) | Semiconductor integrated circuit device | |
| El-Gouhary et al. | Analysis of transformer-based resonator quality factor and bandwidth and the implications to VCOs | |
| JP5789003B2 (en) | Oscillation circuit and semiconductor device | |
| JP2010192466A (en) | Wide band capacitance element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |