CN114911418A - A radio signal storage and playback device - Google Patents

Abstract

The embodiment of this specification provides a radio signal storage and playback device, including: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer; the radio frequency front end is used to receive the signal to be analyzed through an antenna, and The signal to be analyzed is subjected to at least one of amplification, filtering and frequency mixing processing to obtain an intermediate frequency signal; the AD data acquisition module is used to sample the intermediate frequency signal, and the FPGA processor is used to perform digital frequency shifting, spectrum calculation, At least one of digital demodulation, storage and playback control, trigger signal identification and trigger processing, and uploading the data generated in the processing to the host computer when receiving instructions from the host computer; DDR3 memory chips are used for data processing. Category storage.

Description

A radio signal storage and playback device

technical field

This specification relates to the field of radio monitoring, in particular to a radio signal storage and playback device.

Background technique

With the development of society, wireless communication plays an increasingly important role in national security and national life security, and radio signal storage and playback devices are used to search, measure, analyze, identify, and identify radiation sources. Direction finding and positioning are an important part of wireless communication technology. As the radio environment becomes more and more complex, related technical indicators such as the sensitivity, stability, miniaturization, bandwidth, and analysis speed of the monitoring system also need to be upgraded, especially with the addition of some offline analysis application scenarios.

Therefore, it is desirable to provide a spectrum analysis device, method and storage medium for a radio signal storage and playback device, which can realize the classification, storage and management of data sources, identification and storage of abnormal signals, and matching of playback rates through an FPGA processor, thereby enriching radio signals. offline analysis capabilities.

SUMMARY OF THE INVENTION

One or more embodiments of this specification provide a radio signal storage and playback device, including: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer; the radio frequency front end and the AD The data acquisition module is connected in communication, and the radio frequency front end is used to receive the signal to be analyzed through the antenna, and to perform at least one of amplifying, filtering, and frequency mixing processing on the signal to be analyzed, so as to obtain an intermediate frequency signal; the The AD data acquisition module is connected in communication with the FPGA processor, and the AD data acquisition module is used to sample the intermediate frequency signal, and upload the obtained sampling data to the FPGA processor; the FPGA processor is respectively connected to the FPGA processor. The DDR3 memory chip, the host computer, and the digital walkie-talkie are connected for communication, and the FPGA processor is used to perform digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal identification and Triggering at least one of the processes, and uploading the data generated in the processing to the host computer when receiving an instruction from the host computer; the DDR3 memory chip is used for instructions issued by the FPGA processor based on , classify and store the data received by the FPGA processor, and use it as a data source when the FPGA processor plays back data; the digital walkie-talkie is connected to the FPGA processor for communication, and the digital walkie-talkie is used to communicate with all The FPGA processor performs data interaction to receive the sound signals under each channel; the host computer is used to run the human-computer interaction software, and obtain user instructions based on the running human-computer interaction software, and send the user instructions to the FPGA processor. The user command is issued, and spectral information is displayed based on the data generated in the process.

In some embodiments, the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is respectively connected with the storage and playback control module, the data The source selection module is in communication connection, and the storage and playback control module is respectively in communication connection with the data source selection module and the digital signal processing module; the data source selection module is in communication connection with the digital signal processing module.

In some embodiments, the digital signal processing module includes: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; the digital filter is respectively connected in communication with the digital demodulation unit and the FFT unit, and the FFT unit Communication connection with the detection unit.

In some embodiments, the sampling working mode of the radio signal storage and playback device includes a real-time sampling working mode and a recording and playback working mode.

In some embodiments, the real-time sampling working mode is implemented in the following manner:

The AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor; the data source selection module transmits the received real-time sampling data to the digital filter of the FPGA processor; the digital filter transmits the received real-time sampling data to the FFT unit and the digital demodulation unit respectively, so as to narrow-band the real-time sampling data respectively Filtering, digital demodulation, spectrum calculation and digital detection operations; the digital demodulation unit and the detection unit respectively transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

In some embodiments, the recording and playback working mode is divided into original IQ data recording and playback and narrow-band IQ data recording and playback based on different data sources.

In some embodiments, the playback of the raw IQ data records is implemented in the following manner:

The AD data acquisition module transmits the real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor; the storage and playback control module performs an abnormal signal on the real-time sampling data. At least one of identification, data packaging, and interface protocol conversion processing, and the processed data is transmitted to the DDR3 memory chip for storage; when data playback is performed, the storage and playback control module is set according to the host computer. The required amount of data is read from the DDR3 memory chip, and data rate matching is performed, so that the playback data matches the rate of the real-time sampling data and is sent to the digital signal processing module for processing; the digital signal processing module will process The data are respectively transmitted to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

In some embodiments, the playback of the narrowband IQ data records is implemented in the following manner:

The AD data acquisition module sequentially transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor; Described digital filter comprises several filter units and the decimation rate of each described filter unit is different; Described digital filter outputs the narrowband IQ data of different bandwidths after the data received, the bandwidth range of described narrowband IQ data is 2kHz-160MHz; the digital filter sends the narrowband IQ data of each file to the storage and playback control module for at least one of abnormal signal identification, data packaging, and interface protocol conversion processing; the storage and the playback control module sends the processed data to the DDR3 storage chip for storage; when performing data playback, the storage and playback control module reads from the DDR3 storage chip according to the required amount of data set by the host computer Take the data, and perform data rate matching, so that the playback data matches the rate of the narrowband IQ data sampled in real time and is sent to the digital signal processing module for processing; the digital signal processing module transmits the processed data to the The digital walkie-talkie can play or the host computer can display the spectrum in real time.

In some embodiments, the operation mode of the storage and playback control module includes a normal mode;

In the normal mode, the radio signal storage and playback device is configured to perform the following operations:

Obtaining the storage parameters set by the user based on the host computer, the storage parameters include storage data source, storage starting point, and storage length; the FPGA processor stores the received sampling data in the DDR3 based on the storage parameters memory chip; after the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt mode; wherein, the execution times of the above-mentioned stored procedure are not less than 1, and each execution of the stored procedure , the host computer has a corresponding file record storage setting; when data playback is performed, the data source for playback is determined based on the host computer;

The amount of playback data and playback speed are controlled based on the FPGA processor to simulate real sampled data; the playback data is processed based on the FPGA processor, and the processed data are respectively transmitted to the digital walkie-talkie for playback or the The host computer performs real-time spectrum display.

In some embodiments, the operation mode of the storage and playback control module includes a trigger mode;

In the trigger mode, the radio signal storage and playback device is configured to:

Before storage, trigger parameters and storage parameters are obtained based on the host computer, where the trigger parameters include the amount of data ahead of the trigger and the trigger threshold; the storage parameters include storage starting points and storage lengths; during storage, the FPGA processor is based on the The storage parameter stores the received sample data in the DDR3 memory chip, and judges abnormal signals and counts the amount of stored data according to the trigger threshold during the storage process; based on the detection status of the abnormal signals, the The FPGA processor performs the following operations respectively: if the abnormal signal is detected after the amount of stored data exceeds the amount of the triggering advance data, the abnormal signal and the data of the remaining data length are continued to be stored, and the storage of the abnormal signal is recorded. location; if the abnormal signal is detected before the amount of stored data reaches the triggering advance data amount, the abnormal signal is discarded and the stored data is cleared; the detection of new abnormal signal is restarted and the amount of stored data is counted , the condition of the abnormal signal will not be detected until the amount of stored data exceeds the amount of data ahead of the trigger; after the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies all The above-mentioned host computer uploads the storage location of the abnormal signal simultaneously; wherein, the execution times of the above-mentioned stored procedure is not less than 1, and each time the execution of the stored procedure, the host computer has a corresponding file record storage setting; when performing data playback, The host computer first issues parameters such as the storage location and storage boundary of the abnormal signal, and determines the data source for playback; controls the playback data volume and playback speed based on the FPGA processor to simulate real sampling data; processes based on the FPGA The controller processes the playback data, and respectively transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

Description of drawings

The present specification will be further described by way of example embodiments, which will be described in detail with reference to the accompanying drawings. These examples are not limiting, and in these examples, the same numbers refer to the same structures, wherein:

1 is a schematic diagram of an application scenario of a radio signal storage and playback device according to some embodiments of this specification;

FIG. 2 is an exemplary structural composition diagram of a radio signal storage and playback apparatus according to some embodiments of the present specification;

3 is an exemplary flowchart of a real-time sampling working mode according to some embodiments of the present specification;

Fig. 4 is an exemplary flow chart of recording and playback of raw IQ data in a recording and playback working mode according to some embodiments of the present specification;

FIG. 5 is an exemplary flow diagram of recording playback of narrowband IQ data according to some embodiments of the present specification;

FIG. 6 is an exemplary flow chart in normal mode according to some embodiments of the present specification;

FIG. 7 is an exemplary flowchart of a trigger mode according to some embodiments of the present specification.

Detailed ways

In order to illustrate the technical solutions of the embodiments of the present specification more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present specification. For those of ordinary skill in the art, without creative efforts, the present specification can also be applied to the present specification according to these drawings. other similar situations. Unless obvious from the locale or otherwise specified, the same reference numbers in the figures represent the same structure or operation.

It is to be understood that "system", "device", "unit" and/or "module" as used herein is a method used to distinguish different components, elements, parts, parts or assemblies at different levels. However, other words may be replaced by other expressions if they serve the same purpose.

As shown in the specification and claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. Generally speaking, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

Flowcharts are used in this specification to illustrate operations performed by a system according to an embodiment of this specification. It should be understood that the preceding or following operations are not necessarily performed in the exact order. Instead, the various steps can be processed in reverse order or simultaneously. At the same time, other actions can be added to these procedures, or a step or steps can be removed from these procedures.

FIG. 1 is a schematic diagram of an application scenario 100 of a radio signal storage and playback apparatus according to some embodiments of the present specification.

In some embodiments, the application scenario 100 may be configured for radio monitoring and analysis, or the like. It can be applied in corresponding communication control scenarios such as radio monitoring, radio identification, and radio management. The application scenario 100 may include a server 110 , a network 120 , a user terminal 130 , a storage device 140 and a signal source 150 . Server 110 may include processing engine 112 . In some embodiments, server 110, user terminal 130, storage device 140, and signal source 150 may connect and/or communicate with each other via a wireless connection (eg, network 120), a wired connection, or a combination thereof.

Server 110 may be used to implement radio processing, such as radio signal storage and playback, and the like. In some embodiments, it may be specifically used to implement monitoring of radios such as satellites.

Server 110 refers to a system with computing capabilities, and in some embodiments, server 110 may be a single server or a group of servers. The server group may be centralized or distributed (eg, server 110 may be a distributed system). In some embodiments, server 110 may be local or remote. For example, server 110 may access information and/or data stored in user terminal 130 and/or storage device 140 via network 120 . As another example, the server 110 may be directly connected to the user terminal 130 and/or the storage device 140 to access stored information and/or data. In some embodiments, server 110 may be implemented on a cloud platform. For example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distribution cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

In some embodiments, server 110 may include processing engine 112 . Processing engine 112 may process information and/or data related to wireless signals. For example, the processing engine 112 may implement radio monitoring in the telematics data acquired by the signal source 150 . In some embodiments, processing engine 112 may include one or more processing engines (eg, a single-core processing engine or a multi-core processor). For example only, the processing engine 112 may include one or more hardware processors, such as a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), controller, microcontroller unit, reduced instruction set computer (RISC), microprocessor, etc. or any combination thereof.

Network 120 may facilitate the exchange of information and/or data. In some embodiments, one or more components in application scenario 100 (eg, server 110 , user terminal 130 , storage device 140 , and signal source 150 ) may send information and/or data over network 120 to other components in application scenario 100 . other components. For example, the processing engine 112 may send the analysis results of the monitored radios to the user terminal 130 via the network 120 . In some embodiments, the network 120 may be a wired network or a wireless network, or the like, or any combination thereof. By way of example only, the network 120 may include a cable network, a wired network, a fiber optic network, a telecommunications network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network ( WAN), Public Switched Telephone Network (PSTN), Bluetooth™ network, ZigBee network, Near Field Communication (NFC) network, or the like, or any combination thereof. In some embodiments, network 120 may include one or more network access points. For example, network 120 may include wired or wireless network access points such as base stations and/or Internet exchange points 120-1, 120-2, . . . through which one or more components of application scenario 100 may be accessed Points are connected to the network 120 to exchange data and/or information.

In some embodiments, the user terminal 130 may include a mobile device 130-1, a tablet computer 130-2, a laptop computer 130-3, a desktop computer 130-4, the like, or any combination thereof. In some embodiments, mobile device 140-1 may include a smart home device, wearable device, mobile device, virtual reality device, augmented reality device, etc., or any combination thereof. In some embodiments, smart home devices may include smart lighting devices, smart appliance control devices, smart monitoring devices, smart TVs, smart cameras, walkie-talkies, etc., or any combination thereof. In some embodiments, the wearable device may include bracelets, footwear, glasses, helmets, watches, clothing, backpacks, smart accessories, etc., or any combination thereof. In some embodiments, mobile devices may include mobile phones, personal digital assistants (PDAs), gaming devices, navigation devices, point-of-sale (POS) devices, laptops, desktops, etc., or any combination thereof. In some embodiments, a virtual reality device and/or an augmented virtual reality device may include a virtual reality headset, virtual reality glasses, virtual reality goggles, augmented reality helmet, augmented reality glasses, augmented reality goggles, etc., or any combination thereof. For example, virtual reality devices and/or augmented reality devices may include GoogleGlass ^™ , RiftCon ^™ , Fragments ^™ , GearVR ^™ , and the like.

In some embodiments, user terminal 130 may be a mobile terminal configured to acquire radio signals. User terminal 130 may send and/or receive information related to radio signal monitoring and identification to processing engine 112 or a processor installed in user terminal 130 via a user interface. For example, the user terminal 130 may transmit radio signal data captured by the user terminal 130 to the processing engine 112 or processor installed in the user terminal 120 via the user interface. The user interface may be in the form of an application implemented on the user terminal 130 for identifying satellites. A user interface implemented on the user terminal 130 may facilitate communication between the user and the processing engine 112 . For example, a user may input and/or import radio signal data to be identified via the user interface. The processing engine 112 may receive incoming signal data via a user interface. As another example, a user may input a request to identify a radio signal via a user interface implemented on the user terminal 130 .

In some embodiments, in response to the identification request, the user terminal 130 may directly process the radio signal data via the processor of the user terminal 130 based on signal acquisition means installed in the user terminal 130 as described elsewhere in this application. In some embodiments, in response to the identification request, the user terminal 130 may send the identification request to the processing engine 112 for determining the radio signal based on the signal acquisition device installed by the signal source 150 or elsewhere herein. In some embodiments, the user interface may facilitate presenting or displaying information and/or data (eg, signals) received from the processing engine 112 related to radio monitoring. For example, the information and/or data may include results indicating the content of radio monitoring, or indicating that radio monitoring is performed, or the like. In some embodiments, the information and/or data may be further configured to cause the user terminal 130 to display the results to the user.

Storage device 140 may store data and/or instructions. In some embodiments, storage device 140 may store data obtained from signal source 150 . The storage device 140 may store data and/or instructions that the processing engine 112 may execute or use to perform the example methods described in this application. In some embodiments, storage device 140 may include mass storage, removable storage, volatile read-write memory, read-only memory (ROM), the like, or any combination thereof. Exemplary mass storage may include magnetic disks, optical disks, solid state drives, and the like. Exemplary removable storage may include flash drives, floppy disks, optical disks, memory cards, compact disks, magnetic tapes, and the like. Exemplary volatile read-write memory may include random access memory (RAM). Exemplary RAMs may include dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), static random access memory (SRAM), thyristor random access memory (T-RAM), and zero capacitance Random Access Memory (Z-RAM), etc. Exemplary ROMs may include masked read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), optical disk only Read-only memory (CD-ROM) and digital versatile disk read-only memory, etc. In some embodiments, the storage device 140 may execute on a cloud platform. For example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distribution cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

In some embodiments, storage device 140 may be connected to network 120 to communicate with one or more components in application scenario 100 (eg, server 110 , user terminal 130 ). One or more components in application scenario 100 may access data or instructions stored in storage device 140 via network 120. In some embodiments, storage device 140 may be directly connected to or in communication with one or more components in application scenario 100 (eg, server 110, user terminal 130). In some embodiments, storage device 140 may be part of server 110 .

The signal source 150 is a signal terminal that sends out a radio signal. For example, the signal source can be a satellite, a signal generator, a base station, and the like. The radio signal generated by the signal source 150 can be collected based on the corresponding signal collection device.

It should be noted that the above description is intended to be illustrative, and not to limit the scope of the present application. Numerous alternatives, modifications and variations will be apparent to those skilled in the art. The features, structures, methods and other characteristics of the exemplary embodiments described herein may be combined in various ways to obtain additional and/or alternative exemplary embodiments. For example, the signal source 150 may be configured with a storage module, a processing module, a communication module, and the like. However, these changes and modifications do not depart from the scope of this application.

FIG. 2 is an exemplary structural diagram of a radio signal storage and playback apparatus according to some embodiments of the present specification.

As shown in FIG. 2 , the radio signal storage and playback apparatus 200 may include: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer.

The radio frequency front end is connected in communication with the AD data acquisition module, and the radio frequency front end is used to receive the signal to be analyzed through the antenna, and to perform at least one of amplification, filtering, and frequency mixing processing on the signal to be analyzed, so the to obtain the intermediate frequency signal.

The AD data acquisition module is connected in communication with the FPGA processor, and the AD data acquisition module is used for sampling the intermediate frequency signal, and uploading the obtained sampling data to the FPGA processor.

The FPGA processor is respectively connected to the DDR3 memory chip, the host computer, and the digital walkie-talkie, and the FPGA processor is used to perform digital frequency shifting, spectrum calculation, digital demodulation, storage and at least one of playback control, trigger signal identification and trigger processing, and uploading the data generated in the processing to the upper computer when receiving an instruction from the upper computer.

In some embodiments, the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is respectively connected with the storage and playback control module, the data The source selection module is in communication connection, and the storage and playback control module is respectively in communication connection with the data source selection module and the digital signal processing module; the data source selection module is in communication connection with the digital signal processing module.

The digital frequency shift control module can be used to perform digital frequency shift processing on the received signal; the data source selection module determines the data source read when the FPGA processor performs data playback processing; the digital signal processing module is used for reading The acquired data is processed, and the storage and playback control module is used to read the data and perform playback processing.

In some embodiments, the FPGA processor may further include an external connection module, and the external connection module may be used to implement at least one of the FPGA processor and the apparatus other than the processor in the radio signal storage and playback apparatus Communication with some devices. For example, the external connection module can include PCIe interface, jesd204b interface, etc., the FPGA processor can be connected with the DDR3 memory chip through the PCIe interface, and the AD data acquisition module and the FPGA processor can be communicated and connected through the jesd204b interface. Specifically, the AD data acquisition module can transmit the data to the FPGA processor through the jesd204b interface for subsequent processing. For another example, as a signal processing unit, the FPGA processor can receive sampling data from the AD data acquisition module through the jesd204b interface, and further perform operations such as digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal identification and triggering, etc. , and then the generated data can be selectively uploaded to the host computer through the PCIe interface.

In some embodiments, the digital signal processing module may include: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; wherein, inside the digital signal processing module, the digital filter and the digital demodulation unit are respectively , FFT unit communication connection, the FFT unit and the detection unit communication connection; in the entire FPGA processor, the digital filter is respectively connected to the data source selection module, the storage and playback control module communication connection. The digital demodulation unit can also communicate with the digital walkie-talkie. The detection unit can also be connected to the upper computer for communication. In some embodiments, the digital filter, the FFT unit, the detection unit, and the digital demodulation unit may be used to perform operations such as digital filtering, spectrum calculation, digital detection, and digital demodulation on the received data, respectively.

The DDR3 memory chip is used for classifying and storing data received by the FPGA processor based on an instruction issued by the FPGA processor, and serving as a data source when the FPGA processor plays back data. In some embodiments, the DDR3 memory chip is used as the main storage space, and the raw IQ data and the narrowband IQ data can be sorted and stored through the data source selection command. During data playback, the DDR3 memory chip takes out data to replace the sampling data source.

Using DDR3 as the storage unit, under the design of 1866Mhz sampling clock and 64bit data bus, it can support a maximum transmission speed of 14.9GMB/s, which is much higher than the throughput rate of IQ data, so sampling will not be caused by the bottleneck of the memory transmission rate. loss of signal. And if the storage space of DDR3 is expanded to 4GB, for 160MHz real-time IQ data (sampling rate 204.8MHz, data bit width is 32bit), it can store up to 5s; for narrowband IQ data, it can store up to several hours. Such a storage time can meet the routine monitoring of radio signals.

The digital walkie-talkie is connected in communication with the FPGA processor, and the digital walkie-talkie is used for data interaction with the FPGA processor to receive sound signals under various channels. For example, a digital walkie-talkie can perform data interaction with a digital demodulation module to receive sound signals under various channels.

The host computer is used for running human-computer interaction software, and obtains user instructions based on the running human-computer interaction software, and issues the user instructions to the FPGA processor, and displays the spectrum based on the data generated in the processing. information.

It should be noted that the parameters that need to be used in this manual can be set by the user according to the actual situation, such as input based on the host computer.

It should be noted that the above description of the system and its components is only for the convenience of description, and does not limit the description to the scope of the illustrated embodiments. It can be understood that for those skilled in the art, after understanding the principle of the system, it is possible to arbitrarily combine the various components, or form a subsystem to connect with other components without departing from the principle. For example, the RF front end and AD data acquisition module can be integrated in one component. For another example, each component may share one storage device, and each component may also have its own storage device. Such deformations are all within the protection scope of this specification.

In some embodiments, the radio signal storage and playback device supports a real-time sampling mode of operation and a record-playback mode of operation.

FIG. 3 is an exemplary flowchart of a real-time sampling working mode according to some embodiments of the present specification. In some embodiments, the process 300 may be performed by the radio signal storage and playback apparatus 200 . In some embodiments, process 300 may include the following steps:

Step 310, the AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor.

In some embodiments, the radio signal storage and playback apparatus may first collect the received signal through the antenna based on the radio frequency front end, and then perform processing such as amplifying, filtering, and frequency mixing on the collected signal based on the radio frequency front end, and then output an intermediate frequency signal.

In some embodiments, the RF front-end can transmit the obtained intermediate frequency signal to an AD data acquisition module designed with ADI high-speed AD chips, and the AD data acquisition module samples the received intermediate frequency signal, and then obtains the corresponding Digital signals such as IQ data.

In some embodiments, the AD data acquisition module may transmit its real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor.

Step 320, the data source selection module transmits the received real-time sampling data to the digital filter of the FPGA processor.

Step 330: The digital filter transmits the received real-time sampled data to the FFT unit and the digital demodulation unit, respectively, to perform narrowband filtering, digital demodulation, and spectrum calculation on the real-time sampled data. and digital detection operation.

Step 340: The digital demodulation unit and the detection unit respectively transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

As an example only, in the real-time sampling working mode, the real-time sampling data of the AD data acquisition module reaches the FPGA processor through the digital frequency shift control module and the data source selection module, and further performs narrowband filtering, digital demodulation, spectrum calculation and digital detection. and other operations, the processed data are respectively sent to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

It should be noted that the above description about the process 300 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 400 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

In some embodiments, in the recording and playback working mode, it can be further divided into original IQ data recording and playback and narrow-band IQ data recording and playback according to different data sources.

4 is an exemplary flow chart of recording and playback of raw IQ data in a recording and playback mode of operation according to some embodiments of the present specification; In some embodiments, process 400 may include the following steps:

Step 410, the AD data acquisition module transmits the real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor.

Step 420, the storage and playback control module performs at least one of abnormal signal identification, data packaging, and interface protocol conversion processing on the real-time sampled data, and transmits the processed data to a DDR3 memory chip for storage.

Step 430, when performing data playback, the storage and playback control module reads data from the DDR3 memory chip according to the required data amount set by the host computer, and performs data rate matching, so that the playback data matches the real-time sampling data. rate and sent to the digital signal processing module for processing.

Step 440: The digital signal processing module transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

As an example only, when the original IQ data is recorded and played back, the real-time sampling data of the AD data acquisition module enters the storage and playback control module through the digital frequency shift control module, and further operations such as abnormal signal identification, data packaging, and interface protocol conversion are performed. Then it is stored in the DDR3 memory chip. During playback, the storage and playback control module retrieves data from the DDR3 memory chip according to the required amount of data set by the host computer, and performs data rate matching, so that the playback data matches the rate of real-time sampling data and is poured into the subsequent digital signal processing module for processing. The finished data is then sent to the digital walkie-talkie for playback or the host computer for spectrum display.

It should be noted that the above description about the process 400 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 400 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

FIG. 5 is an exemplary flowchart of narrowband IQ data recording playback according to some embodiments of the present specification; in some embodiments, process 500 may be performed by radio signal storage and playback apparatus 200 . In some embodiments, process 500 may include the following steps:

Step 510, the AD data acquisition module transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor in turn.

Step 520, the digital filter outputs narrowband IQ data of different bandwidths after processing the received data.

Step 530, the digital filter sends the narrowband IQ data of each file to the storage and playback control module for at least one of abnormal signal identification, data packing, and interface protocol conversion processing.

Step 540, the storage and playback control module sends the processed data to the DDR3 memory chip for storage.

Step 550, when performing data playback, the storage and playback control module reads data from the DDR3 memory chip according to the required data amount set by the host computer, and performs data rate matching.

Step 560: Match the playback data to the real-time sampling rate of the narrowband IQ data and send it to a digital signal processing module for processing.

Step 570, the digital signal processing module transmits the processed data to the digital walkie-talkie respectively for playback or the host computer for real-time spectrum display.

Just as an example, when the narrowband IQ data is recorded and played back, the real-time sampled data of the AD data acquisition module passes through the digital frequency shift module and the digital filter bank (wherein, the decimation rates of the filter banks at each stage are different), and narrowbands with different bandwidths can be output. IQ data, the bandwidth range is 2kHz-160MHz, and can be divided into n grades according to user needs.

The narrowband IQ data of each file enters the storage and playback control module, and further operations such as abnormal signal identification, data packaging, and interface protocol conversion are stored in the DDR3 memory chip. During playback, the storage and playback control module retrieves data from the DDR3 memory chip according to the required amount of data set by the host computer, and performs data rate matching, so that the playback data matches the real-time sampling narrowband IQ data rate and is fed into subsequent digital demodulation. , spectrum calculation and detection module for processing, the processed data are respectively sent to the digital walkie-talkie for playback or the host computer for spectrum display.

It should be noted that the above description about the process 500 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 500 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

In some embodiments, the operating mode of the storage and playback control module includes a normal mode.

FIG. 6 is an exemplary flowchart in a conventional mode shown in accordance with some embodiments of the present specification; in some embodiments, the process 600 may be performed by the radio signal storage and playback apparatus 200 . In some embodiments, process 600 may include the following steps:

Step 610: Obtain storage parameters set by the user based on the host computer, where the storage parameters include a storage data source, a storage starting point, and a storage length.

Step 620, the FPGA processor stores the received sampling data in the DDR3 memory chip based on the storage parameter.

Step 630, after the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt mode.

Step 640: When performing data playback, determine the data source for playback based on the host computer.

Step 650 , based on the FPGA processor, control the playback data volume and playback speed to simulate real sample data.

Step 660: Process the playback data based on the FPGA processor, and transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

By way of example only, in the normal mode, the starting position and the amount of data for storage and playback can be freely selected. The host computer selects the storage data source, sets the storage starting point, storage length and other parameters. After the parameters take effect, data storage begins. After the storage length meets the set requirements, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt mode. Among them, the storage process can be executed multiple times, and each time the host computer is stored, there is a corresponding file record storage setting.

During playback, the host computer selects the data source for playback, and then clicks to start playback. The FPGA processor performs logic control of the playback data volume and playback speed to match the real sampling data source. And replace the real-time sampling data with the playback data, and perform subsequent signal analysis, digital demodulation and other operations, and the spectrum waveform generated by the playback data is also displayed on the host computer interface.

It should be noted that the above description about the process 600 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 600 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

FIG. 7 is an exemplary flowchart of a trigger mode according to some embodiments of the present specification; in some embodiments, the process 700 may be performed by the radio signal storage and playback apparatus 200 . In some embodiments, process 700 may include the following steps:

Step 710: Before storing, obtain trigger parameters and storage parameters based on the host computer, where the trigger parameters include the amount of data ahead of the trigger and the trigger threshold; and the storage parameters include the storage starting point and the storage length.

Step 720, when storing, the FPGA processor stores the received sampled data to the DDR3 memory chip based on the storage parameters, and judges abnormal signals and counts the stored data according to the trigger threshold during the storing process quantity.

Step 730: Based on the detection state of the abnormal signal, the FPGA processor performs different operations respectively.

In some embodiments, based on the detection state of the abnormal signal, the FPGA processor performs the following operations:

If the amount of stored data exceeds the amount of data ahead of the trigger, the abnormal signal is detected, then continue to store the data of the abnormal signal and the remaining data length, and record the storage location of the abnormal signal;

If the amount of stored data does not reach the amount of triggering advance data and the abnormal signal is detected, discard the abnormal signal and clear the stored data;

The detection of a new abnormal signal is restarted and the amount of stored data is counted, and the condition of the abnormal signal is not detected until the amount of stored data exceeds the amount of the triggering advance data.

Step 740, after the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt mode to upload the storage location of the abnormal signal at the same time. Wherein, the execution times of the above-mentioned stored procedure is not less than 1, and each time the stored procedure is executed, the upper computer has a corresponding file record storage setting.

Step 750: When performing data playback, the host computer first sends parameters such as the storage location and storage boundary of the abnormal signal, and determines the data source for playback.

Step 760 , based on the FPGA processor, control the playback data volume and playback speed to simulate real sample data.

Step 770: Process the playback data based on the FPGA processor, and transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

Just as an example, the trigger mode is mainly for the recording and playback of abnormal signals, and the playback operation is limited by the stored procedure and cannot be set arbitrarily. In the storage operation, first set the trigger data volume, trigger threshold, storage start, storage length and other parameters through the host computer. After the parameters take effect, data storage starts, and during the storage process, abnormal signals are judged according to the trigger threshold, and the amount of stored data is counted. According to the state of the abnormal signal, it can be divided into two cases:

a. The amount of stored data exceeds the set trigger advance data amount and then an abnormal signal is detected, then continue to store the data of the abnormal signal and the remaining data length, and record the storage location of the abnormal point;

b. An abnormal signal is detected before the amount of stored data reaches the set trigger advance data amount, then the abnormal signal is discarded, the existing data is cleared, and the new abnormal signal is detected again and the stored data is counted until it is satisfied case a.

When the length meets the set requirements, the FPGA processor generates a storage completion signal, notifies the host computer in an interrupt mode, and uploads the abnormal signal storage location at the same time. The storage process can be executed multiple times, and each time the host computer is stored, there is a corresponding file record storage setting.

In the playback operation, the host computer first sends the abnormal signal storage location, storage boundary and other parameters, and selects the data source for playback, and then clicks to start playback. The FPGA processor logic controls the playback data volume and playback speed to match the real sampling data source. The playback data replaces the real-time sampling data, and performs subsequent signal analysis, digital demodulation and other operations. The spectrum waveform generated by the playback data is also displayed on the host computer interface.

It should be noted that the above description about the process 700 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 700 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

In some embodiments of the present invention, rich storage and playback functions are designed by design. According to the working mode, it can be divided into regular mode and trigger mode. Among them, the trigger mode is aimed at the capture of abnormal signals, which can greatly improve the retrieval efficiency of abnormal signals; Users can analyze signals and observe spectral phenomena more clearly. At the same time, the storage data sources can also be classified, raw IQ data and narrowband IQ data can be stored separately, and the playback speed can be matched with the real-time sampling speed, so that there is no difference in the sampling rate between the playback data source and the real-time sampling data source.

The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is merely an example, and does not constitute a limitation of the present specification. Although not explicitly described herein, various modifications, improvements, and corrections to this specification may occur to those skilled in the art. Such modifications, improvements, and corrections are suggested in this specification, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of this specification.

Meanwhile, the present specification uses specific words to describe the embodiments of the present specification. Examples such as "one embodiment," "an embodiment," and/or "some embodiments" mean a certain feature, structure, or characteristic associated with at least one embodiment of this specification. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places in this specification are not necessarily referring to the same embodiment . Furthermore, certain features, structures or characteristics of the one or more embodiments of this specification may be combined as appropriate.

Furthermore, unless explicitly stated in the claims, the order of processing elements and sequences described in this specification, the use of alphanumerics, or the use of other names is not intended to limit the order of the processes and methods of this specification. While the foregoing disclosure discusses by way of various examples some embodiments of the invention that are presently believed to be useful, it is to be understood that such details are for purposes of illustration only and that the appended claims are not limited to the disclosed embodiments, but rather The requirements are intended to cover all modifications and equivalent combinations falling within the spirit and scope of the embodiments of this specification. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described systems on existing servers or mobile devices.

Similarly, it should be noted that, in order to simplify the expressions disclosed in this specification and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of this specification, various features may sometimes be combined into one embodiment, in the drawings or descriptions thereof. However, this method of disclosure does not imply that the subject matter of the description requires more features than are recited in the claims. Indeed, there are fewer features of an embodiment than all of the features of a single embodiment disclosed above.

Some examples use numbers to describe quantities of ingredients and attributes, it should be understood that such numbers used to describe the examples, in some examples, use the modifiers "about", "approximately" or "substantially" to retouch. Unless stated otherwise, "about", "approximately" or "substantially" means that a variation of ±20% is allowed for the stated number. Accordingly, in some embodiments, the numerical parameters set forth in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and use a general digit reservation method. Notwithstanding that the numerical fields and parameters used in some embodiments of this specification to confirm the breadth of their ranges are approximations, in specific embodiments such numerical values are set as precisely as practicable.

For each patent, patent application, patent application publication, and other material, such as article, book, specification, publication, document, etc., cited in this specification, the entire contents of which are hereby incorporated by reference into this specification are hereby incorporated by reference. Application history documents that are inconsistent with or conflict with the contents of this specification are excluded, as are documents (currently or hereafter appended to this specification) limiting the broadest scope of the claims of this specification. It should be noted that, if there is any inconsistency or conflict between the descriptions, definitions and/or use of terms in the accompanying materials of this specification and the contents of this specification, the descriptions, definitions and/or use of terms in this specification shall prevail .

Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations are also possible within the scope of this specification. Accordingly, by way of example and not limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to those expressly introduced and described in this specification.

Claims (10)

1. a radio signal storage and playback device, is characterized in that, comprises: radio frequency front-end, AD data acquisition module, FPGA processor, DDR3 memory chip, digital walkie-talkie, host computer; The radio frequency front end is connected in communication with the AD data acquisition module, and the radio frequency front end is used to receive the signal to be analyzed through the antenna, and to perform at least one of amplification, filtering, and frequency mixing processing on the signal to be analyzed, so the to obtain the intermediate frequency signal; The AD data acquisition module is connected in communication with the FPGA processor, and the AD data acquisition module is used for sampling the intermediate frequency signal, and uploading the obtained sampling data to the FPGA processor; The FPGA processor is respectively connected to the DDR3 memory chip, the host computer, and the digital walkie-talkie, and the FPGA processor is used to perform digital frequency shifting, spectrum calculation, digital demodulation, storage and at least one of playback control, trigger signal identification and trigger processing, and uploading the data generated in the processing to the host computer when receiving an instruction from the host computer; The DDR3 memory chip is used for classifying and storing the data received by the FPGA processor based on the instructions issued by the FPGA processor, and as a data source when the FPGA processor plays back data; The digital walkie-talkie is connected in communication with the FPGA processor, and the digital walkie-talkie is used for data interaction with the FPGA processor to receive sound signals under each channel; The host computer is used for running human-computer interaction software, and obtains user instructions based on the running human-computer interaction software, and issues the user instructions to the FPGA processor, and displays the spectrum based on the data generated in the processing. information. 2. The radio signal storage and playback device according to claim 1, wherein the FPGA processor comprises a digital frequency shift control module, a data source selection module, a digital signal processing module, a storage and playback control module; the The digital frequency shift control module is respectively connected in communication with the storage and playback control module and the data source selection module, and the storage and playback control module is respectively connected in communication with the data source selection module and the digital signal processing module; The module is connected in communication with the digital signal processing module. 3. The radio signal storage and playback device according to claim 2, wherein the digital signal processing module comprises: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; The digital filter is respectively connected in communication with the digital demodulation unit and the FFT unit, and the FFT unit is connected in communication with the detection unit. 4 . The radio signal storage and playback device according to claim 3 , wherein the sampling working modes of the radio signal storage and playback device include a real-time sampling working mode and a recording and playback working mode. 5 . 5. The radio signal storage and playback device according to claim 4, wherein the real-time sampling working mode is realized based on the following methods: The AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor; The data source selection module transfers the received real-time sampling data to the digital filter of the FPGA processor; The digital filter transmits the received real-time sampled data to the FFT unit and the digital demodulation unit respectively, so as to perform narrowband filtering, digital demodulation, spectrum calculation and digital detection on the real-time sampled data respectively operate; The digital demodulation unit and the detection unit respectively transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display. 6 . The radio signal storage and playback device according to claim 4 , wherein the recording and playback working modes are divided into original IQ data recording and playback and narrow-band IQ data recording and playback based on different data sources. 7 . 7. The radio signal storage and playback device according to claim 6, wherein the recording and playback of the original IQ data is realized in the following manner: The AD data acquisition module transmits real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor; The storage and playback control module performs at least one of abnormal signal identification, data packaging, and interface protocol conversion processing on the real-time sampled data, and transmits the processed data to the DDR3 memory chip for storage; When performing data playback, the storage and playback control module reads data from the DDR3 memory chip according to the required amount of data set by the host computer, and performs data rate matching, so that the playback data matches the real-time sampling data The rate is sent to the digital signal processing module for processing; The digital signal processing module transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display. 8. The radio signal storage and playback device according to claim 6, wherein the recording and playback of the narrowband IQ data is realized in the following manner: The AD data acquisition module sequentially transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor; The digital filter includes several filtering units and each of the filtering units has a different decimation rate; The digital filter outputs narrowband IQ data of different bandwidths after processing the received data, and the bandwidth range of the narrowband IQ data is 2kHz-160MHz; The digital filter then sends the narrowband IQ data of each file to the storage and playback control module for at least one of abnormal signal identification, data packaging, and interface protocol conversion processing; The storage and playback control module sends the processed data to the DDR3 memory chip for storage; When performing data playback, the storage and playback control module reads data from the DDR3 memory chip according to the required data amount set by the host computer, and performs data rate matching, Matching the playback data to the rate of the narrowband IQ data sampled in real time and sending it to a digital signal processing module for processing; The digital signal processing module transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display. 9. The radio signal storage and playback device according to any one of claims 1-8, wherein the operation mode of the storage and playback control module comprises a normal mode; In the normal mode, the radio signal storage and playback device is configured to perform the following operations: Obtaining the storage parameters set by the user based on the host computer, the storage parameters include a storage data source, a storage starting point, and a storage length; The FPGA processor stores the received sampling data to the DDR3 memory chip based on the storage parameter; After the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt mode; Wherein, the execution times of the above-mentioned stored procedure is not less than 1, and each time the stored procedure is executed, the host computer has a corresponding file record storage setting; When performing data playback, determine the data source for playback based on the host computer; Controlling the amount of playback data and playback speed based on the FPGA processor to simulate real sampling data; The playback data is processed based on the FPGA processor, and the processed data is respectively transmitted to the digital walkie-talkie for playback or the host computer for real-time spectrum display. 10. The radio signal storage and playback device according to any one of claims 1-8, wherein the operation mode of the storage and playback control module comprises a trigger mode; In the trigger mode, the radio signal storage and playback device is configured to: Before storage, trigger parameters and storage parameters are obtained based on the host computer, where the trigger parameters include triggering advance data amount and trigger threshold; the storage parameters include storage starting point and storage length; During storage, the FPGA processor stores the received sampling data to the DDR3 memory chip based on the storage parameters, and judges abnormal signals and counts the amount of stored data according to the trigger threshold during the storage process; Based on the detection state of the abnormal signal, the FPGA processor performs the following operations: If the amount of stored data exceeds the amount of data ahead of the trigger, the abnormal signal is detected, then continue to store the data of the abnormal signal and the remaining data length, and record the storage location of the abnormal signal; If the amount of stored data does not reach the amount of triggering advance data and the abnormal signal is detected, discard the abnormal signal and clear the stored data; Restart to detect new abnormal signals and count the amount of stored data, until the condition of the abnormal signal is detected after the amount of stored data exceeds the amount of trigger advance data; After the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupted manner to upload the storage location of the abnormal signal at the same time; Wherein, the execution times of the above-mentioned stored procedure is not less than 1, and each time the stored procedure is executed, the host computer has a corresponding file record storage setting; When performing data playback, the host computer first sends parameters such as the storage location and storage boundary of the abnormal signal, and determines the data source for playback; The amount of playback data and playback speed are controlled based on the FPGA processor to simulate real sampled data; the playback data is processed based on the FPGA processor, and the processed data are respectively transmitted to the digital walkie-talkie for playback or the The host computer performs real-time spectrum display.

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