CN114899169A - Multi-chip flat-laying packaging structure - Google Patents

Abstract

The invention provides a multi-chip and multi-chip flat package structure which comprises a lead frame and a plastic package body, wherein the plastic package body is formed in a carrying area of the lead frame, a semiconductor capacitor and at least one functional chip are packaged in the plastic package body, the semiconductor capacitor and the at least one functional chip are positioned on the carrying area, and the functional chip and the semiconductor capacitor are laid on the carrying area side by side and can be electrically connected with pins. In the invention, compared with the chip capacitor in the related art, the semiconductor capacitor has small volume, so that the semiconductor capacitor can be tiled and packaged together with the functional chip in the chip carrying area. In this case, the semiconductor capacitor is closer to the functional chip, which can greatly reduce the electric signal delay generated by packaging, reduce the parasitic inductance on the multi-chip tiled packaging structure, and further improve the EMC resistance of the functional chip due to the reduction of the parasitic inductance and the delay.

Description

Multi-chip tiled package structure

technical field

The invention relates to the technical field of magnetic sensors, in particular to a multi-chip tiled packaging structure.

Background technique

Electromagnetic Compatibility (EMC, Electromagnetic Compatibility) refers to the ability of a device or system to operate compliantly in its electromagnetic environment without causing intolerable electromagnetic disturbance to any device in its environment.

In the related technical field, in order to solve the EMC resistance, the industry adopts two plastic packages as shown in FIG. 1 on the lead frame. One plastic package is formed in the carrier area of the lead frame and encapsulated with a functional chip, and the other plastic package is formed on the lead frame pins and packaged with chip capacitors.

In this way, when electromagnetic interference is introduced from the power supply terminal and the functional chip itself, the introduction of the chip capacitor between the power supply and the ground can play the role of electrical filtering, thereby improving the EMC resistance of the device corresponding to the package structure.

SUMMARY OF THE INVENTION

In view of the problems in the prior art, the purpose of the present invention is to provide a multi-chip tiled packaging structure, which can reduce the signal delay of functional chips.

An embodiment of the present invention provides a multi-chip tiled packaging structure, which includes:

a lead frame having a carrier area and pins extending from the carrier area;

The plastic package formed in the carrier area encapsulates the semiconductor capacitor and at least one functional chip on the carrier area, wherein the functional chip and the semiconductor capacitor are distributed in a tiled manner on the carrier area.

Optionally, the leads of the semiconductor capacitor and the leads of the functional chip are both packaged in a plastic package and electrically connected to corresponding pins.

Optionally, a gap is formed between the functional chip and the semiconductor capacitor, and the lead of at least one of the functional chip and the semiconductor capacitor is located in the gap.

Optionally, wire bonding is used for electrical connection between one electrode plate of the semiconductor capacitor and the power supply pin, and between the other electrode plate of the semiconductor capacitor and the ground pin.

Optionally, between the power access terminal of the function chip and the power supply pin, the ground terminal of the function chip and the ground pin are electrically connected by wire bonding.

Optionally, the projections of the functional chip and the semiconductor capacitor on the slide area do not overlap.

Optionally, the thickness of the lead frame ranges from 0.1 to 1 mm.

Optionally, the thickness of the plastic package is between 0.5mm and 3mm.

Optionally, the lead frame is made of metal.

An embodiment of the present disclosure further provides a magnetic sensor, which is formed in the multi-chip tiled packaging structure of any of the above embodiments, and the functional chip is a magnetic sensor chip.

The multi-chip tiled packaging structure provided by the present invention has the following advantages:

The multi-chip tiled packaging structure includes a lead frame and a plastic package, wherein the plastic package is formed in the carrier area of the lead frame, and a semiconductor capacitor and at least one functional chip on the carrier area are packaged in the plastic package, wherein the functional chip and the semiconductor capacitor are laid side by side. on the carrier area and can be electrically connected to the pins.

In the embodiments of the present disclosure, compared with the chip capacitors in the related art, the semiconductor capacitors are small in size, so that they can be tiled and packaged in the carrier area together with the functional chips. In this case, the semiconductor capacitor is closer to the functional chip, which can greatly reduce the electrical signal delay caused by packaging, and reduce the parasitic inductance on the multi-chip tiled packaging structure. Due to the reduction of parasitic inductance and delay, it can further improve The EMC resistance of functional chips is improved.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings.

1 is a front cross-sectional view of a multi-chip tiled packaging structure of the prior art;

2 is a front cross-sectional view of a multi-chip tiled packaging structure provided by an embodiment of the present disclosure;

3 is a side cross-sectional view of a multi-chip tiled packaging structure provided by an embodiment of the present disclosure;

4 is a package circuit diagram of a multi-chip tiled package structure according to an embodiment of the present invention.

Detailed ways

The embodiments of the present application are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied to the system through other different specific embodiments, and various details in the present application can also be modified or changed according to different viewpoints and applied systems without departing from the spirit of the present application. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other under the condition of no conflict.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art to which the present application pertains can easily implement. The present application can be embodied in many different forms, and is not limited to the embodiments described herein.

In the representations of this application, references to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., are intended to be combined with the specific features represented by the embodiment or example. , structure, material or feature is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials or characteristics shown may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples presented in this application, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the expression of this application, "plurality" means two or more, unless expressly and specifically defined otherwise.

In order to clearly describe the present application, components irrelevant to the description are omitted, and the same or similar components are assigned the same reference numerals throughout the specification.

Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when it is said that a certain device "includes" a certain constituent element, unless there is no particular description to the contrary, it does not exclude other constituent elements, but means that other constituent elements may also be included.

When a device is said to be "on" another device, this can be directly on the other device, but it can also be accompanied by other devices in between. When a device is said to be "directly on" another device in contrast, there are no other devices in between.

Although in some instances the terms first, second, etc. are used herein to refer to various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first interface and the second interface, etc. are represented. Also, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context dictates otherwise. It should be further understood that the terms "comprising" and "comprising" indicate the presence of features, steps, operations, elements, components, items, kinds, and/or groups, but do not exclude one or more other features, steps, operations, elements, The existence, appearance or addition of components, items, categories, and/or groups. The terms "or" and "and/or" as used herein are to be construed to be inclusive or to mean any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C" . Exceptions to this definition arise only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the application. The singular form used here also includes the plural form, as long as the sentence does not clearly express the opposite meaning. The meaning of "comprising" as used in the specification is to embody particular characteristics, regions, integers, steps, operations, elements and/or components, but not to exclude other characteristics, regions, integers, steps, operations, elements and/or components exist or append.

Although not defined differently, including technical and scientific terms used herein, all terms have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms defined in commonly used dictionaries are additionally interpreted to have meanings consistent with the content of the relevant technical literature and current tips, and as long as they are not defined, they should not be unduly interpreted as ideal or very formulaic meanings.

The analysis of related technologies shows that the corresponding packaging structure adopts a separate plastic body, although it can enhance the EMC resistance, but due to the long distance between the chip capacitor and the functional chip, the delay of the electrical signal is prolonged, and the parasitic inductance is large, which affects the performance of the functional chip. performance.

Moreover, the separation plastic body is adopted, the product integration degree is low, and the product volume is large. In addition, the double-molded body is complicated to process, the moisture-proof level is poor, and the product application space is complicated, which limits the application scenarios of the end product. Furthermore, the use of a double-molded body is equivalent to one more fault location, and the reliability of the product is reduced.

Therefore, the technical problem to be solved by the embodiments of the present disclosure is how to reduce or avoid electrical signal delay without reducing the EMC resistance, so as to reduce the package volume and improve the product integration.

In order to solve the technical problems of the related art, an embodiment of the present disclosure provides a new multi-chip tiled package structure, the multi-chip tiled package structure includes a lead frame and a plastic package, wherein the plastic package is formed in the carrier area of the lead frame, The plastic package is encapsulated with a semiconductor capacitor and at least one functional chip on the carrier area, wherein the functional chip and the semiconductor capacitor are laid side by side on the carrier area and can be electrically connected to the pins.

In the embodiments of the present disclosure, compared with the chip capacitors in the related art, the semiconductor capacitors are small in size, so that they can be tiled and packaged in the carrier area together with the functional chips. In this case, the semiconductor capacitor is closer to the functional chip, which can greatly reduce the electrical signal delay caused by packaging, and reduce the parasitic inductance on the multi-chip tiled packaging structure. Due to the reduction of parasitic inductance and delay, it can further improve The EMC resistance of functional chips is improved.

Moreover, the integrated package reduces the packaging difficulty, reliability and moisture resistance through the multi-chip tiled packaging structure.

Furthermore, the package volume is reduced, which is convenient for the industry to use.

Therefore, the embodiments of the present disclosure have high feasibility in solving the above technical problems by using semiconductor capacitors.

2 is a front cross-sectional view of a multi-chip tiled packaging structure provided by an embodiment of the present disclosure, and FIG. 3 is a side cross-sectional view of the multi-chip tiled packaging structure provided by an embodiment of the present disclosure. Referring to FIG. 2 and FIG. The package structure includes:

The lead frame 10 has a carrier area 11 and pins 12 extending from the carrier area 11;

The plastic package 20 formed in the carrier area 11 is encapsulated in the plastic package 20 with a semiconductor capacitor 21 and at least one functional chip 22 located on the carrier area 11 , wherein the functional chip 22 and the semiconductor capacitor 21 are distributed in a tiled manner on the carrier area 11 .

With such a solution, in an application example, referring to FIG. 4 , the semiconductor capacitor 21 and the functional chip 22 are connected in parallel. The semiconductor capacitor 21 plays the role of electrical filtering. When electromagnetic interference is introduced from the power supply terminal VCC (which is regarded as external EMC) and the functional chip (Die) (which is regarded as internal EMC) 22 itself, the electromagnetic interference can pass through the semiconductor. The capacitor 21 is electrically filtered to the ground GND without affecting the operation of Die.

In the embodiment of the present disclosure, the semiconductor capacitor 21 is a silicon-based chip capacitor.

The semiconductor capacitor structure is based on a metal-oxide-metal (MOM) structure that can be fabricated in standard CMOS processes without additional cost. A capacitor constructed with an oxide layer as a dielectric material. However, as is widely known by those who are familiar with semiconductor manufacturing technology, the core concept of the present invention is not necessarily realized by the materials described in the embodiments, and other common or innovative conductive materials or dielectric materials can also be used to realize the present invention. Invention of the semiconductor capacitor structure.

Compared with the solution in the prior art in which the chip capacitor uses metal as the electrode plate, the volume of the semiconductor capacitor 21 is greatly reduced, which can improve the feasibility of the integrated plastic packaging solution of the embodiment of the present disclosure.

In the embodiment of the present disclosure, the projections of the functional chip 22 and the semiconductor capacitor 21 on the carrier area 11 do not overlap, so that the functional chip 22 and the semiconductor capacitor 21 are tiled and distributed on the carrier area 11 and can be mounted on the carrier area 11 .

Only one functional chip 22 is shown in FIG. 2 and FIG. 3 , which is only an example. In other embodiments, the number of functional chips may also be other, which is not specifically limited herein.

In the packaging process, the semiconductor capacitor 21 and the functional chip 22 are firstly packaged in the carrier area 11 side by side, and then the carrier area 11 is plastic-encapsulated to obtain the plastic package 20 .

Among them, the functional chip 22 and the semiconductor capacitor 21 are on the carrier area 11 and can be bonded to the carrier area 11 by a patch glue. The molding compound 20 can be made of a molding compound resin for packaging the functional chip 22 and the semiconductor capacitor 21, and a large amount of filler is filled in the molding compound resin.

In the corresponding process, the functional chip 22 and the semiconductor capacitor 21 are each wrapped with insulating material, or the material of the plastic package 20 also has insulating properties and will not interfere with each other.

The embodiment of the present disclosure provides a chip-capacitor tile packaging design scheme based on a lead frame. For the first time in the industry, the chip+thin semiconductor capacitor is paved in the carrier area and packaged into a single plastic package to realize a new multi-chip tile package. The structure and the compact shape of the one-piece molded body.

In an embodiment of the present disclosure, the leads of the semiconductor capacitor 21 and the leads of the functional chip 22 are both encapsulated in the plastic package 20 and electrically connected to the corresponding pins. At this time, the plastic package 20 has a protective effect on the leads.

In one embodiment, one electrode plate of the semiconductor capacitor 21 and the power supply pin and the other electrode plate of the semiconductor capacitor 21 and the ground pin are electrically connected by wire bonding. FIG. 2 and FIG. 3 show two pins 12, which can be used to connect the power terminal and the ground respectively, one of which is a power pin and the other is a ground pin. For this embodiment, reference may be made to the circuit diagram shown in FIG. 4 . Through this electrical connection, the semiconductor capacitor 21 can play an electrical filtering role.

In other optional application scenarios, the lead frame can have other functional pins or other numbers of pins, and the lead connections can be adjusted as required, which is not limited here.

In an embodiment of the present disclosure, between the power access terminal of the function chip 22 and the power supply pin, the ground terminal of the function chip 22 and the ground pin are electrically connected by wire bonding.

In this way, the leads of the semiconductor capacitor 21 and the leads of the functional chip 22 may or may not be in contact, which is not limited herein.

In the packaging process, a wire bonding process is used to form the leads of the semiconductor capacitor 21 and the leads of the functional chip 22 . Wire bonding is a method of using thin metal wires to closely bond the metal wires to the pads corresponding to the carrier area 11 by using heat, pressure and ultrasonic energy.

In one embodiment of the present disclosure, a gap is formed between the functional chip 22 and the semiconductor capacitor 21 , and the lead of at least one of the functional chip 22 and the semiconductor capacitor 21 is located in the gap and connected to the pin 12 .

Among them, the gap will provide corresponding space for routing the leads. The leads between the functional chip 22 and the semiconductor capacitor 21 and the pins 12 can be copper wires or gold wires.

In the embodiment of the present disclosure, the thickness h ₁ of the lead frame 10 ranges from 0.1 to 1 mm. Wherein, if the thickness of the lead frame 10 is less than 0.1, the carrier area 11 will not be able to effectively support the plastic package 20; and if the thickness of the lead frame 10 is higher than 1 mm, a cost problem will arise.

In an embodiment of the present disclosure, the thickness h ₂ of the plastic sealing body 20 is between 0.5 mm and 3 mm. By setting the thickness of the plastic package 20 to be not less than 0.5 mm, a stable package can be formed for the semiconductor capacitor 21 and the functional chip 22, and the function of moisture-proof isolation can be achieved. By setting the thickness of the plastic package 20 to be no greater than 3 mm, a suitable product integration degree can be provided.

In an embodiment of the present disclosure, the lead frame is made of metal.

An embodiment of the present disclosure further provides a magnetic sensor, which is formed in the above-mentioned multi-chip tiled packaging structure, such that the functional chip is a magnetic sensor chip.

A magnetic sensor is a device that converts the magnetic properties of sensitive components caused by external factors such as magnetic field, current, stress and strain, temperature, and light into electrical signals, and detects the corresponding physical quantities in this way. Magnetic sensors are widely used in modern industry and electronic products to measure physical parameters such as current, position, and direction by sensing the strength of magnetic fields. There are also many different types of sensors used to measure magnetic fields and other parameters.

For example, magnetic sensors are widely used in industrial control and automotive electronics to provide a new generation of automotive-grade, low-profile, one-piece packages with enhanced EMC immunity.

The basic unit of the magnetic sensor may have a multi-chip tiled package structure as shown in FIG. 2 and FIG. 3 . On this basis, other components can also be added to form the final product of the magnetic sensor.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A multi-chip tiled package structure, comprising:

a lead frame having a carrier region and pins extending from the carrier region;

the chip-on-chip packaging structure comprises a plastic packaging body formed in a chip-carrying area, wherein a semiconductor capacitor and at least one functional chip are packaged in the plastic packaging body, the semiconductor capacitor and the at least one functional chip are positioned on the chip-carrying area, and the functional chips and the semiconductor capacitor are distributed on the chip-carrying area in a tiled mode.

2. The multi-chip tiling package structure of claim 1, wherein the leads of the semiconductor capacitors and the leads of the functional chips are packaged in the plastic package and electrically connected to the corresponding leads.

3. The multi-chip tiling package structure of claim 2, wherein a gap is formed between the functional chip and the semiconductor capacitor, and leads of at least one of the functional chip and the semiconductor capacitor are located within the gap.

4. The multi-chip tiled package structure according to claim 2, wherein the electrical connection between one plate of the semiconductor capacitor and a power pin and the electrical connection between the other plate of the semiconductor capacitor and a ground pin are made by wire bonding.

5. The multi-chip tiling package structure of claim 2, wherein the power access terminals of the functional chips and the power pins, and the ground terminals of the functional chips and the ground pins are electrically connected by wire bonding.

6. The multi-chip tiled package structure according to claim 1, wherein the projections of the functional chips and the semiconductor capacitors on the carrier area do not overlap.

7. The multi-chip tiled package structure according to claim 1, wherein the thickness of the lead frame ranges from 0.1 to 1 mm.

8. The multi-chip tile package structure of claim 1, wherein the molding compound has a thickness between 0.5mm and 3 mm.

9. The multi-chip tile package structure of claim 1, wherein the lead frame is a metal.

10. A magnetic sensor formed in the multi-chip tiling package structure of any one of claims 1-9, wherein the functional chips are magnetic sensor chips.

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