CN114843297A - How to make a CIS device - Google Patents

Abstract

The present application discloses a method for fabricating a CIS device, comprising: forming a first nitride layer on a back-end structure, forming a CIS device under the back-end structure, and the back-end structure comprising a dielectric layer and a dielectric layer formed in the dielectric layer The metal layer is formed; ultraviolet baking treatment is performed; a first oxide layer is formed on the first nitride layer; and a second nitride layer is formed on the first oxide layer. In the manufacturing process of the CIS device of the present application, a first nitride layer is first formed on the back-end structure, and then ultraviolet baking is performed, and then a first oxide layer is formed on the first nitride layer, and a first oxide layer is formed on the first oxide layer. The second nitride layer is formed, because the first oxide layer can relieve the stress of the nitride layer as a buffer layer, thereby improving the bubble defect caused by only forming a thick nitride layer to reduce the warpage of the wafer in the related art problems, improve the reliability and yield of the device.

Description

How to make a CIS device

technical field

The present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a CIS device.

Background technique

Complementary metal oxide semiconductor image sensor (complementary metal oxide semiconductor contact image sensor, CIS) is an image sensor made of CMOS devices. Due to its advantages of high integration, low power supply voltage and low technical threshold, it is widely used in photography, videography, security systems, smart portable phones, and medical electronics.

In the related art, in the manufacturing process of the CIS device, after the backend of line (BEOL) structure is formed, an ultraviolet (ultraviolet, UV) baking (bake) step may be added to improve the image lag of the CIS device ( image lag) and signal noise. However, UV baking will increase the final warpage of the wafer, which will affect the subsequent process. In view of this, the warpage of the wafer can be reduced by increasing the thickness of the nitride layer in the back-end structure. However, an increase in the thickness of the nitrided layer can cause excessive stress to form bubble defects on its surface, thereby reducing device reliability and yield.

SUMMARY OF THE INVENTION

The application provides a manufacturing method of CIS, which can solve the problem of bubble defects caused by the larger thickness of the nitrided layer in the manufacturing method of the CIS provided in the related art including the ultraviolet baking step, and the method includes:

A first nitride layer is formed on the back-end structure, a CIS device is formed below the back-end structure, and the back-end structure includes a dielectric layer and a metal layer formed in the dielectric layer;

Carry out UV baking treatment;

forming a first oxide layer on the first nitride layer;

A second nitride layer is formed on the first oxide layer.

In some embodiments, the thickness of the first nitride layer is 80 angstroms to 200 angstroms.

In some embodiments, the thickness of the first oxide layer is 200 angstroms to 3000 angstroms.

In some embodiments, the forming a first oxide layer on the first nitride layer includes:

The first oxide layer is formed on the first nitride layer by a TEOS deposition process.

In some embodiments, the thickness of the second nitride layer is 1000 angstroms to 8000 angstroms.

In some embodiments, the temperature of the ultraviolet baking treatment is 180 degrees Celsius to 500 degrees Celsius.

In some embodiments, the duration of the UV bake treatment is 100 seconds to 1000 seconds.

In some embodiments, after the ultraviolet baking treatment is performed, and before the oxide layer is formed on the first nitride layer, the method further includes:

Do WAT.

The technical solution of the present application includes at least the following advantages:

In the manufacturing process of the CIS device, a first nitride layer is formed on the back-end structure, and then ultraviolet baking is performed, and then a first oxide layer is formed on the first nitride layer, and a first oxide layer is formed on the first oxide layer. The dinitride layer, because the first oxide layer acts as a buffer layer can relieve the stress of the nitride layer, thereby improving the problem of bubble defects caused by only forming a thick nitride layer to reduce the warpage of the wafer in the related art , improving the reliability and yield of the device.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings required in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a flowchart of a method for making a CIS provided by an exemplary embodiment of the present application;

2 to 6 are schematic diagrams of a manufacturing process of a CIS provided by an exemplary embodiment of the present application.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict with each other.

Referring to FIG. 1, it shows a flowchart of a method for manufacturing a CIS provided by an exemplary embodiment of the present application. As shown in FIG. 1, the method includes:

In step S1, a first nitride layer is formed on the back-end structure, a CIS device is formed under the back-end structure, and the back-end structure includes a dielectric layer and a metal layer formed in the dielectric layer.

Referring to FIG. 2 , a schematic cross-sectional view of forming a first nitride layer on the back-end structure is shown. The back-end structure includes a dielectric layer and a metal layer formed in the dielectric layer, and the back-end structure is formed above the CIS device (not shown in FIG. 2 ). FIG. 2 takes a back-end structure as an example to illustrate.

Exemplarily, as shown in FIG. 2 , the back-end structure includes a first dielectric layer 211 and a second dielectric layer 212 , and nitride doped silicon carbide is formed between the first dielectric layer 211 and the second dielectric layer 212 . silicon carbide, NDC) layer 220 . The first dielectric layer 211 and the second dielectric layer 212 include a low dielectric constant material (a material whose dielectric constant k is less than 4, for example, it may be a thin film composed of silicon oxide (such as silicon dioxide (SiO ₂ ))) A metal connection 2312 is formed in the first dielectric layer 211, a contact hole (via) 2321 and a metal connection 2322 are formed in the second dielectric layer 212, and the bottom end of the contact hole 2321 is connected with the top of the metal connection 2312, The top end of the contact hole 2321 is connected to the bottom end of the metal wire 2322 .

至200埃。The silicon nitride (eg, silicon nitride (SiN)) can be formed by depositing a silicon nitride (eg, silicon nitride (SiN)) by a chemical vapor deposition (CVD) process (eg, a plasma enhanced chemical vapor deposition (PE CVD) process). A nitride layer 240 . The thickness of the first nitride layer 240 is 80 angstroms

to 200 angstroms.

In step S2, ultraviolet baking treatment is performed.

Referring to FIG. 3, a schematic diagram of UV bake treatment is shown. Image lag and signal noise of CIS devices can be improved by UV bake. In some embodiments, the temperature of the UV baking treatment is 180 degrees Celsius (° C.) to 500 degrees Celsius, and the time of the UV baking treatment is 100 seconds (s) to 1000 seconds.

Referring to Figure 4, a schematic diagram of conducting a wafer acceptable test (WAT) is shown. As shown in FIG. 4 , in some embodiments, after step S2 and before step S3, the method further includes: performing WAT. WAT can reflect the process fluctuation of the wafer in the tape-out stage, and can detect the abnormality of the production line.

Step S3, forming a first oxide layer on the first nitride layer.

Referring to FIG. 5, a schematic cross-sectional view of forming a first oxide layer on the first nitride layer is shown. Exemplarily, as shown in FIG. 5 , the first oxide layer 250 may be formed by depositing silicon oxide on the first nitride layer 240 through a tetraethoxysilane (TEOS) process. The thickness of the first oxide layer 250 is 200 angstroms to 3000 angstroms.

Step S4, forming a second nitride layer on the first oxide layer.

Exemplarily, as shown in FIG. 6 , the second nitride layer 260 may be formed by depositing silicon nitride on the first oxide layer 250 by a chemical vapor deposition CVD process (eg, PE CVD process). The thickness of the second nitride layer 260 is 1000 angstroms to 8000 angstroms.

To sum up, in the embodiment of the present application, in the process of fabricating the CIS device, the first nitride layer is first formed on the back-end structure, and then the ultraviolet baking is performed, and then the first nitride layer is formed on the first nitride layer. An oxide layer, a second nitride layer is formed on the first oxide layer, since the first oxide layer acts as a buffer layer to relieve the stress of the nitride layer, thus improving the reduction of the wafer in the related art by only forming a thick nitride layer The problem of bubble defects caused by high warpage improves the reliability and yield of the device.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (8)

1. A method for manufacturing a CIS device is characterized by comprising the following steps:

forming a first nitride layer on a rear-end structure, wherein a CIS device is formed below the rear-end structure, and the rear-end structure comprises a dielectric layer and a metal layer formed in the dielectric layer;

carrying out ultraviolet baking treatment;

forming a first oxide layer on the first nitride layer;

and forming a second nitride layer on the first oxide layer.

2. The method as claimed in claim 1, wherein the first nitride layer has a thickness of 80-200 angstroms.

3. The method of claim 2, wherein the first oxide layer has a thickness of 200 to 3000 angstroms.

4. The method of claim 3, wherein the forming a first oxide layer on the first nitride layer comprises:

forming the first oxide layer on the first nitride layer by a TEOS deposition process.

5. The method of claim 4, wherein the second nitride layer has a thickness of 1000 to 8000 angstroms.

6. The method of claim 5, wherein the temperature of the UV baking process is 180 to 500 degrees Celsius.

7. The method of claim 6, wherein the time of the UV baking treatment is 100 to 1000 seconds.

8. The method of manufacturing according to any one of claims 1 to 7, further comprising, after the performing the ultraviolet baking process and before forming the oxide layer on the first nitride layer:

WAT is performed.

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