CN114823349A - A kind of metal oxide thin film transistor based on plasma treatment of active layer and preparation method thereof - Google Patents

Abstract

The invention discloses a metal oxide thin film transistor based on a plasma processing active layer and a preparation method thereof, belonging to the technical field of transistors. The preparation method comprises the following steps: depositing and etching a semiconductor active layer on a substrate by using metal oxide; depositing a gate insulating layer on the active semiconductor layer; injecting a low-concentration plasma beam into the semiconductor active layer through the gate insulating layer; depositing and etching on the gate insulating layer to form a gate electrode; injecting low-concentration plasma beams into the semiconductor active layer through the gate insulating layer so as to manufacture a channel region, a source region and a drain region; depositing again to form a passivation insulating layer to protect the whole device; opening a lead hole to expose the gate electrode, the source region and the drain region; and depositing metal on each lead hole and etching to form a metal electrode. The method has simple process and low cost, can simultaneously realize depletion type and enhancement type transistors, and the prepared transistor has excellent electrical properties such as high mobility, high stability and the like.

Description

A kind of metal oxide thin film transistor based on plasma treatment active layer and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor transistors, in particular to a metal oxide thin film transistor based on plasma treatment of an active layer and a preparation method thereof.

Background technique

In recent years, with the explosive development of Internet of Things technology, biosensing, flexible electronics and the rapid change of flat panel display technology, metal oxide transparent thin film transistors have rapidly become a The darling of science and industry. In the application of integrated circuits, metal oxide transparent thin film transistors can be prepared on various substrates by low-temperature deposition, which can realize large-area, highly transparent, and highly flexible chip circuits, while traditional silicon-based circuits are limited by the preparation Process and transfer process, it is difficult to show their talents in biosensing and flexible electronics. In flat panel displays, since the mobility of traditional amorphous silicon thin film transistors is lower than 1cm ² /Vs, and the transistors in high-definition pixels are small in size, the turn-on current is small, the charge and discharge delay time is long, and the response speed of the display screen is seriously affected. At the same time, the high operating voltage, high power consumption and serious heat generation of amorphous silicon thin film transistors are very unfavorable for mobile device applications. The currently used small-size high-resolution displays are mainly driven by low temperature polysilicon thin film transistors. Although low temperature polysilicon thin film transistors have a high mobility (~100 cm ² /Vs), they require laser scanning annealing, and the process manufacturing cost is high, making it difficult to achieve large size screen. Metal oxide thin film transistor combines the advantages of both amorphous silicon and polysilicon: high mobility 10-120cm ² /Vs, high aperture ratio and low power consumption; compatible with amorphous silicon thin film transistor process, the process is simple and The preparation temperature is lower than 300 °C; the uniformity of the amorphous structure is good, and it is suitable for large-scale high-resolution screens.

However, the metal oxide transparent thin film transistor lacks the corresponding P-type thin film transistor, and can only use the NMOS design method to realize the circuit. At present, the most widely used is to use depletion mode metal oxide transparent thin film transistors and enhancement mode metal oxide transparent thin film transistors to build circuits. How to realize the process compatibility of enhancement mode and depletion mode transistors, and how to modulate the threshold voltage of transistors with the lowest cost and the fastest steps has become a major obstacle for the application of metal oxide transparent thin film transistors in biosensing and flexible electronics. On the other hand, due to many intrinsic defects in metal oxide semiconductor films, including oxygen vacancies, zinc interstitials, etc., as well as grain boundary defects, the electrical properties such as mobility and reliability of the device are reduced. In addition, as next-generation TVs will feature 3840×2160 display panels with ultra-high-definition resolution, or even multi-view naked-eye 3D technology, there is an increasing need for higher-speed thin-film transistors.

SUMMARY OF THE INVENTION

In order to obtain a piezoelectric material with higher piezoelectric constant and electromechanical coupling coefficient, the present invention provides a metal oxide thin film transistor based on plasma treatment of an active layer and a preparation method thereof. The threshold voltage of the metal oxide thin film transistor is modulated by plasma treatment, so that the obtained metal oxide thin film transistor can achieve a wide range of threshold voltage modulation and excellent electrical properties such as high mobility and high stability.

According to a first aspect of the present invention, there is provided a method for preparing a metal oxide thin film transistor based on plasma treatment of an active layer, comprising the following steps:

Step 1, depositing a metal oxide on the substrate to form a semiconductor thin film, and etching it into a semiconductor active layer;

Step 2, depositing a gate insulating layer on the semiconductor active layer, and making the gate insulating layer cover the semiconductor active layer and the substrate;

Step 3, introducing a low-concentration plasma beam through the gate insulating layer to inject it into the semiconductor active layer;

Step 4, depositing a conductive film on the gate insulating layer, and forming a gate electrode after etching, and the gate electrode is located above the middle of the semiconductor active layer;

Step 5. Introduce a high-concentration plasma beam into the semiconductor active layer through the gate insulating layer. The middle of the semiconductor active layer is blocked by the gate electrode and cannot be injected with a high-concentration plasma beam to form a channel region. forming source and drain regions;

Step 6. On the basis of step 5, deposit again to form a passivation insulating layer to protect the entire device;

Step 7, opening lead holes in the passivation insulating layer and the gate insulating layer to expose the gate electrode, the source region and the drain region;

Step 8, depositing metal on each lead hole and etching to form a metal electrode, the metal electrode is located at each lead hole and is respectively connected to the gate electrode, the source region and the drain region,

The deposition method is one of chemical vapor method, physical vapor method, electrochemical method or sol-gel method.

Preferably, the semiconductor active layer is at least one of the following oxides: zinc oxide, indium oxide, copper oxide, tin oxide; or the semiconductor active layer is composed of two or more of the following elements Composition of complex oxides: zinc, indium, tin, gallium, titanium, aluminum, silver or copper.

Preferably, the structure of the metal oxide in the semiconductor active layer is an amorphous, polycrystalline or single crystal structure, and the thickness of the semiconductor active layer is between 10 nm and 2000 nm.

Preferably, the plasma beam contains one or more of hydrogen, deuterium, oxygen, nitrogen, nitrous oxide and other gases.

Preferably, the middle region and the two side regions in the semiconductor source layer are formed by deposition of the same metal oxide; or the middle region and the two side regions in the semiconductor source layer are formed by deposition of different metal oxides.

Preferably, the concentration of doping atoms in the source region and the drain region is greater than 1×10 ²⁰ cm ⁻³ after implanting a plasma beam; the concentration of doping atoms in the channel region after implanting a plasma beam is less than 5 ×10 ¹⁹ cm ^-3 and greater than 1 × 10 ¹² cm ^-3 .

Preferably, the substrate is one of glass, polymer, insulating stainless steel, amorphous silicon, polycrystalline silicon, or monocrystalline silicon containing prefabricated traditional integrated circuits; further, the substrate is Covered with an electrical insulating layer.

Preferably, the conductive thin film is amorphous or polycrystalline metal, transparent conductive oxide, or a combination thereof.

Preferably, the passivation insulating layer and the gate insulating layer are made of silicon dioxide, silicon oxynitride, silicon nitride or insulating materials with high dielectric constant.

According to another aspect of the present invention, a metal oxide thin film transistor is also provided, and the metal oxide thin film transistor is prepared by the above method.

Compared with the prior art, the present invention has the following advantages: using plasma beam processing to modulate the threshold voltage of the metal oxide thin film transistor, realizing a wide range of threshold voltage modulation of the metal oxide thin film transistor, while reducing the source region and the resistivity of the drain region, improve the carrier mobility of the channel region, and then help to improve the on-state current, field-effect mobility and switching speed of the thin film transistor; the process steps are simple, the cost is low, and the consumption can be realized at the same time. Exhaust-mode and enhancement-mode transistors to achieve high-performance NMOS circuits.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a metal oxide thin film transistor of the present invention.

FIG. 2 is a schematic cross-sectional view of the active layer after the pattern is transferred on the substrate.

FIG. 3 is a schematic cross-sectional view of plasma beam implantation after depositing a gate insulating layer on the active layer.

FIG. 4 is a schematic cross-sectional view of ion beam implantation into the source region and the drain region after depositing and etching the gate electrode on the gate insulating layer.

FIG. 5 is a schematic cross-sectional view of the device after opening a lead hole through the gate insulating layer and the passivation insulating layer.

In the figure, 1, substrate; 2, source region; 3, drain region; 4, channel region; 5, gate insulating layer; 6, gate electrode; 7, passivation insulating layer; 8, metal electrode, 9 , photoresist; 10, semiconductor active layer.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to specific embodiments. It should be understood that the following examples are only for illustrating and explaining the present invention, and should not be construed as limiting the protection scope of the present invention. All technologies implemented based on the above content of the present invention are covered within the intended protection scope of the present invention.

Example 1:

Referring to FIG. 2 to FIG. 5 , cross-sectional views of the process flow of the method for preparing a metal oxide thin film transistor based on plasma treatment of an active layer are shown. The specific steps are as follows:

As shown in Figure 1, the metal oxide thin film transistor is formed by plasma processing the active layer, and its structure includes a substrate 1, a source region 2, a drain region 3, a channel region 4, a gate insulating layer 5, a gate Electrode 6 , passivation insulating layer 7 and metal electrode 8 .

As shown in the figure, the substrate 1 is located at the bottom layer, and its materials include but are not limited to the following: polymer, glass, stainless steel, amorphous silicon, polycrystalline silicon or monocrystalline silicon containing prefabricated conventional integrated circuits, the substrate 1 can be Contains an electrically insulating cover.

The source region 2, the drain region 3 and the channel region 4 are the same active layer, and the material of the active layer is a metal oxide semiconductor treated by a plasma beam, wherein the source region 2 and the drain region 3 are subjected to plasma treatment. The concentration of dopant atoms after the bulk beam implantation is higher than that of the channel region 4 . It should be noted that the source region 2 , the drain region 3 and the channel region 4 can be deposited on the substrate 1 by using the same material, or the channel region 4 can be obtained by using the same material as the source region 2 and the drain region 3 Different materials are deposited on the substrate 1 . However, no matter what material is used for deposition, the choice of material is: oxides of zinc, indium, copper or tin, or at least two elements of zinc, tin, indium, gallium, aluminum, titanium, silver and copper. Alloy oxides.

The gate insulating layer 5 covers the active layer and the substrate 1, and is composed of one of silicon dioxide, silicon oxynitride, silicon nitride or insulating materials with high dielectric constant.

The gate electrode 6 is disposed on the gate insulating layer 5 and is located directly above the channel region 4, which can be any metal and metal alloy in amorphous or polycrystalline form, transparent conductive oxide, such as indium tin oxide, doped oxide Zinc etc.

The passivation insulating layer 7 covers the gate electrode 6 and the gate insulating layer 5 , which is also composed of one of silicon dioxide, silicon oxynitride, silicon nitride or insulating materials with high dielectric constant.

The gate insulating layer 5 and the passivation insulating layer 7 are located above the source region 2 and the drain region 3 and are provided with lead holes penetrating the gate insulating layer 5 and the passivation insulating layer 7, and the passivation insulating layer 7 is located on the gate electrode 6. A lead hole penetrating the passivation insulating layer 7 is opened above the lead hole, and a metal electrode 8 is formed in each lead hole by depositing metal and etching.

Referring to FIGS. 2-5 , cross-sectional views of the process flow of the method for preparing a metal oxide thin film transistor based on plasma treatment of an active layer are shown. For a cross-sectional view of the finished product, please refer to FIG. 1 . The specific steps are as follows:

Step 1, depositing a semiconductor thin film with a single crystal structure on the silicon dioxide substrate 1 with zinc oxide, and etching to form a semiconductor active layer 10, the thickness of the semiconductor active layer 10 is 10 nm;

Step 2, depositing a gate insulating layer 5 with silicon oxynitride on the semiconductor source layer, and making the gate insulating layer 5 cover the semiconductor active layer 10 and the substrate 1;

Step 3. Introduce a plasma beam containing low-concentration hydrogen gas through the gate insulating layer 5 to inject it into the semiconductor active layer 10 , and make the dopant atom concentration in the semiconductor active layer 10 reach 1.2×10 ¹³ after injection. cm ^-3 ;

Step 4, adopting indium tin oxide deposition to form a conductive film on the gate insulating layer 5, and forming a gate electrode 6 after etching, and the gate electrode 6 is located above the middle of the semiconductor active layer 10;

Step 5. Introduce a plasma beam containing a high concentration of hydrogen into the semiconductor active layer 10 through the gate insulating layer 5, and the middle of the semiconductor active layer 10 is blocked by the gate electrode 6 and cannot be injected with a high concentration plasma beam to form a channel region 4. The source region 2 and the drain region 3 are respectively formed on both sides of the channel region 4. After the secondary implantation, the dopant atomic concentration of the source region 2 and the drain region 3 reaches 1.2×10 ²⁰ cm ^-3 ;

Step 6. On the basis of step 5, silicon dioxide is deposited again to form a passivation insulating layer 7 to protect the entire device;

Step 7, opening lead holes in the passivation insulating layer 7 and the gate insulating layer 5 to expose the gate electrode 6, the source region 2 and the drain region 3;

Step 8. Deposit copper on each lead hole and etch to form a metal electrode 8. The metal electrode 8 is located at each lead hole and is connected to the gate electrode 6, the source region 2 and the drain region 3 respectively. Process metal oxide thin film transistors for the active layer. The deposition method in the above steps adopts the chemical vapor phase method, and the etching adopts the photoresist 9 for etching.

Example 2:

The process flow of the present embodiment is shown with reference to Example 1, and its specific process steps are as follows:

Step 1, depositing a semiconductor thin film with a polycrystalline structure on the polysilicon substrate 1 with copper oxide, and etching it into a semiconductor active layer 10, the thickness of the semiconductor active layer 10 is 50nm;

Step 2, depositing a gate insulating layer 5 with silicon oxynitride on the semiconductor source layer, and making the gate insulating layer 5 cover the semiconductor active layer 10 and the substrate 1;

Step 3. Introduce a plasma beam containing low-concentration deuterium gas through the gate insulating layer 5 to inject it into the semiconductor active layer 10 , and make the dopant atom concentration in the semiconductor active layer 10 reach 2×10 after injection. ¹³ cm ^-3 ;

Step 4, adopting indium tin oxide deposition to form a conductive film on the gate insulating layer 5, and forming a gate electrode 6 after etching, and the gate electrode 6 is located above the middle of the semiconductor active layer 10;

Step 5. Introduce a plasma beam containing a high concentration of deuterium gas into the semiconductor active layer 10 through the gate insulating layer 5, and the middle of the semiconductor active layer 10 is blocked by the gate electrode 6 and cannot be injected with a high concentration plasma beam to form a channel In region 4, source region 2 and drain region 3 are respectively formed on both sides of channel region 4. After secondary implantation, the dopant atomic concentration of source region 2 and drain region 3 reaches 3×10 ²⁰ cm ^-3 ;

Step 6, on the basis of step 5, deposit silicon dioxide again to form a passivation insulating layer 7 to protect the entire device;

Step 7, opening lead holes in the passivation insulating layer 7 and the gate insulating layer 5 to expose the gate electrode 6, the source region 2 and the drain region 3;

Step 8. Deposit aluminum on each lead hole and etch to form a metal electrode 8. The metal electrode 8 is located at each lead hole and is connected to the gate electrode 6, the source region 2 and the drain region 3 respectively. Process metal oxide thin film transistors for the active layer. The deposition method in the above steps adopts an electrochemical method, and the etching adopts a photoresist 9 for etching.

Example 3:

The process flow of the present embodiment is shown with reference to Example 1, and its specific process steps are as follows:

Step 1, depositing a semiconductor film with a polycrystalline structure on the polysilicon substrate 1 with oxides of copper and silver alloys, and etching to form a semiconductor active layer 10, the thickness of the semiconductor active layer 10 is 500 nm;

Step 2. A gate insulating layer 5 is formed by depositing silicon nitride on the semiconductor source layer, and the gate insulating layer 5 covers the semiconductor active layer 10 and the substrate 1;

Step 3. Introduce a plasma beam containing low-concentration oxygen through the gate insulating layer 5 to inject it into the semiconductor active layer 10 , and make the dopant atom concentration in the semiconductor active layer 10 reach 4×10 ¹⁵ after injection cm ^-3 ;

Step 4, adopting indium tin oxide deposition to form a conductive film on the gate insulating layer 5, and forming a gate electrode 6 after etching, and the gate electrode 6 is located above the middle of the semiconductor active layer 10;

Step 5. Introduce a plasma beam containing a high concentration of oxygen into the semiconductor active layer 10 through the gate insulating layer 5. The middle of the semiconductor active layer 10 is blocked by the gate electrode 6 and cannot be injected with a high concentration plasma beam to form a channel region. 4. The source region 2 and the drain region 3 are respectively formed on both sides of the channel region 4. After the secondary implantation, the dopant atomic concentration of the source region 2 and the drain region 3 reaches 5×10 ²⁰ cm ⁻³ ;

Step 6. On the basis of step 5, deposit silicon nitride again to form a passivation insulating layer 7 to protect the entire device;

Step 7, opening lead holes in the passivation insulating layer 7 and the gate insulating layer 5 to expose the gate electrode 6, the source region 2 and the drain region 3;

Step 8. Deposit copper on each lead hole and etch to form a metal electrode 8. The metal electrode 8 is located at each lead hole and is connected to the gate electrode 6, the source region 2 and the drain region 3 respectively. Process metal oxide thin film transistors for the active layer. The deposition method in the above steps adopts the physical vapor phase method, and the etching adopts the photoresist 9 for etching.

Example 4:

The process flow of the present embodiment is shown with reference to Example 1, and its specific process steps are as follows:

Step 1, depositing a semiconductor film with a polycrystalline structure on the polysilicon substrate 1 with oxides of zinc, indium, and tin alloys, and etching to form a semiconductor active layer 10, the thickness of the semiconductor active layer 10 is 2000 nm;

Step 2, depositing a gate insulating layer 5 with silicon oxynitride on the semiconductor source layer, and making the gate insulating layer 5 cover the semiconductor active layer 10 and the substrate 1;

Step 3. Introduce a plasma beam containing a low concentration of nitrous oxide through the gate insulating layer 5 and inject it into the semiconductor active layer 10. After the injection, the dopant atom concentration in the semiconductor active layer 10 reaches 4.5 ×10 ¹⁹ cm ^-3 ;

Step 4, using doped zinc oxide to deposit on the gate insulating layer 5 to form a conductive film, and after etching to form a gate electrode 6, the gate electrode 6 is located above the middle of the semiconductor active layer 10;

Step 5. Introduce a plasma beam containing a high concentration of nitrous oxide into the semiconductor active layer 10 through the gate insulating layer 5. The semiconductor active layer 10 is blocked by the gate electrode 6 and cannot be injected with a high concentration plasma beam. Channel region 4, source region 2 and drain region 3 are formed on both sides of channel region 4 respectively. After secondary implantation, the dopant atomic concentration of source region 2 and drain region 3 reaches 3×10 ²¹ cm ^-3 ;

Step 6. On the basis of step 5, deposit silicon nitride again to form a passivation insulating layer 7 to protect the entire device;

Step 7, opening lead holes in the passivation insulating layer 7 and the gate insulating layer 5 to expose the gate electrode 6, the source region 2 and the drain region 3;

Step 8. Deposit silver on each lead hole and etch to form a metal electrode 8. The metal electrode 8 is located at each lead hole and is connected to the gate electrode 6, the source region 2 and the drain region 3 respectively. Process metal oxide thin film transistors for the active layer. The deposition method in the above steps adopts the physical vapor phase method, and the etching adopts the photoresist 9 for etching.

The above embodiments respectively provide metal oxide thin film transistors treated with one or more plasmas in hydrogen, deuterium, oxygen, nitrous oxide and other gases, wherein the active layer is a metal oxide containing dopant atoms. material semiconductor. The content and effect of doping atoms in the source and drain regions and the channel region 4 are different: doping the source and drain regions with a high concentration as a donor reduces the source-drain resistance; doping the channel region 4 with a low concentration to modulate the metal oxide film Threshold voltage of transistors and passivated channels reduce defects and improve device performance. Table 1 presents the threshold changes of metal oxide thin film transistors treated with hydrogen, deuterium, oxygen, and nitrous oxide gas plasma.

Table 1

It can be seen from Table 1 that the threshold voltage of the metal oxide transparent thin film transistor is modulated by containing hydrogen, deuterium, oxygen, and nitrous oxide gas plasma to passivate the defects in the metal oxide semiconductor thin film, and a high-performance thin film transistor is prepared. . For example, according to our previous experimental results, the mobility of the hydrogenated zinc oxide thin film transistor can reach up to ~280cm ² /Vs, which is close to the highest Hall mobility of ~300cm ² /Vs currently tested for zinc oxide single crystal materials. The method has simple process steps and low cost, and can simultaneously realize depletion mode and enhancement mode transistors, thereby realizing a high-performance NMOS circuit.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which the present invention pertains can make various modifications or additions to the described specific embodiments or substitute in similar manners, but will not deviate from the spirit of the present invention or go beyond the definition of the appended claims range.

Claims (10)

1. A preparation method of a metal oxide thin film transistor based on plasma processing of an active layer comprises the following steps:

1) depositing a semiconductor film on a substrate (1) by using metal oxide, and etching the semiconductor film into a semiconductor active layer (10);

2) depositing a gate insulating layer (5) on the active semiconductor layer, and enabling the gate insulating layer (5) to cover the semiconductor active layer (10) and the substrate (1);

3) introducing a low-concentration plasma beam through the gate insulating layer (5) so as to be injected into the semiconductor active layer (10);

4) depositing and forming a conductive film on the gate insulating layer (5), and forming a gate electrode (6) after etching, wherein the gate electrode (6) is positioned above the middle part of the semiconductor active layer (10);

5) introducing high-concentration plasma beams to a semiconductor active layer (10) through a gate insulating layer (5), wherein the middle of the semiconductor active layer (10) is blocked by a gate electrode (6) and the high-concentration plasma beams cannot be injected to form a channel region (4), and a source region (2) and a drain region (3) are respectively formed on two sides of the channel region (4);

6) depositing again on the basis of the step 5 to form a passivation insulating layer (7) to protect the whole device;

7) lead holes are formed in the passivation insulating layer (7) and the gate insulating layer (5) to expose the gate electrode (6), the source region (2) and the drain region (3);

8) depositing metal on each lead hole and etching to form a metal electrode (8), wherein the metal electrode (8) is positioned at each lead hole and is respectively connected with the gate electrode (6), the source region (2) and the drain region (3),

the deposition method is one of a chemical vapor method, a physical vapor method, an electrochemical method or a sol-gel method.

2. The method of claim 1, wherein the semiconductor active layer (10) is at least one of the following oxides: zinc oxide, indium oxide, copper oxide, tin oxide; or the semiconductor active layer (10) is a composite oxide composed of two or more of the following elements: zinc, indium, tin, gallium, titanium, aluminum, silver, or copper.

3. The method according to claim 1 or 2, wherein the metal oxide structure in the semiconductor active layer (10) is amorphous, polycrystalline or single crystal, and the thickness of the semiconductor active layer (10) is between 10nm and 2000 nm.

4. The method of claim 1 or 2, wherein the plasma beam comprises one or more of hydrogen, deuterium, oxygen, nitrogen, nitrous oxide, and the like.

5. The method according to claim 1 or 2, wherein the semiconductor source layer is formed by depositing the same metal oxide in the middle region and the two side regions; or the middle area and the two side areas in the semiconductor source layer are formed by deposition of different metal oxides.

6. The method according to claim 1 or 2, wherein the source region (2) and the drain region (3) are doped with ions having a concentration of more than 1 x 10 atoms after the plasma implantation ²⁰ cm ^-3 (ii) a The concentration of post-doped atoms in the channel region (4) is less than 5 x 10 by injecting plasma beams ¹⁹ cm ^-3 And is greater than 1X 10 ¹² cm ^-3 。

7. The method of claim 1 or 2, wherein the substrate (1) is one of glass, polymer, insulating stainless steel, amorphous silicon, polysilicon, or single crystal silicon comprising a prefabricated conventional integrated circuit.

8. The method of claim 1 or 2, wherein the conductive film is an amorphous or polycrystalline form of metal, a transparent conductive oxide, or a combination thereof.

9. The method of claim 1 or 2, wherein the passivation insulating layer (7) and the gate insulating layer (5) are made of one of silicon dioxide, silicon oxynitride, silicon nitride or high-k insulating material.

10. A metal oxide thin film transistor prepared by the method of any one of claims 1 to 9.

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