CN114826962A - Link fault detection method, device, equipment and machine readable storage medium - Google Patents

Abstract

The present disclosure provides a link failure detection method, device, device and machine-readable storage medium, the method includes: judging whether a target PCIE device supports the MCTP protocol; sending a status acquisition command to the target PCIE device supporting the MCTP protocol; trying to receive feedback message, according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device; the feedback message is the feedback message sent by the target PCIE device in response to the state obtaining command after receiving the state obtaining command. arts. Through the technical solution of the present disclosure, a state acquisition command is sent to a PCIE device supporting the MCTP protocol, and whether the PCIE link is faulty or abnormal is determined by means of protocol communication. If the feedback message cannot be received normally, it indicates that the PCIE link is abnormal. The fault detection process is intuitive, convenient and efficient.

Description

A link failure detection method, apparatus, device, and machine-readable storage medium

technical field

The present disclosure relates to the field of communication technologies, and in particular, to a link failure detection method, apparatus, device, and machine-readable storage medium.

Background technique

BMC (Baseboard Management Controller, baseboard management controller), can upgrade the firmware of the machine, view the machine equipment, and other operations when the machine is not turned on.

The Management Component Transport Protocol (MCTP) is a media-independent protocol for intercommunication between intelligent devices within the platform management subsystem of a managed computer system. This protocol is independent of the underlying physical bus and the "data link" layer messages on the bus, that is, only the messages of the transport layer are defined. For the lower transport layer, it is regarded as the transport layer message of its own protocol.

PCIE (PCI-Express, peripheral component interconnect express) is a high-speed serial computer expansion bus standard. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. It mainly supports Active power management, error reporting, end-to-end reliable delivery, hot-plugging, and Quality of Service (QOS) features.

NCSI (Network Controller Sideband Interface) is an industry standard defined by the Distributed Management Task Force for sideband interface network controllers that support out-of-band management of servers.

A solution for a server to detect PCIE anomalies is through the MCA hardware mechanism, and an interrupt or an exception is issued when a hardware error is found. Through MCA, the system can detect hardware errors, such as system bus errors, ECC errors, parity errors, cache errors, TLB errors, etc. The MCA hardware mechanism needs to record and analyze the existing errors in processing, and the process is more complicated , the efficiency is low.

SUMMARY OF THE INVENTION

In view of this, the present disclosure provides a link fault detection method, apparatus, electronic device, and machine-readable storage medium to improve the above problem of low fault detection efficiency.

The specific technical solutions are as follows:

The present disclosure provides a link failure detection method, which is applied to a BMC device. The method includes: judging whether a target PCIE device supports the MCTP protocol; sending a status acquisition command to the target PCIE device supporting the MCTP protocol; trying to receive a feedback message, According to the result of receiving the feedback message, the state of the PCIE link associated with the target PCIE device is determined; the feedback message is the feedback message sent by the target PCIE device in response to the state obtaining command after receiving the state obtaining command.

As a technical solution, the state acquisition command is sent to the target PCIE device supporting the MCTP protocol, an attempt is made to receive a feedback message, and the state of the PCIE link associated with the target PCIE device is judged according to the result of receiving the feedback message, including: If receiving the feedback message fails, the step of sending the status acquisition command to the target PCIE device supporting the MCTP protocol is performed again after a preset delay, and the result of the failure to receive the feedback message this time is recorded; if the recorded failure to receive the feedback message fails If the result reaches a specified number of times, it is judged that the state of the PCIE link associated with the target PCIE device is abnormal.

As a technical solution, the sending a state acquisition command to a target PCIE device supporting the MCTP protocol includes: encapsulating a packet of a specified protocol containing the state acquisition command through the MCTP protocol, and sending the packet to the target PCIE device supporting the MCTP protocol. The specified protocol includes NCSI protocol or PLDM protocol or VDM protocol.

As a technical solution, the attempt to receive the feedback message, according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device, including: if judging the state of the PCIE link associated with the target PCIE device If abnormal, report to the police.

The present disclosure also provides a link failure detection device, which is applied to a BMC device. The device includes: a protocol module for judging whether a target PCIE device supports the MCTP protocol; a command module for sending the target PCIE device supporting the MCTP protocol to the target PCIE device. Sending a state acquisition command; the processing module is used to attempt to receive a feedback message, and according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device; the feedback message is the state of the target PCIE device receiving the message After obtaining the command, the feedback message sent in response to the state obtaining command.

As a technical solution, the state acquisition command is sent to the target PCIE device supporting the MCTP protocol, an attempt is made to receive a feedback message, and the state of the PCIE link associated with the target PCIE device is judged according to the result of receiving the feedback message, including: If receiving the feedback message fails, the step of sending the status acquisition command to the target PCIE device supporting the MCTP protocol is performed again after a preset delay, and the result of the failure to receive the feedback message this time is recorded; if the recorded failure to receive the feedback message fails If the result reaches a specified number of times, it is judged that the state of the PCIE link associated with the target PCIE device is abnormal.

As a technical solution, the sending a state acquisition command to a target PCIE device supporting the MCTP protocol includes: encapsulating a packet of a specified protocol containing the state acquisition command through the MCTP protocol, and sending the packet to the target PCIE device supporting the MCTP protocol. The specified protocol includes NCSI protocol or PLDM protocol or VDM protocol.

As a technical solution, the attempt to receive the feedback message, according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device, including: if judging the state of the PCIE link associated with the target PCIE device If abnormal, report to the police.

The present disclosure also provides an electronic device including a processor and a machine-readable storage medium, where the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions. instructions to implement the aforementioned link failure detection method.

The present disclosure also provides a machine-readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the machine-executable instructions to cause all The processor implements the aforementioned link failure detection method.

The above-mentioned technical solutions provided by the present disclosure bring at least the following beneficial effects:

Send a status acquisition command to the PCIE device that supports the MCTP protocol, and determine whether the PCIE link is faulty or abnormal by means of protocol communication. If the feedback message cannot be received normally, it means that the PCIE link is abnormal, which simplifies the fault detection process and is intuitive and convenient. and efficient.

Description of drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments of the present disclosure or the prior art. Obviously, the drawings in the following description These are just some embodiments described in the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained according to these drawings of the embodiments of the present disclosure.

1 is a flowchart of a method for detecting a link failure in an embodiment of the present disclosure;

FIG. 2 is a structural diagram of a link failure detection device in an embodiment of the present disclosure;

FIG. 3 is a hardware structure diagram of an electronic device in an embodiment of the present disclosure.

Detailed ways

The terminology used in the embodiments of the present disclosure is for the purpose of describing particular embodiments only, and not for the purpose of limiting the present disclosure. As used in this disclosure and the claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present disclosure. Furthermore, the use of the word "if" can be interpreted as "at the time of" or "when" or "in response to determining", depending on the context.

The present disclosure provides a link fault detection method, device, electronic device, and machine-readable storage medium to improve the above problem of low fault detection efficiency.

Specific technical solutions are described later.

In one embodiment, the present disclosure provides a link failure detection method, applied to a BMC device, the method includes: judging whether a target PCIE device supports the MCTP protocol; sending a status acquisition command to the target PCIE device supporting the MCTP protocol ; Attempt to receive the feedback message, according to the result of receiving the feedback message, judge the state of the PCIE link associated with the target PCIE device; Described feedback message is that the target PCIE device receives the state acquisition order in response to the state acquisition order Feedback message sent.

Specifically, as shown in Figure 1, the following steps are included:

Step S11, judging whether the target PCIE device supports the MCTP protocol;

Step S12, sending a state acquisition command to the target PCIE device supporting the MCTP protocol;

Step S13, try to receive the feedback message, and judge the state of the PCIE link associated with the target PCIE device according to the result of receiving the feedback message.

Send a status acquisition command to the PCIE device that supports the MCTP protocol, and determine whether the PCIE link is faulty or abnormal by means of protocol communication. If the feedback message cannot be received normally, it means that the PCIE link is abnormal, which simplifies the fault detection process and is intuitive and convenient. and efficient.

In one embodiment, the state acquisition command is sent to the target PCIE device supporting the MCTP protocol, an attempt is made to receive a feedback message, and the state of the PCIE link associated with the target PCIE device is determined according to the result of receiving the feedback message, including : If receiving the feedback message fails, re-execute the step of sending a status acquisition command to the target PCIE device supporting the MCTP protocol after a preset delay, and record the result of the failure to receive the feedback message this time; If the result of failure reaches the specified number of times, it is judged that the state of the PCIE link associated with the target PCIE device is abnormal.

In one embodiment, the sending the status acquisition command to the target PCIE device supporting the MCTP protocol includes: encapsulating a packet of the specified protocol that contains the status acquisition command through the MCTP protocol, and sending the status acquisition command to the target PCIE device supporting the MCTP protocol. message; the specified protocol includes NCSI protocol, PLDM protocol or VDM protocol.

In one embodiment, the attempt to receive the feedback message, according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device, including: if judging the status of the PCIE link associated with the target PCIE device If the status is abnormal, an alarm will be reported.

In an implementation manner, the BMC is connected to the PCH through a PCIE bus, the PCH is connected to a PCIE bus controller of the CPU, and a PCIE device is attached to the CPU. The BMC communicates with the PCIE device through the PCIE link. The BMC encapsulates NCSI or PLDM or VDM protocol packets on the basis of protocol packets, and then sends the packets to the PCH through the PCIE link. The PCH forwards the packets to the device through the PCIE controller. will be processed and the response passed to the BMC.

Take a network card that supports NCSI OVER MCTP protocol as an example, firstly, BMC will set EID (endpoint ID) for each network card as its own identity number; then BMC will send NCSI OVER MCTP status acquisition command to network card, such as sending to get network card link status After receiving the command, the network card responds to the BMC through the PCIE link. If the link status of the responding port is up or down, the BMC can determine that the PCIE link and device are normal after receiving the response from the network card. During this process, if the PCIE link is abnormal or the PCIE device is abnormal, the command interaction process will fail, that is, the feedback message cannot be received. In order to avoid misjudgment caused by link flapping, you can confirm the abnormality of the link or device through the failure of multiple MCTP command exchanges. Repeat three times, if the feedback message cannot be received normally three times, it is considered that the PCIE link is abnormal.

In an embodiment, the present disclosure also provides a link failure detection apparatus, as shown in FIG. 2 , which is applied to a BMC device. The apparatus includes: a protocol module 21 for judging whether the target PCIE device supports the MCTP protocol; a command The module 22 is used to send a state acquisition command to the target PCIE device supporting the MCTP protocol; the processing module 23 is used to attempt to receive the feedback message, and judge the state of the PCIE link associated with the target PCIE device according to the result of receiving the feedback message ; The feedback message is a feedback message sent by the target PCIE device in response to the status acquisition command after receiving the status acquisition command.

In one embodiment, the state acquisition command is sent to the target PCIE device supporting the MCTP protocol, an attempt is made to receive a feedback message, and the state of the PCIE link associated with the target PCIE device is determined according to the result of receiving the feedback message, including : If receiving the feedback message fails, re-execute the step of sending a status acquisition command to the target PCIE device supporting the MCTP protocol after a preset delay, and record the result of the failure to receive the feedback message this time; If the result of failure reaches the specified number of times, it is judged that the state of the PCIE link associated with the target PCIE device is abnormal.

In one embodiment, the sending the status acquisition command to the target PCIE device supporting the MCTP protocol includes: encapsulating a packet of the specified protocol that contains the status acquisition command through the MCTP protocol, and sending the status acquisition command to the target PCIE device supporting the MCTP protocol. message; the specified protocol includes NCSI protocol, PLDM protocol or VDM protocol.

In one embodiment, the attempt to receive the feedback message, according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device, including: if judging the status of the PCIE link associated with the target PCIE device If the status is abnormal, an alarm will be reported.

The device implementation is the same as or similar to the corresponding method implementation, and details are not described herein again.

In one embodiment, the present disclosure provides an electronic device including a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor The machine-executable instructions are executed to implement the foregoing link failure detection method. From a hardware level, a schematic diagram of a hardware architecture can be referred to as shown in FIG. 3 .

In one embodiment, the present disclosure provides a machine-readable storage medium storing machine-executable instructions that when invoked and executed by a processor, the Machine-executable instructions cause the processor to implement the aforementioned link failure detection method.

Here, a machine-readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: RAM (Radom Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk ( such as optical discs, DVDs, etc.), or similar storage media, or a combination thereof.

The systems, devices, modules or units described in the above embodiments may be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementing device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smart phone, personal digital assistant, media player, navigation device, email sending and receiving device, game control desktop, tablet, wearable device, or a combination of any of these devices.

For the convenience of description, when describing the above device, the functions are divided into various units and described respectively. Of course, when implementing the present disclosure, the functions of each unit may be implemented in one or more software and/or hardware.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware implementation, an entirely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, CD-ROM, optical storage, and the like.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

Furthermore, these computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer readable memory result in an article of manufacture comprising the instruction means, The instruction means implements the functions specified in a flow or flows of the flowcharts and/or a block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware implementation, an entirely software implementation, or an implementation combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The above descriptions are merely embodiments of the present disclosure, and are not intended to limit the present disclosure. Various modifications and variations of the present disclosure will occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included within the scope of the claims of the present disclosure.

Claims (10)

1. a link failure detection method, is characterized in that, is applied to BMC equipment, and described method comprises: Determine whether the target PCIE device supports the MCTP protocol; Send a status acquisition command to the target PCIE device that supports the MCTP protocol; Attempt to receive the feedback message, and judge the state of the PCIE link associated with the target PCIE device according to the result of receiving the feedback message; The feedback message is a feedback message sent by the target PCIE device in response to the state obtaining command after receiving the state obtaining command. 2. method according to claim 1, is characterized in that, described to the target PCIE equipment that supports MCTP agreement to send state acquisition order, try to receive feedback message, according to the result of receiving feedback message, judge to be related to target PCIE equipment The status of the PCIE link, including: If receiving the feedback message fails, re-execute the step of sending a status acquisition command to the target PCIE device supporting the MCTP protocol after a preset delay, and record the result of the failure to receive the feedback message this time; If the recorded result of receiving the feedback message failure reaches the specified number of times, it is determined that the state of the PCIE link associated with the target PCIE device is abnormal. 3. method according to claim 1, is characterized in that, described to the target PCIE equipment that supports MCTP agreement sends state acquisition order, comprises: Encapsulate the message of the specified protocol containing the state acquisition command through the MCTP protocol, and send the message to the target PCIE device supporting the MCTP protocol; The specified protocol includes NCSI protocol, PLDM protocol or VDM protocol. 4. The method according to claim 1, wherein the attempt to receive the feedback message, according to the result of receiving the feedback message, judges the state of the PCIE link associated with the target PCIE device, comprising: If it is determined that the state of the PCIE link associated with the target PCIE device is abnormal, an alarm is reported. 5. A link failure detection device, characterized in that, applied to BMC equipment, the device comprising: The protocol module is used to judge whether the target PCIE device supports the MCTP protocol; The command module is used to send a status acquisition command to the target PCIE device supporting the MCTP protocol; The processing module is used to try to receive the feedback message, and according to the result of receiving the feedback message, determine the state of the PCIE link associated with the target PCIE device; The feedback message is a feedback message sent by the target PCIE device in response to the state obtaining command after receiving the state obtaining command. 6. device according to claim 5, is characterized in that, described to the target PCIE equipment that supports MCTP agreement to send state acquisition order, attempt to receive feedback message, according to the result of receiving feedback message, judge to be related to target PCIE equipment The status of the PCIE link, including: If receiving the feedback message fails, re-execute the step of sending a status acquisition command to the target PCIE device supporting the MCTP protocol after a preset delay, and record the result of the failure to receive the feedback message this time; If the recorded result of receiving the feedback message failure reaches the specified number of times, it is determined that the state of the PCIE link associated with the target PCIE device is abnormal. 7. device according to claim 5, is characterized in that, described to the target PCIE equipment that supports MCTP agreement sends the state acquisition command, comprises: Encapsulate the message of the specified protocol containing the state acquisition command through the MCTP protocol, and send the message to the target PCIE device supporting the MCTP protocol; The specified protocol includes NCSI protocol, PLDM protocol or VDM protocol. 8. The device according to claim 5, wherein the attempt to receive the feedback message, according to the result of receiving the feedback message, judges the state of the PCIE link associated with the target PCIE device, comprising: If it is determined that the state of the PCIE link associated with the target PCIE device is abnormal, an alarm is reported. 9. An electronic device, comprising: a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the The machine-executable instructions to implement the method of any one of claims 1-4. 10. A machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the machine-executable instructions to The processor implements the method of any one of claims 1-4.

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