CN114758891A - Encapsulating lead Y-type capacitor and preparation method thereof - Google Patents
Encapsulating lead Y-type capacitor and preparation method thereof Download PDFInfo
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- CN114758891A CN114758891A CN202210534059.3A CN202210534059A CN114758891A CN 114758891 A CN114758891 A CN 114758891A CN 202210534059 A CN202210534059 A CN 202210534059A CN 114758891 A CN114758891 A CN 114758891A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/224—Housing; Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
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- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
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- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
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Abstract
本发明提供一种灌封引线Y型电容器及其制备方法,包括间隔布置的两芯片组、公共引线、两单独引线、第一绝缘层、外壳、固定机构和灌封胶,两芯片间隔并排布置,芯片组包括至少一个陶瓷芯片,一芯片组的所有陶瓷芯片的位于同一侧的导电端导电连接形成总导电端,共用引线与两芯片组的位于同一侧的两总导电端连接,两单独引线分别与两芯片组另一总导电端连接,第一绝缘层设置在两芯片组之间以绝缘隔离两芯片组,两芯片组置于外壳内,公共引线和两单独引线伸出外壳外,固定机构设置在公共引线及两单独引线与外壳之间,灌封胶设置在芯片组与外壳之间。本发明能够实现抑制共模干扰的作用,且可靠性高,机械性能强,抗震性强,能够满足批量生产需求。
The invention provides a potting lead Y-type capacitor and a preparation method thereof, comprising two chip groups arranged at intervals, a common lead, two separate leads, a first insulating layer, a casing, a fixing mechanism and a potting glue, and the two chips are arranged side by side at intervals , the chip set includes at least one ceramic chip, the conductive terminals on the same side of all the ceramic chips of a chip set are conductively connected to form a total conductive terminal, the common lead is connected with the two total conductive terminals on the same side of the two chip sets, and the two separate leads It is respectively connected with the other general conductive end of the two chip sets. The first insulating layer is arranged between the two chip sets to isolate the two chip sets. The two chip sets are placed in the casing. The common lead and the two individual leads extend out of the casing and are fixed. The mechanism is arranged between the common lead and the two individual leads and the casing, and the potting glue is arranged between the chip set and the casing. The invention can realize the function of suppressing common mode interference, and has high reliability, strong mechanical performance and strong shock resistance, and can meet the needs of mass production.
Description
技术领域technical field
本发明涉及一种灌封引线Y型电容器及其制备方法。The invention relates to a potting lead Y-type capacitor and a preparation method thereof.
背景技术Background technique
现有技术中,如图1所示,共模干扰抑制电路为两串接的电容,两电容的自由端与电源连接,公共端则接地。但在实际使用中,设计PCB板时,有时会因为共模干扰抑制电路而导致整个电路设计变得复杂。再者,在使用过程中,可能因环境原因导致电路发生损坏,从而影响共模干扰抑制电路的可靠性,且其防震性能较差,在极端环境中极易损坏而失去作用。In the prior art, as shown in FIG. 1 , the common mode interference suppression circuit is two capacitors connected in series, the free ends of the two capacitors are connected to the power supply, and the common end is grounded. However, in actual use, when designing a PCB board, sometimes the entire circuit design becomes complicated due to the common mode interference suppression circuit. Furthermore, during use, the circuit may be damaged due to environmental reasons, thereby affecting the reliability of the common mode interference suppression circuit, and its shockproof performance is poor, and it is easily damaged and loses its function in extreme environments.
发明内容SUMMARY OF THE INVENTION
本发明提出一种灌封引线Y型电容器及其制备方法,能够实现抑制共模干扰的作用,且可靠性高,机械性能强,抗震性强,能够满足批量生产需求。The invention provides a potting lead Y-type capacitor and a preparation method thereof, which can realize the function of suppressing common mode interference, and have high reliability, strong mechanical performance and strong shock resistance, and can meet the needs of mass production.
本发明通过以下技术方案实现:The present invention is achieved through the following technical solutions:
一种灌封引线Y型电容器,包括间隔布置的两芯片组、公共引线、两单独引线、第一绝缘层、外壳、固定机构和灌封胶,两芯片间隔并排布置,芯片组包括至少一个陶瓷芯片,一芯片组的所有陶瓷芯片的位于同一侧的导电端导电连接形成总导电端,共用引线与两芯片组的位于同一侧的两总导电端连接,两单独引线分别与两芯片组另一总导电端连接,第一绝缘层设置在两芯片组之间以绝缘隔离两芯片组,两芯片组置于外壳内,公共引线和两单独引线伸出外壳外,固定机构设置在公共引线及两单独引线与外壳之间,灌封胶设置在芯片组与外壳之间。A potting lead Y-type capacitor, comprising two chip sets arranged at intervals, a common lead, two separate leads, a first insulating layer, a casing, a fixing mechanism and a potting glue, the two chips are arranged side by side at intervals, and the chip set comprises at least one ceramic Chip, the conductive terminals on the same side of all the ceramic chips of a chip set are conductively connected to form a total conductive terminal, the common lead is connected to the two general conductive terminals on the same side of the two chip sets, and the two separate leads are respectively connected to the other two chip sets. The main conductive terminals are connected, the first insulating layer is arranged between the two chip groups to isolate the two chip groups, the two chip groups are placed in the casing, the common lead and the two individual leads extend out of the casing, and the fixing mechanism is arranged on the common lead and the two chip groups. Between the individual leads and the casing, the potting glue is arranged between the chip set and the casing.
进一步的,所述两芯片组位于同一侧的两总导电端上设置有第一铜片,所述公共引线一端焊接在第一铜片上。Further, a first copper sheet is provided on the two general conductive ends of the two chip sets on the same side, and one end of the common lead is welded on the first copper sheet.
进一步的,所述外壳上端具有开口、下端设置有供公共引线和两单独引线穿出的让位孔,所述固定机构包括设置在公共引线、两单独引线上与让位孔对应位置的红胶。Further, the upper end of the casing has an opening, and the lower end is provided with a hole for the common lead and the two separate leads to pass through, and the fixing mechanism includes a red glue that is arranged on the common lead and the two separate leads and the corresponding positions of the give-away holes. .
进一步的,所述外壳由高强度绝缘且耐高温高压材料制成。Further, the housing is made of high-strength insulating and high temperature and high pressure resistant materials.
进一步的,还包括第二绝缘层,所述陶瓷芯片包括两导电端和设置在两导电端之间的瓷体,第二绝缘层设置在瓷体外周。Further, it also includes a second insulating layer, the ceramic chip includes two conductive ends and a porcelain body disposed between the two conductive ends, and the second insulating layer is disposed on the periphery of the porcelain body.
进一步的,所述第二绝缘层为涂覆在瓷体外周的绝缘漆。Further, the second insulating layer is insulating paint coated on the periphery of the porcelain body.
进一步的,所述第一绝缘层为由聚酰亚胺材料制成的矩形片,该矩形片面积不小于陶瓷芯片面积,该矩形片厚度不小于1mm。Further, the first insulating layer is a rectangular sheet made of polyimide material, the area of the rectangular sheet is not less than the area of the ceramic chip, and the thickness of the rectangular sheet is not less than 1 mm.
本发明还通过以下技术方案实现:The present invention also realizes through the following technical solutions:
一种灌封引线Y型电容器的制备方法,先在两芯片组之间设置第一绝缘层,然后使公共引线与两芯片组位于同一侧的两总导电端连接、分别将两单独引线与两芯片组的另一总导电端连接,再将芯片组置于外壳内并使公共引线和单独引线穿出外壳,并在芯片组与外壳之间导入灌封胶固化。A preparation method of a potted lead Y-type capacitor. First, a first insulating layer is arranged between two chip groups, and then a common lead is connected to two general conductive terminals on the same side of the two chip groups. The other general conductive end of the chip set is connected, and then the chip set is placed in the casing, the common lead and the individual lead are passed out of the casing, and a potting glue is introduced between the chip set and the casing to cure.
本发明具有如下有益效果:The present invention has the following beneficial effects:
1、本发明首先在两芯片组之间设置第一绝缘层,以确保两芯片组绝缘隔离,然后分别使公共引线与两芯片组位于同一侧的两总导电端连接、分别将两单独引线与两芯片组的另一总导电端连接,再将芯片置于外壳内并使公共引线和单独引线穿出外壳,并在芯片组与外壳之间导入灌封胶固化,使用时,将两单独引线与电源连接,共用引线接地,即可实现抑制共模干扰的作用;本发明为模块化设计,将共模干扰一直电路集成为一个电容器模块,使用时进行简单的焊接操作即可,使PCB板的设计更为简单;在公共引线、两单独引线与外壳之间设置有固定机构,能够使焊接后公共引线和单独引线后的两芯片组固定在外壳内,在芯片组与壳体之间导入灌封胶,能够提高本发明的可靠性、极性性能和抗震性能;本发明的陶瓷芯片为市场标配的陶瓷芯片,使用时,可根据具体使用情况选择芯片组所包含的陶瓷芯片的数量,从而得到适合的电容量,适配性强,也能够满足批量生产需求。1. In the present invention, a first insulating layer is firstly arranged between the two chip groups to ensure insulation isolation of the two chip groups, and then the common lead is connected to the two general conductive terminals on the same side of the two chip groups respectively, and the two individual leads are connected to the two chip groups respectively. The other general conductive ends of the two chip sets are connected, and then the chip is placed in the casing and the common lead and the individual lead are passed out of the casing, and the potting glue is introduced between the chip set and the casing to cure. It is connected to the power supply and the common lead is grounded to realize the function of suppressing the common mode interference; the present invention is a modular design, and the common mode interference circuit is integrated into a capacitor module, and a simple welding operation can be performed during use to make the PCB board The design is simpler; a fixing mechanism is arranged between the common lead, the two individual leads and the casing, so that the two chip sets after the welding of the common lead and the independent lead can be fixed in the casing, and the chip set and the casing can be introduced between the chip set and the casing. The potting compound can improve the reliability, polarity performance and anti-vibration performance of the present invention; the ceramic chip of the present invention is a standard ceramic chip in the market. When using, the number of ceramic chips included in the chip set can be selected according to the specific use situation. , so as to obtain suitable capacitance, strong adaptability, and can also meet the needs of mass production.
附图说明Description of drawings
下面结合附图对本发明做进一步详细说明。The present invention will be further described in detail below in conjunction with the accompanying drawings.
图1为现有技术中的共模干扰抑制电路图。FIG. 1 is a circuit diagram of a common mode interference suppression circuit in the prior art.
图2为本发明的结构示意图。FIG. 2 is a schematic structural diagram of the present invention.
图3为本发明的分解机构示意图。FIG. 3 is a schematic diagram of the decomposition mechanism of the present invention.
图4为本发明去除外壳与灌封胶之后的结构示意图。FIG. 4 is a schematic structural diagram of the present invention after removing the casing and the potting glue.
其中,11、导电端;2、公共引线;21、第一铜片;3、单独引线;4、第一绝缘层;5、第二绝缘层;6、外壳;61、开口;7、灌封胶;8、红胶。Among them, 11, conductive end; 2, common lead; 21, first copper sheet; 3, individual lead; 4, first insulating layer; 5, second insulating layer; 6, shell; 61, opening; 7, potting Glue; 8. Red glue.
具体实施方式Detailed ways
如图2至图4所示,灌封引线Y型电容器包括间隔布置的两芯片组、公共引线2、两单独引线3、第一绝缘层4、第二绝缘层5、外壳6、固定机构和灌封胶7。在本实施例中,芯片组包括一个陶瓷芯片,陶瓷芯片包括两导电端11和设置在两导电端11之间的瓷体。陶瓷芯片的导电端11即为芯片组的总导电端,两陶瓷芯片位于同一侧的两导电端11上设置有第一铜片21,以使该两导电端11导电连接。共用引线上端则焊接在该第一铜片21上,两单独引线3上端分别与两陶瓷芯片另一导电端11焊接,两陶瓷芯片间隔并排布置。第一绝缘层4设置在两陶瓷芯片之间以隔离两陶瓷芯片。第二绝缘层5为涂覆在瓷体外周的绝缘漆,以进一步确保两陶瓷芯片不会接触短路。焊接公共引线2和两单独引线3的两陶瓷芯片置于外壳6内,公共引线2和两单独引线3伸出外壳6外。固定机构则设置在公共引线2与外壳6之间、两单独引线3与外壳6之间。灌封胶7则设置在陶瓷芯片与外壳6之间。As shown in FIGS. 2 to 4 , the potted lead Y-type capacitor includes two chip groups arranged at intervals, a
在另一实施例中,芯片组包括多个陶瓷芯片,多个陶瓷芯片位于同一侧的导电端11导电连接形成总导电端,位于同一侧的各导电端11的导电连接可通过设置在这些导电端11上的第二铜片实现。共用引线与两芯片组的位于同一侧的两总导电端连接,两单独引线3分别与两芯片组另一总导电端连接,两芯片间隔并排布置,第一绝缘层4设置在两芯片组之间,两芯片组置于外壳6内,各芯片组的各个陶瓷芯片的瓷体外周均涂覆有绝缘漆,公共引线2和两单独引线3伸出外壳6外,固定机构设置在公共引线2及两单独引线3与外壳6之间,灌封胶7设置在芯片组与外壳6之间。In another embodiment, the chip set includes a plurality of ceramic chips, and the conductive terminals 11 of the plurality of ceramic chips on the same side are conductively connected to form a total conductive terminal, and the conductive connections of the conductive terminals 11 on the same side The second copper sheet on the end 11 is realized. The common lead is connected to the two general conductive ends of the two chip sets on the same side, the two
外壳6由高强度绝缘且耐高温高压材料制成,具体可采用聚苯并咪唑PBI。壳体设置为空心长方体,为了方便陶瓷芯片的放入,该长方体上端设置有开口61,而下端则设置有供公共引线2和两单独引线3穿出的让位孔,固定机构则包括设置在公共引线2、两单独引线3上与让位孔对应位置的红胶8。The
在本实施例中,第一绝缘层4为由聚酰亚胺材料制成的矩形片,该矩形片面积不小于陶瓷芯片面积,该矩形片厚度为不小于1mm,以保证产品的绝缘强度。In this embodiment, the first insulating layer 4 is a rectangular sheet made of polyimide material, the area of the rectangular sheet is not less than that of the ceramic chip, and the thickness of the rectangular sheet is not less than 1 mm to ensure the insulation strength of the product.
灌封引线Y型电容器的制备方法为:在陶瓷芯片的瓷体外周涂覆第一绝缘层4,然后在两芯片组之间设置第一绝缘层4,接着使公共引线2与两芯片组位于同一侧的两总导电端连接、分别将两单独引线3与两芯片组的另一总导电端连接,再将芯片组置于外壳6内并使公共引线2和单独引线3穿出外壳6,并在芯片组与外壳6之间导入灌入灌封胶7固化。The preparation method of the potted lead Y-type capacitor is as follows: coating a first insulating layer 4 on the periphery of the porcelain body of the ceramic chip, then disposing the first insulating layer 4 between the two chip groups, and then placing the
以上所述,仅为本发明的较佳实施例而已,故不能以此限定本发明实施的范围,即依本发明申请专利范围及说明书内容所作的等效变化与修饰,皆应仍属本发明专利涵盖的范围内。The above descriptions are only the preferred embodiments of the present invention, and therefore cannot limit the scope of the present invention. That is, equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the description should still belong to the present invention. covered by the patent.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020048139A1 (en) * | 2000-09-08 | 2002-04-25 | Avx Corporation | Non-polarized tantalum capacitor and capacitor array |
| CN112349513A (en) * | 2019-08-08 | 2021-02-09 | Tdk株式会社 | Conductive terminal and electronic component |
| CN217719331U (en) * | 2022-05-17 | 2022-11-01 | 福建火炬电子科技股份有限公司 | Y-shaped capacitor with encapsulated lead |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020048139A1 (en) * | 2000-09-08 | 2002-04-25 | Avx Corporation | Non-polarized tantalum capacitor and capacitor array |
| CN112349513A (en) * | 2019-08-08 | 2021-02-09 | Tdk株式会社 | Conductive terminal and electronic component |
| CN217719331U (en) * | 2022-05-17 | 2022-11-01 | 福建火炬电子科技股份有限公司 | Y-shaped capacitor with encapsulated lead |
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Application publication date: 20220715 |